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  1. module test(input clk,
  2. input reset,
  3. output reg[3:0] ledss
  4.  
  5. );
  6.  
  7. integer i=0;
  8.  
  9. wire[31:0] dataread;
  10. reg[31:0] datawrite=0;
  11. reg wren=0;
  12. reg[31:0] address=0;
  13.  
  14.  
  15.  ramm ram(.address(address),
  16.             .clock(clk),
  17.             .data(datawrite),
  18.             .wren(wren),
  19.             .q(dataread)
  20.             ); //
  21.  
  22. always @(posedge clk )
  23. begin
  24.  
  25. if(i==2)
  26.     begin
  27.                     case(dataread)
  28.                          
  29.                          32'b11111111111111111111111111111111:ledss<=4'b0110;
  30.                    
  31.                     endcase
  32.     end
  33.  
  34. if(i!=3)
  35.     i=i+1;
  36. end
  37. endmodule
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