module zad4(
input [1:0]SW,
output [2:0]LEDR);

FDD_clk a(SW[0],SW[1],LEDR[0]);
FDD_posedge b(SW[0],SW[1],LEDR[1]);
FDD_negedge c (SW[0],SW[1],LEDR[2]);


endmodule



module FDD_clk(
	input D,Clk,
	output reg Q);

	always @(*)
		if (Clk) 		Q=D;
endmodule

module FDD_posedge(
	input D,clk,
	output reg Q);

	always@(posedge clk)
	Q<=D;

endmodule

module FDD_negedge(
	input D,clk,
	output reg Q);

	always @(negedge clk)
	Q<=D;
endmodule