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Saturn target synthesis

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  1. python3 -m misoc.targets.saturn --integrated-rom-size 20000
  2. fvco (MHz) = 1000
  3. n= 10
  4. d= 1
  5. clk_freq (parameter) = 62.5
  6. clk_freq (f0*n/d/p/2) = 62.5
  7. sdram_half (f0*n/d/p) = 125.0
  8. sdram_full_wr (2*f0*n/d/p) = 250.0
  9. sdram_full_rd (2*f0*n/d/p) = 250.0
  10. make: Entering directory '/home/fevi8970/misoc_basesoc_saturn/software/bios'
  11. CC sdram.o
  12. CC main.o
  13. LD bios.elf
  14. OBJCOPY bios.bin
  15. make: Leaving directory '/home/fevi8970/misoc_basesoc_saturn/software/bios'
  16. Release 14.7 - xst P.20131013 (nt64)
  17. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  18. --> WARNING:Xst:1583 - You are using an internal switch '-use_new_parser'.
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Parsing
  23. 3) HDL Elaboration
  24. 4) HDL Synthesis
  25. 4.1) HDL Synthesis Report
  26. 5) Advanced HDL Synthesis
  27. 5.1) Advanced HDL Synthesis Report
  28. 6) Low Level Synthesis
  29. 7) Partition Report
  30. 8) Design Summary
  31. 8.1) Primitive and Black Box Usage
  32. 8.2) Device utilization summary
  33. 8.3) Partition Resource Summary
  34. 8.4) Timing Report
  35. 8.4.1) Clock Information
  36. 8.4.2) Asynchronous Control Signals Information
  37. 8.4.3) Timing Summary
  38. 8.4.4) Timing Details
  39. 8.4.5) Cross Clock Domains Report
  40.  
  41.  
  42. =========================================================================
  43. * Synthesis Options Summary *
  44. =========================================================================
  45. ---- Source Parameters
  46. Input File Name : "top.prj"
  47. Input Format : MIXED
  48. Verilog Include Directory : D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog
  49.  
  50. ---- Target Parameters
  51. Output File Name : "top.ngc"
  52. Target Device : xc6slx45-2csg324
  53.  
  54. ---- Source Options
  55. Top Module Name : top
  56. Use New Parser : yes
  57. Automatic Register Balancing : yes
  58.  
  59. ---- General Options
  60. Optimization Goal : SPEED
  61.  
  62. =========================================================================
  63.  
  64. WARNING:Xst:29 - Optimization Effort not specified
  65. =========================================================================
  66.  
  67. =========================================================================
  68. * HDL Parsing *
  69. =========================================================================
  70. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_logic_op.v" into library work
  71. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 50.
  72. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog/lm32_config.v" included at line 61.
  73. WARNING:HDLCompiler:1591 - "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog/lm32_config.v" Line 186: Root scope declaration is not allowed in verilog 95/2K mode
  74. Parsing module <lm32_logic_op>.
  75. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_icache.v" into library work
  76. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 57.
  77. Parsing module <lm32_icache>.
  78. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_itlb.v" into library work
  79. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 32.
  80. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_decoder.v" into library work
  81. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 56.
  82. Parsing module <lm32_decoder>.
  83. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_dtlb.v" into library work
  84. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 32.
  85. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_load_store_unit.v" into library work
  86. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 63.
  87. Parsing module <lm32_load_store_unit>.
  88. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_dcache.v" into library work
  89. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 52.
  90. Parsing module <lm32_dcache>.
  91. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_addsub.v" into library work
  92. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 49.
  93. Parsing module <lm32_addsub>.
  94. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_debug.v" into library work
  95. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 53.
  96. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_adder.v" into library work
  97. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 50.
  98. Parsing module <lm32_adder>.
  99. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_ram.v" into library work
  100. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 55.
  101. Parsing module <lm32_ram>.
  102. Analyzing Verilog file "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" into library work
  103. Parsing module <top>.
  104. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v" into library work
  105. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 50.
  106. Parsing module <lm32_interrupt>.
  107. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v" into library work
  108. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 50.
  109. Parsing module <lm32_mc_arithmetic>.
  110. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_shifter.v" into library work
  111. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 50.
  112. Parsing module <lm32_shifter>.
  113. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_dp_ram.v" into library work
  114. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 31.
  115. Parsing module <lm32_dp_ram>.
  116. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_multiplier.v" into library work
  117. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 50.
  118. Parsing module <lm32_multiplier>.
  119. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" into library work
  120. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 93.
  121. Parsing module <lm32_cpu>.
  122. WARNING:HDLCompiler:924 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" Line 653: Attribute target identifier preserve_driver not found in this scope
  123. WARNING:HDLCompiler:924 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" Line 652: Attribute target identifier preserve_signal not found in this scope
  124. Analyzing Verilog file "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_instruction_unit.v" into library work
  125. Parsing verilog file "D:\cygwin64\home\fevi8970\misoc\misoc\cores\lm32\verilog\submodule\rtl\/lm32_include.v" included at line 71.
  126. Parsing module <lm32_instruction_unit>.
  127.  
  128. =========================================================================
  129. * HDL Elaboration *
  130. =========================================================================
  131. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3519: Port I_LOCK_O is not connected to this instance
  132. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3612: Port IOCLK is not connected to this instance
  133. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3621: Port CLKFBDCM is not connected to this instance
  134. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3682: Port LOCK is not connected to this instance
  135. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3799: Port SHIFTOUT1 is not connected to this instance
  136. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3830: Port CFB0 is not connected to this instance
  137. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3858: Port SHIFTOUT1 is not connected to this instance
  138. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3889: Port CFB0 is not connected to this instance
  139. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3917: Port SHIFTOUT1 is not connected to this instance
  140. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3948: Port CFB0 is not connected to this instance
  141. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3976: Port SHIFTOUT1 is not connected to this instance
  142. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4007: Port CFB0 is not connected to this instance
  143. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4035: Port SHIFTOUT1 is not connected to this instance
  144. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4066: Port CFB0 is not connected to this instance
  145. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4094: Port SHIFTOUT1 is not connected to this instance
  146. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4125: Port CFB0 is not connected to this instance
  147. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4153: Port SHIFTOUT1 is not connected to this instance
  148. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4184: Port CFB0 is not connected to this instance
  149. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4212: Port SHIFTOUT1 is not connected to this instance
  150. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4243: Port CFB0 is not connected to this instance
  151. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4271: Port SHIFTOUT1 is not connected to this instance
  152. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4302: Port CFB0 is not connected to this instance
  153. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4330: Port SHIFTOUT1 is not connected to this instance
  154. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4361: Port CFB0 is not connected to this instance
  155. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4389: Port SHIFTOUT1 is not connected to this instance
  156. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4420: Port CFB0 is not connected to this instance
  157. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4448: Port SHIFTOUT1 is not connected to this instance
  158. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4479: Port CFB0 is not connected to this instance
  159. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4507: Port SHIFTOUT1 is not connected to this instance
  160. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4538: Port CFB0 is not connected to this instance
  161. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4566: Port SHIFTOUT1 is not connected to this instance
  162. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4597: Port CFB0 is not connected to this instance
  163. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4625: Port SHIFTOUT1 is not connected to this instance
  164. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4656: Port CFB0 is not connected to this instance
  165. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4684: Port SHIFTOUT1 is not connected to this instance
  166. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4715: Port CFB0 is not connected to this instance
  167. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4743: Port SHIFTOUT1 is not connected to this instance
  168. WARNING:HDLCompiler:1016 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 4769: Port SHIFTOUT1 is not connected to this instance
  169.  
  170. Elaborating module <top>.
  171.  
  172. Elaborating module <$unit_1>.
  173. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 78: Using initial value of rom_bus_err since it is never assigned
  174. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 91: Using initial value of sram_bus_err since it is never assigned
  175. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 110: Using initial value of bus_wishbone_err since it is never assigned
  176. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 126: Using initial value of uart_phy_source_eop since it is never assigned
  177. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 162: Using initial value of uart_tx_fifo_sink_eop since it is never assigned
  178. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 175: Using initial value of uart_tx_fifo_replace since it is never assigned
  179. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 204: Using initial value of uart_rx_fifo_replace since it is never assigned
  180. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 229: Using initial value of timer0_update_value_w since it is never assigned
  181. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 257: Using initial value of cpulevel_sdram_if_arbitrated_err since it is never assigned
  182. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 261: Using initial value of sdram_half_rst since it is never assigned
  183. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 471: Using initial value of phaseinjector0_command_issue_w since it is never assigned
  184. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 487: Using initial value of phaseinjector1_command_issue_w since it is never assigned
  185. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 508: Using initial value of sdram_controller_dfi_p0_wrdata_en since it is never assigned
  186. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 525: Using initial value of sdram_controller_dfi_p1_rddata_en since it is never assigned
  187. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 538: Using initial value of sdram_controller_bus_err since it is never assigned
  188. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 588: Using initial value of bridge_if_bus_cti since it is never assigned
  189. WARNING:HDLCompiler:872 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 589: Using initial value of bridge_if_bus_bte since it is never assigned
  190. Reading initialization file \"mem.init\".
  191. WARNING:HDLCompiler:1670 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3560: Signal <mem> in initial block is partially initialized.
  192. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1024: Assignment to sdram_controller_dfi_p1_rddata_valid ignored, since the identifier is never used
  193. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1090: Assignment to uart_phy_sink_eop ignored, since the identifier is never used
  194. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1094: Assignment to uart_phy_source_ack ignored, since the identifier is never used
  195. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1193: Assignment to uart_rx_fifo_source_eop ignored, since the identifier is never used
  196. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1246: Assignment to ddrphy_record1_wrdata ignored, since the identifier is never used
  197. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1247: Assignment to ddrphy_record1_wrdata_mask ignored, since the identifier is never used
  198. WARNING:HDLCompiler:413 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1704: Result of 31-bit expression is truncated to fit in 30-bit target.
  199. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1709: Assignment to word_clr ignored, since the identifier is never used
  200. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1785: Assignment to cpulevel_sdram_if_arbitrated_cti ignored, since the identifier is never used
  201. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1786: Assignment to cpulevel_sdram_if_arbitrated_bte ignored, since the identifier is never used
  202. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1790: Assignment to sdram_cpulevel_arbiter_request ignored, since the identifier is never used
  203. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1798: Assignment to sdram_controller_bus_cti ignored, since the identifier is never used
  204. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1799: Assignment to sdram_controller_bus_bte ignored, since the identifier is never used
  205. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1802: Assignment to bridge_if_bus_err ignored, since the identifier is never used
  206. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1803: Assignment to sdram_native_arbiter_request ignored, since the identifier is never used
  207. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1835: Assignment to rom_bus_dat_w ignored, since the identifier is never used
  208. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1836: Assignment to rom_bus_sel ignored, since the identifier is never used
  209. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1838: Assignment to rom_bus_we ignored, since the identifier is never used
  210. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1839: Assignment to rom_bus_cti ignored, since the identifier is never used
  211. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1840: Assignment to rom_bus_bte ignored, since the identifier is never used
  212. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1846: Assignment to sram_bus_cti ignored, since the identifier is never used
  213. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1847: Assignment to sram_bus_bte ignored, since the identifier is never used
  214. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1850: Assignment to bus_wishbone_sel ignored, since the identifier is never used
  215. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1853: Assignment to bus_wishbone_cti ignored, since the identifier is never used
  216. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1854: Assignment to bus_wishbone_bte ignored, since the identifier is never used
  217. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1874: Assignment to phaseinjector0_command_issue_r ignored, since the identifier is never used
  218. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1890: Assignment to basesoc_csrbank0_pi0_rddata3_r ignored, since the identifier is never used
  219. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1891: Assignment to basesoc_csrbank0_pi0_rddata3_re ignored, since the identifier is never used
  220. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1892: Assignment to basesoc_csrbank0_pi0_rddata2_r ignored, since the identifier is never used
  221. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1893: Assignment to basesoc_csrbank0_pi0_rddata2_re ignored, since the identifier is never used
  222. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1894: Assignment to basesoc_csrbank0_pi0_rddata1_r ignored, since the identifier is never used
  223. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1895: Assignment to basesoc_csrbank0_pi0_rddata1_re ignored, since the identifier is never used
  224. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1896: Assignment to basesoc_csrbank0_pi0_rddata0_r ignored, since the identifier is never used
  225. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1897: Assignment to basesoc_csrbank0_pi0_rddata0_re ignored, since the identifier is never used
  226. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1900: Assignment to phaseinjector1_command_issue_r ignored, since the identifier is never used
  227. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1916: Assignment to basesoc_csrbank0_pi1_rddata3_r ignored, since the identifier is never used
  228. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1917: Assignment to basesoc_csrbank0_pi1_rddata3_re ignored, since the identifier is never used
  229. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1918: Assignment to basesoc_csrbank0_pi1_rddata2_r ignored, since the identifier is never used
  230. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1919: Assignment to basesoc_csrbank0_pi1_rddata2_re ignored, since the identifier is never used
  231. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1920: Assignment to basesoc_csrbank0_pi1_rddata1_r ignored, since the identifier is never used
  232. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1921: Assignment to basesoc_csrbank0_pi1_rddata1_re ignored, since the identifier is never used
  233. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1922: Assignment to basesoc_csrbank0_pi1_rddata0_r ignored, since the identifier is never used
  234. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1923: Assignment to basesoc_csrbank0_pi1_rddata0_re ignored, since the identifier is never used
  235. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1993: Assignment to timer0_update_value_r ignored, since the identifier is never used
  236. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1995: Assignment to basesoc_csrbank1_value7_r ignored, since the identifier is never used
  237. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1996: Assignment to basesoc_csrbank1_value7_re ignored, since the identifier is never used
  238. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1997: Assignment to basesoc_csrbank1_value6_r ignored, since the identifier is never used
  239. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1998: Assignment to basesoc_csrbank1_value6_re ignored, since the identifier is never used
  240. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 1999: Assignment to basesoc_csrbank1_value5_r ignored, since the identifier is never used
  241. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2000: Assignment to basesoc_csrbank1_value5_re ignored, since the identifier is never used
  242. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2001: Assignment to basesoc_csrbank1_value4_r ignored, since the identifier is never used
  243. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2002: Assignment to basesoc_csrbank1_value4_re ignored, since the identifier is never used
  244. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2003: Assignment to basesoc_csrbank1_value3_r ignored, since the identifier is never used
  245. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2004: Assignment to basesoc_csrbank1_value3_re ignored, since the identifier is never used
  246. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2005: Assignment to basesoc_csrbank1_value2_r ignored, since the identifier is never used
  247. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2006: Assignment to basesoc_csrbank1_value2_re ignored, since the identifier is never used
  248. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2007: Assignment to basesoc_csrbank1_value1_r ignored, since the identifier is never used
  249. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2008: Assignment to basesoc_csrbank1_value1_re ignored, since the identifier is never used
  250. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2009: Assignment to basesoc_csrbank1_value0_r ignored, since the identifier is never used
  251. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2010: Assignment to basesoc_csrbank1_value0_re ignored, since the identifier is never used
  252. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2011: Assignment to timer0_eventmanager_status_r ignored, since the identifier is never used
  253. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2012: Assignment to timer0_eventmanager_status_re ignored, since the identifier is never used
  254. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2072: Assignment to basesoc_csrbank3_txfull_r ignored, since the identifier is never used
  255. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2073: Assignment to basesoc_csrbank3_txfull_re ignored, since the identifier is never used
  256. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2074: Assignment to basesoc_csrbank3_rxempty_r ignored, since the identifier is never used
  257. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2075: Assignment to basesoc_csrbank3_rxempty_re ignored, since the identifier is never used
  258. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2076: Assignment to uart_status_r ignored, since the identifier is never used
  259. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2077: Assignment to uart_status_re ignored, since the identifier is never used
  260. WARNING:HDLCompiler:413 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2724: Result of 4-bit expression is truncated to fit in 3-bit target.
  261. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2692: Assignment to ddrphy_record0_reset_n ignored, since the identifier is never used
  262. WARNING:HDLCompiler:413 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2774: Result of 32-bit expression is truncated to fit in 8-bit target.
  263. WARNING:HDLCompiler:413 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2775: Result of 30-bit expression is truncated to fit in 14-bit target.
  264. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 2757: Assignment to re ignored, since the identifier is never used
  265.  
  266. Elaborating module <lm32_cpu(eba_reset=32'b0)>.
  267.  
  268. Elaborating module <lm32_instruction_unit(eba_reset=32'b0,associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.
  269.  
  270. Elaborating module <lm32_icache(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.
  271.  
  272. Elaborating module <lm32_ram(data_width=32,address_width=32'sb01010)>.
  273.  
  274. Elaborating module <lm32_ram(data_width=32'sb010101,address_width=32'sb01000)>.
  275. "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_instruction_unit.v" Line 802. $display Instruction bus error. Address: 0
  276. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" Line 910: Assignment to pc_x ignored, since the identifier is never used
  277. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" Line 912: Assignment to pc_w ignored, since the identifier is never used
  278.  
  279. Elaborating module <lm32_decoder>.
  280. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_decoder.v" Line 392: Assignment to op_user ignored, since the identifier is never used
  281. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_decoder.v" Line 419: Assignment to multiply ignored, since the identifier is never used
  282. WARNING:HDLCompiler:413 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_decoder.v" Line 597: Result of 32-bit expression is truncated to fit in 30-bit target.
  283.  
  284. Elaborating module <lm32_load_store_unit(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.
  285.  
  286. Elaborating module <lm32_dcache(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.
  287.  
  288. Elaborating module <lm32_adder>.
  289.  
  290. Elaborating module <lm32_addsub>.
  291.  
  292. Elaborating module <lm32_logic_op>.
  293.  
  294. Elaborating module <lm32_shifter>.
  295. WARNING:HDLCompiler:413 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_shifter.v" Line 149: Result of 64-bit expression is truncated to fit in 32-bit target.
  296.  
  297. Elaborating module <lm32_multiplier>.
  298.  
  299. Elaborating module <lm32_mc_arithmetic>.
  300.  
  301. Elaborating module <lm32_interrupt>.
  302. WARNING:HDLCompiler:413 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v" Line 166: Result of 2-bit expression is truncated to fit in 1-bit target.
  303. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v" Line 166: Assignment to ie_csr_read_data ignored, since the identifier is never used
  304. WARNING:HDLCompiler:413 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v" Line 175: Result of 32-bit expression is truncated to fit in 1-bit target.
  305. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v" Line 175: Assignment to ip_csr_read_data ignored, since the identifier is never used
  306. WARNING:HDLCompiler:413 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v" Line 176: Result of 32-bit expression is truncated to fit in 1-bit target.
  307. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v" Line 176: Assignment to im_csr_read_data ignored, since the identifier is never used
  308. WARNING:HDLCompiler:1127 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" Line 2678: Assignment to x_result_sel_logic_x ignored, since the identifier is never used
  309. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3590: Assignment to uart_tx_fifo_wrport_dat_r ignored, since the identifier is never used
  310. WARNING:HDLCompiler:1127 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3604: Assignment to uart_rx_fifo_wrport_dat_r ignored, since the identifier is never used
  311.  
  312. Elaborating module <IBUFG>.
  313.  
  314. Elaborating module <BUFIO2(DIVIDE=1'b1,DIVIDE_BYPASS="TRUE",I_INVERT="FALSE")>.
  315.  
  316. Elaborating module <PLL_ADV(BANDWIDTH="OPTIMIZED",CLKFBOUT_MULT=4'b1010,CLKFBOUT_PHASE=0.0,CLKIN1_PERIOD=10.0,CLKIN2_PERIOD=0.0,CLKOUT0_DIVIDE=3'b100,CLKOUT0_DUTY_CYCLE=0.5,CLKOUT0_PHASE=0.0,CLKOUT1_DIVIDE=3'b100,CLKOUT1_DUTY_CYCLE=0.5,CLKOUT1_PHASE=0.0,CLKOUT2_DIVIDE=4'b1000,CLKOUT2_DUTY_CYCLE=0.5,CLKOUT2_PHASE=270.0,CLKOUT3_DIVIDE=4'b1000,CLKOUT3_DUTY_CYCLE=0.5,CLKOUT3_PHASE=225.0,CLKOUT4_DIVIDE=5'b10000,CLKOUT4_DUTY_CYCLE=0.5,CLKOUT4_PHASE=0.0,CLKOUT5_DIVIDE=5'b10000,CLKOUT5_DUTY_CYCLE=0.5,CLKOUT5_PHASE=0.0,CLK_FEEDBACK="CLKFBOUT",COMPENSATION="INTERNAL",DIVCLK_DIVIDE=1'b1,REF_JITTER=0.01,SIM_DEVICE="SPARTAN6")>.
  317. WARNING:HDLCompiler:189 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3655: Size mismatch in connection of port <DADDR>. Formal port size is 5-bit while actual signal size is 1-bit.
  318. WARNING:HDLCompiler:189 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" Line 3658: Size mismatch in connection of port <DI>. Formal port size is 16-bit while actual signal size is 1-bit.
  319.  
  320. Elaborating module <BUFG>.
  321.  
  322. Elaborating module <BUFPLL(DIVIDE=3'b100)>.
  323.  
  324. Elaborating module <ODDR2(DDR_ALIGNMENT="NONE",INIT=1'b0,SRTYPE="SYNC")>.
  325.  
  326. Elaborating module <ODDR2(DDR_ALIGNMENT="C1",INIT=1'b0,SRTYPE="ASYNC")>.
  327.  
  328. Elaborating module <OBUFT>.
  329.  
  330. Elaborating module <OSERDES2(DATA_RATE_OQ="SDR",DATA_RATE_OT="SDR",DATA_WIDTH=3'b100,OUTPUT_MODE="SINGLE_ENDED",SERDES_MODE="NONE")>.
  331.  
  332. Elaborating module <ISERDES2(BITSLIP_ENABLE="TRUE",DATA_RATE="SDR",DATA_WIDTH=3'b100,INTERFACE_TYPE="RETIMED",SERDES_MODE="NONE")>.
  333.  
  334. Elaborating module <IOBUF>.
  335.  
  336. Elaborating module <FDPE(INIT=1'b1)>.
  337.  
  338. =========================================================================
  339. * HDL Synthesis *
  340. =========================================================================
  341.  
  342. Synthesizing Unit <top>.
  343. Related source file is "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v".
  344. Set property "register_balancing = no" for signal <regs0>.
  345. Set property "shreg_extract = no" for signal <regs0>.
  346. Set property "register_balancing = no" for signal <regs1>.
  347. Set property "shreg_extract = no" for signal <regs1>.
  348. WARNING:Xst:647 - Input <serial_cts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  349. WARNING:Xst:647 - Input <serial_rts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  350. INFO:Xst:3210 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" line 3521: Output port <I_CTI_O> of the instance <lm32_cpu> is unconnected or connected to loadless signal.
  351. INFO:Xst:3210 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" line 3521: Output port <I_BTE_O> of the instance <lm32_cpu> is unconnected or connected to loadless signal.
  352. INFO:Xst:3210 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" line 3521: Output port <D_CTI_O> of the instance <lm32_cpu> is unconnected or connected to loadless signal.
  353. INFO:Xst:3210 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" line 3521: Output port <D_BTE_O> of the instance <lm32_cpu> is unconnected or connected to loadless signal.
  354. INFO:Xst:3210 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" line 3521: Output port <I_LOCK_O> of the instance <lm32_cpu> is unconnected or connected to loadless signal.
  355. INFO:Xst:3210 - "D:\cygwin64\home\fevi8970\misoc_basesoc_saturn\gateware\top.v" line 3521: Output port <D_LOCK_O> of the instance <lm32_cpu> is unconnected or connected to loadless signal.
  356. WARNING:Xst:2999 - Signal 'mem', unconnected in block 'top', is tied to its initial value.
  357. WARNING:Xst:3035 - Index value(s) does not match array range for signal <mem>, simulation mismatch.
  358. Found 5000x32-bit single-port Read Only RAM <Mram_mem> for signal <mem>.
  359. Found 1024x32-bit dual-port RAM <Mram_mem_1> for signal <mem_1>.
  360. Found 16x9-bit dual-port RAM <Mram_storage_1> for signal <storage_1>.
  361. Found 16x9-bit dual-port RAM <Mram_storage_2> for signal <storage_2>.
  362. Found 2x64-bit dual-port RAM <Mram_data_mem> for signal <data_mem>.
  363. Found 2x31-bit dual-port RAM <Mram_tag_mem> for signal <tag_mem>.
  364. Register <ddrphy_record1_cke> equivalent to <ddrphy_record0_cke> has been removed
  365. Register <memadr_5<0>> equivalent to <memadr_4<0>> has been removed
  366. Found 1-bit register for signal <ddrphy_phase_sel>.
  367. Found 1-bit register for signal <ddrphy_phase_half>.
  368. Found 13-bit register for signal <ddrphy_record0_address>.
  369. Found 2-bit register for signal <ddrphy_record0_bank>.
  370. Found 1-bit register for signal <ddrphy_record0_cke>.
  371. Found 1-bit register for signal <ddrphy_record0_cas_n>.
  372. Found 1-bit register for signal <ddrphy_record0_ras_n>.
  373. Found 1-bit register for signal <ddrphy_record0_we_n>.
  374. Found 13-bit register for signal <ddrphy_record1_address>.
  375. Found 2-bit register for signal <ddrphy_record1_bank>.
  376. Found 1-bit register for signal <ddrphy_record1_cas_n>.
  377. Found 1-bit register for signal <ddrphy_record1_ras_n>.
  378. Found 1-bit register for signal <ddrphy_record1_we_n>.
  379. Found 13-bit register for signal <ddram_a>.
  380. Found 2-bit register for signal <ddram_ba>.
  381. Found 1-bit register for signal <ddram_cke>.
  382. Found 1-bit register for signal <ddram_ras_n>.
  383. Found 1-bit register for signal <ddram_cas_n>.
  384. Found 1-bit register for signal <ddram_we_n>.
  385. Found 1-bit register for signal <ddrphy_postamble>.
  386. Found 2-bit register for signal <ddrphy_r_dfi_wrdata_en<1:0>>.
  387. Found 1-bit register for signal <tmpu_error>.
  388. Found 1-bit register for signal <rom_bus_ack>.
  389. Found 1-bit register for signal <sram_bus_ack>.
  390. Found 1-bit register for signal <interface_we>.
  391. Found 8-bit register for signal <interface_dat_w>.
  392. Found 14-bit register for signal <interface_adr>.
  393. Found 32-bit register for signal <bus_wishbone_dat_r>.
  394. Found 1-bit register for signal <bus_wishbone_ack>.
  395. Found 2-bit register for signal <counter>.
  396. Found 1-bit register for signal <uart_phy_sink_ack>.
  397. Found 8-bit register for signal <uart_phy_tx_reg>.
  398. Found 4-bit register for signal <uart_phy_tx_bitcount>.
  399. Found 1-bit register for signal <uart_phy_tx_busy>.
  400. Found 1-bit register for signal <serial_tx>.
  401. Found 32-bit register for signal <uart_phy_phase_accumulator_tx>.
  402. Found 1-bit register for signal <uart_phy_uart_clk_txen>.
  403. Found 1-bit register for signal <uart_phy_source_stb>.
  404. Found 1-bit register for signal <uart_phy_rx_r>.
  405. Found 1-bit register for signal <uart_phy_rx_busy>.
  406. Found 4-bit register for signal <uart_phy_rx_bitcount>.
  407. Found 8-bit register for signal <uart_phy_source_payload_data>.
  408. Found 8-bit register for signal <uart_phy_rx_reg>.
  409. Found 32-bit register for signal <uart_phy_phase_accumulator_rx>.
  410. Found 1-bit register for signal <uart_phy_uart_clk_rxen>.
  411. Found 1-bit register for signal <uart_tx_pending>.
  412. Found 1-bit register for signal <uart_tx_old_trigger>.
  413. Found 1-bit register for signal <uart_rx_pending>.
  414. Found 1-bit register for signal <uart_rx_old_trigger>.
  415. Found 4-bit register for signal <uart_tx_fifo_produce>.
  416. Found 4-bit register for signal <uart_tx_fifo_consume>.
  417. Found 5-bit register for signal <uart_tx_fifo_level>.
  418. Found 4-bit register for signal <uart_rx_fifo_produce>.
  419. Found 4-bit register for signal <uart_rx_fifo_consume>.
  420. Found 5-bit register for signal <uart_rx_fifo_level>.
  421. Found 64-bit register for signal <timer0_value>.
  422. Found 64-bit register for signal <timer0_value_status>.
  423. Found 1-bit register for signal <timer0_zero_pending>.
  424. Found 1-bit register for signal <timer0_zero_old_trigger>.
  425. Found 1-bit register for signal <ddrphy_phase_sys>.
  426. Found 1-bit register for signal <ddrphy_bitslip_inc>.
  427. Found 4-bit register for signal <ddrphy_bitslip_cnt>.
  428. Found 16-bit register for signal <ddrphy_record2_wrdata<15:0>>.
  429. Found 32-bit register for signal <ddrphy_record3_wrdata>.
  430. Found 1-bit register for signal <ddrphy_drive_dq_n1>.
  431. Found 1-bit register for signal <ddrphy_wrdata_en_d>.
  432. Found 5-bit register for signal <ddrphy_rddata_sr>.
  433. Found 32-bit register for signal <phaseinjector0_status>.
  434. Found 32-bit register for signal <phaseinjector1_status>.
  435. Found 1-bit register for signal <sdram_controller_bank0_idle>.
  436. Found 13-bit register for signal <sdram_controller_bank0_row1>.
  437. Found 1-bit register for signal <sdram_controller_bank1_idle>.
  438. Found 13-bit register for signal <sdram_controller_bank1_row1>.
  439. Found 1-bit register for signal <sdram_controller_bank2_idle>.
  440. Found 13-bit register for signal <sdram_controller_bank2_row1>.
  441. Found 1-bit register for signal <sdram_controller_bank3_idle>.
  442. Found 13-bit register for signal <sdram_controller_bank3_row1>.
  443. Found 2-bit register for signal <sdram_controller_write2precharge_timer_count>.
  444. Found 9-bit register for signal <sdram_controller_refresh_timer_count>.
  445. Found 4-bit register for signal <minicon_state>.
  446. Found 1-bit register for signal <adr_offset_r>.
  447. Found 3-bit register for signal <cache_state>.
  448. Found 1-bit register for signal <basesoc_grant>.
  449. Found 4-bit register for signal <basesoc_slave_sel_r>.
  450. Found 8-bit register for signal <basesoc_interface0_dat_r>.
  451. Found 4-bit register for signal <storage_full>.
  452. Found 6-bit register for signal <phaseinjector0_command_storage_full>.
  453. Found 1-bit register for signal <phaseinjector0_address_storage_full<12>>.
  454. Found 1-bit register for signal <phaseinjector0_address_storage_full<11>>.
  455. Found 1-bit register for signal <phaseinjector0_address_storage_full<10>>.
  456. Found 1-bit register for signal <phaseinjector0_address_storage_full<9>>.
  457. Found 1-bit register for signal <phaseinjector0_address_storage_full<8>>.
  458. Found 1-bit register for signal <phaseinjector0_address_storage_full<7>>.
  459. Found 1-bit register for signal <phaseinjector0_address_storage_full<6>>.
  460. Found 1-bit register for signal <phaseinjector0_address_storage_full<5>>.
  461. Found 1-bit register for signal <phaseinjector0_address_storage_full<4>>.
  462. Found 1-bit register for signal <phaseinjector0_address_storage_full<3>>.
  463. Found 1-bit register for signal <phaseinjector0_address_storage_full<2>>.
  464. Found 1-bit register for signal <phaseinjector0_address_storage_full<1>>.
  465. Found 1-bit register for signal <phaseinjector0_address_storage_full<0>>.
  466. Found 2-bit register for signal <phaseinjector0_baddress_storage_full>.
  467. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<31>>.
  468. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<30>>.
  469. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<29>>.
  470. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<28>>.
  471. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<27>>.
  472. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<26>>.
  473. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<25>>.
  474. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<24>>.
  475. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<23>>.
  476. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<22>>.
  477. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<21>>.
  478. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<20>>.
  479. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<19>>.
  480. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<18>>.
  481. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<17>>.
  482. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<16>>.
  483. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<15>>.
  484. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<14>>.
  485. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<13>>.
  486. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<12>>.
  487. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<11>>.
  488. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<10>>.
  489. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<9>>.
  490. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<8>>.
  491. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<7>>.
  492. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<6>>.
  493. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<5>>.
  494. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<4>>.
  495. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<3>>.
  496. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<2>>.
  497. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<1>>.
  498. Found 1-bit register for signal <phaseinjector0_wrdata_storage_full<0>>.
  499. Found 6-bit register for signal <phaseinjector1_command_storage_full>.
  500. Found 1-bit register for signal <phaseinjector1_address_storage_full<12>>.
  501. Found 1-bit register for signal <phaseinjector1_address_storage_full<11>>.
  502. Found 1-bit register for signal <phaseinjector1_address_storage_full<10>>.
  503. Found 1-bit register for signal <phaseinjector1_address_storage_full<9>>.
  504. Found 1-bit register for signal <phaseinjector1_address_storage_full<8>>.
  505. Found 1-bit register for signal <phaseinjector1_address_storage_full<7>>.
  506. Found 1-bit register for signal <phaseinjector1_address_storage_full<6>>.
  507. Found 1-bit register for signal <phaseinjector1_address_storage_full<5>>.
  508. Found 1-bit register for signal <phaseinjector1_address_storage_full<4>>.
  509. Found 1-bit register for signal <phaseinjector1_address_storage_full<3>>.
  510. Found 1-bit register for signal <phaseinjector1_address_storage_full<2>>.
  511. Found 1-bit register for signal <phaseinjector1_address_storage_full<1>>.
  512. Found 1-bit register for signal <phaseinjector1_address_storage_full<0>>.
  513. Found 2-bit register for signal <phaseinjector1_baddress_storage_full>.
  514. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<31>>.
  515. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<30>>.
  516. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<29>>.
  517. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<28>>.
  518. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<27>>.
  519. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<26>>.
  520. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<25>>.
  521. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<24>>.
  522. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<23>>.
  523. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<22>>.
  524. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<21>>.
  525. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<20>>.
  526. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<19>>.
  527. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<18>>.
  528. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<17>>.
  529. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<16>>.
  530. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<15>>.
  531. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<14>>.
  532. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<13>>.
  533. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<12>>.
  534. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<11>>.
  535. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<10>>.
  536. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<9>>.
  537. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<8>>.
  538. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<7>>.
  539. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<6>>.
  540. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<5>>.
  541. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<4>>.
  542. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<3>>.
  543. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<2>>.
  544. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<1>>.
  545. Found 1-bit register for signal <phaseinjector1_wrdata_storage_full<0>>.
  546. Found 8-bit register for signal <basesoc_interface1_dat_r>.
  547. Found 1-bit register for signal <timer0_load_storage_full<63>>.
  548. Found 1-bit register for signal <timer0_load_storage_full<62>>.
  549. Found 1-bit register for signal <timer0_load_storage_full<61>>.
  550. Found 1-bit register for signal <timer0_load_storage_full<60>>.
  551. Found 1-bit register for signal <timer0_load_storage_full<59>>.
  552. Found 1-bit register for signal <timer0_load_storage_full<58>>.
  553. Found 1-bit register for signal <timer0_load_storage_full<57>>.
  554. Found 1-bit register for signal <timer0_load_storage_full<56>>.
  555. Found 1-bit register for signal <timer0_load_storage_full<55>>.
  556. Found 1-bit register for signal <timer0_load_storage_full<54>>.
  557. Found 1-bit register for signal <timer0_load_storage_full<53>>.
  558. Found 1-bit register for signal <timer0_load_storage_full<52>>.
  559. Found 1-bit register for signal <timer0_load_storage_full<51>>.
  560. Found 1-bit register for signal <timer0_load_storage_full<50>>.
  561. Found 1-bit register for signal <timer0_load_storage_full<49>>.
  562. Found 1-bit register for signal <timer0_load_storage_full<48>>.
  563. Found 1-bit register for signal <timer0_load_storage_full<47>>.
  564. Found 1-bit register for signal <timer0_load_storage_full<46>>.
  565. Found 1-bit register for signal <timer0_load_storage_full<45>>.
  566. Found 1-bit register for signal <timer0_load_storage_full<44>>.
  567. Found 1-bit register for signal <timer0_load_storage_full<43>>.
  568. Found 1-bit register for signal <timer0_load_storage_full<42>>.
  569. Found 1-bit register for signal <timer0_load_storage_full<41>>.
  570. Found 1-bit register for signal <timer0_load_storage_full<40>>.
  571. Found 1-bit register for signal <timer0_load_storage_full<39>>.
  572. Found 1-bit register for signal <timer0_load_storage_full<38>>.
  573. Found 1-bit register for signal <timer0_load_storage_full<37>>.
  574. Found 1-bit register for signal <timer0_load_storage_full<36>>.
  575. Found 1-bit register for signal <timer0_load_storage_full<35>>.
  576. Found 1-bit register for signal <timer0_load_storage_full<34>>.
  577. Found 1-bit register for signal <timer0_load_storage_full<33>>.
  578. Found 1-bit register for signal <timer0_load_storage_full<32>>.
  579. Found 1-bit register for signal <timer0_load_storage_full<31>>.
  580. Found 1-bit register for signal <timer0_load_storage_full<30>>.
  581. Found 1-bit register for signal <timer0_load_storage_full<29>>.
  582. Found 1-bit register for signal <timer0_load_storage_full<28>>.
  583. Found 1-bit register for signal <timer0_load_storage_full<27>>.
  584. Found 1-bit register for signal <timer0_load_storage_full<26>>.
  585. Found 1-bit register for signal <timer0_load_storage_full<25>>.
  586. Found 1-bit register for signal <timer0_load_storage_full<24>>.
  587. Found 1-bit register for signal <timer0_load_storage_full<23>>.
  588. Found 1-bit register for signal <timer0_load_storage_full<22>>.
  589. Found 1-bit register for signal <timer0_load_storage_full<21>>.
  590. Found 1-bit register for signal <timer0_load_storage_full<20>>.
  591. Found 1-bit register for signal <timer0_load_storage_full<19>>.
  592. Found 1-bit register for signal <timer0_load_storage_full<18>>.
  593. Found 1-bit register for signal <timer0_load_storage_full<17>>.
  594. Found 1-bit register for signal <timer0_load_storage_full<16>>.
  595. Found 1-bit register for signal <timer0_load_storage_full<15>>.
  596. Found 1-bit register for signal <timer0_load_storage_full<14>>.
  597. Found 1-bit register for signal <timer0_load_storage_full<13>>.
  598. Found 1-bit register for signal <timer0_load_storage_full<12>>.
  599. Found 1-bit register for signal <timer0_load_storage_full<11>>.
  600. Found 1-bit register for signal <timer0_load_storage_full<10>>.
  601. Found 1-bit register for signal <timer0_load_storage_full<9>>.
  602. Found 1-bit register for signal <timer0_load_storage_full<8>>.
  603. Found 1-bit register for signal <timer0_load_storage_full<7>>.
  604. Found 1-bit register for signal <timer0_load_storage_full<6>>.
  605. Found 1-bit register for signal <timer0_load_storage_full<5>>.
  606. Found 1-bit register for signal <timer0_load_storage_full<4>>.
  607. Found 1-bit register for signal <timer0_load_storage_full<3>>.
  608. Found 1-bit register for signal <timer0_load_storage_full<2>>.
  609. Found 1-bit register for signal <timer0_load_storage_full<1>>.
  610. Found 1-bit register for signal <timer0_load_storage_full<0>>.
  611. Found 1-bit register for signal <timer0_reload_storage_full<63>>.
  612. Found 1-bit register for signal <timer0_reload_storage_full<62>>.
  613. Found 1-bit register for signal <timer0_reload_storage_full<61>>.
  614. Found 1-bit register for signal <timer0_reload_storage_full<60>>.
  615. Found 1-bit register for signal <timer0_reload_storage_full<59>>.
  616. Found 1-bit register for signal <timer0_reload_storage_full<58>>.
  617. Found 1-bit register for signal <timer0_reload_storage_full<57>>.
  618. Found 1-bit register for signal <timer0_reload_storage_full<56>>.
  619. Found 1-bit register for signal <timer0_reload_storage_full<55>>.
  620. Found 1-bit register for signal <timer0_reload_storage_full<54>>.
  621. Found 1-bit register for signal <timer0_reload_storage_full<53>>.
  622. Found 1-bit register for signal <timer0_reload_storage_full<52>>.
  623. Found 1-bit register for signal <timer0_reload_storage_full<51>>.
  624. Found 1-bit register for signal <timer0_reload_storage_full<50>>.
  625. Found 1-bit register for signal <timer0_reload_storage_full<49>>.
  626. Found 1-bit register for signal <timer0_reload_storage_full<48>>.
  627. Found 1-bit register for signal <timer0_reload_storage_full<47>>.
  628. Found 1-bit register for signal <timer0_reload_storage_full<46>>.
  629. Found 1-bit register for signal <timer0_reload_storage_full<45>>.
  630. Found 1-bit register for signal <timer0_reload_storage_full<44>>.
  631. Found 1-bit register for signal <timer0_reload_storage_full<43>>.
  632. Found 1-bit register for signal <timer0_reload_storage_full<42>>.
  633. Found 1-bit register for signal <timer0_reload_storage_full<41>>.
  634. Found 1-bit register for signal <timer0_reload_storage_full<40>>.
  635. Found 1-bit register for signal <timer0_reload_storage_full<39>>.
  636. Found 1-bit register for signal <timer0_reload_storage_full<38>>.
  637. Found 1-bit register for signal <timer0_reload_storage_full<37>>.
  638. Found 1-bit register for signal <timer0_reload_storage_full<36>>.
  639. Found 1-bit register for signal <timer0_reload_storage_full<35>>.
  640. Found 1-bit register for signal <timer0_reload_storage_full<34>>.
  641. Found 1-bit register for signal <timer0_reload_storage_full<33>>.
  642. Found 1-bit register for signal <timer0_reload_storage_full<32>>.
  643. Found 1-bit register for signal <timer0_reload_storage_full<31>>.
  644. Found 1-bit register for signal <timer0_reload_storage_full<30>>.
  645. Found 1-bit register for signal <timer0_reload_storage_full<29>>.
  646. Found 1-bit register for signal <timer0_reload_storage_full<28>>.
  647. Found 1-bit register for signal <timer0_reload_storage_full<27>>.
  648. Found 1-bit register for signal <timer0_reload_storage_full<26>>.
  649. Found 1-bit register for signal <timer0_reload_storage_full<25>>.
  650. Found 1-bit register for signal <timer0_reload_storage_full<24>>.
  651. Found 1-bit register for signal <timer0_reload_storage_full<23>>.
  652. Found 1-bit register for signal <timer0_reload_storage_full<22>>.
  653. Found 1-bit register for signal <timer0_reload_storage_full<21>>.
  654. Found 1-bit register for signal <timer0_reload_storage_full<20>>.
  655. Found 1-bit register for signal <timer0_reload_storage_full<19>>.
  656. Found 1-bit register for signal <timer0_reload_storage_full<18>>.
  657. Found 1-bit register for signal <timer0_reload_storage_full<17>>.
  658. Found 1-bit register for signal <timer0_reload_storage_full<16>>.
  659. Found 1-bit register for signal <timer0_reload_storage_full<15>>.
  660. Found 1-bit register for signal <timer0_reload_storage_full<14>>.
  661. Found 1-bit register for signal <timer0_reload_storage_full<13>>.
  662. Found 1-bit register for signal <timer0_reload_storage_full<12>>.
  663. Found 1-bit register for signal <timer0_reload_storage_full<11>>.
  664. Found 1-bit register for signal <timer0_reload_storage_full<10>>.
  665. Found 1-bit register for signal <timer0_reload_storage_full<9>>.
  666. Found 1-bit register for signal <timer0_reload_storage_full<8>>.
  667. Found 1-bit register for signal <timer0_reload_storage_full<7>>.
  668. Found 1-bit register for signal <timer0_reload_storage_full<6>>.
  669. Found 1-bit register for signal <timer0_reload_storage_full<5>>.
  670. Found 1-bit register for signal <timer0_reload_storage_full<4>>.
  671. Found 1-bit register for signal <timer0_reload_storage_full<3>>.
  672. Found 1-bit register for signal <timer0_reload_storage_full<2>>.
  673. Found 1-bit register for signal <timer0_reload_storage_full<1>>.
  674. Found 1-bit register for signal <timer0_reload_storage_full<0>>.
  675. Found 1-bit register for signal <timer0_en_storage_full>.
  676. Found 1-bit register for signal <timer0_eventmanager_storage_full>.
  677. Found 8-bit register for signal <basesoc_interface2_dat_r>.
  678. Found 1-bit register for signal <tmpu_enable_null_storage_full>.
  679. Found 1-bit register for signal <tmpu_enable_prog_storage_full>.
  680. Found 1-bit register for signal <tmpu_prog_address_storage_full<29>>.
  681. Found 1-bit register for signal <tmpu_prog_address_storage_full<28>>.
  682. Found 1-bit register for signal <tmpu_prog_address_storage_full<27>>.
  683. Found 1-bit register for signal <tmpu_prog_address_storage_full<26>>.
  684. Found 1-bit register for signal <tmpu_prog_address_storage_full<25>>.
  685. Found 1-bit register for signal <tmpu_prog_address_storage_full<24>>.
  686. Found 1-bit register for signal <tmpu_prog_address_storage_full<23>>.
  687. Found 1-bit register for signal <tmpu_prog_address_storage_full<22>>.
  688. Found 1-bit register for signal <tmpu_prog_address_storage_full<21>>.
  689. Found 1-bit register for signal <tmpu_prog_address_storage_full<20>>.
  690. Found 1-bit register for signal <tmpu_prog_address_storage_full<19>>.
  691. Found 1-bit register for signal <tmpu_prog_address_storage_full<18>>.
  692. Found 1-bit register for signal <tmpu_prog_address_storage_full<17>>.
  693. Found 1-bit register for signal <tmpu_prog_address_storage_full<16>>.
  694. Found 1-bit register for signal <tmpu_prog_address_storage_full<15>>.
  695. Found 1-bit register for signal <tmpu_prog_address_storage_full<14>>.
  696. Found 1-bit register for signal <tmpu_prog_address_storage_full<13>>.
  697. Found 1-bit register for signal <tmpu_prog_address_storage_full<12>>.
  698. Found 8-bit register for signal <basesoc_interface3_dat_r>.
  699. Found 2-bit register for signal <uart_storage_full>.
  700. Found 8-bit register for signal <basesoc_interface4_dat_r>.
  701. Found 1-bit register for signal <uart_phy_storage_full<31>>.
  702. Found 1-bit register for signal <uart_phy_storage_full<30>>.
  703. Found 1-bit register for signal <uart_phy_storage_full<29>>.
  704. Found 1-bit register for signal <uart_phy_storage_full<28>>.
  705. Found 1-bit register for signal <uart_phy_storage_full<27>>.
  706. Found 1-bit register for signal <uart_phy_storage_full<26>>.
  707. Found 1-bit register for signal <uart_phy_storage_full<25>>.
  708. Found 1-bit register for signal <uart_phy_storage_full<24>>.
  709. Found 1-bit register for signal <uart_phy_storage_full<23>>.
  710. Found 1-bit register for signal <uart_phy_storage_full<22>>.
  711. Found 1-bit register for signal <uart_phy_storage_full<21>>.
  712. Found 1-bit register for signal <uart_phy_storage_full<20>>.
  713. Found 1-bit register for signal <uart_phy_storage_full<19>>.
  714. Found 1-bit register for signal <uart_phy_storage_full<18>>.
  715. Found 1-bit register for signal <uart_phy_storage_full<17>>.
  716. Found 1-bit register for signal <uart_phy_storage_full<16>>.
  717. Found 1-bit register for signal <uart_phy_storage_full<15>>.
  718. Found 1-bit register for signal <uart_phy_storage_full<14>>.
  719. Found 1-bit register for signal <uart_phy_storage_full<13>>.
  720. Found 1-bit register for signal <uart_phy_storage_full<12>>.
  721. Found 1-bit register for signal <uart_phy_storage_full<11>>.
  722. Found 1-bit register for signal <uart_phy_storage_full<10>>.
  723. Found 1-bit register for signal <uart_phy_storage_full<9>>.
  724. Found 1-bit register for signal <uart_phy_storage_full<8>>.
  725. Found 1-bit register for signal <uart_phy_storage_full<7>>.
  726. Found 1-bit register for signal <uart_phy_storage_full<6>>.
  727. Found 1-bit register for signal <uart_phy_storage_full<5>>.
  728. Found 1-bit register for signal <uart_phy_storage_full<4>>.
  729. Found 1-bit register for signal <uart_phy_storage_full<3>>.
  730. Found 1-bit register for signal <uart_phy_storage_full<2>>.
  731. Found 1-bit register for signal <uart_phy_storage_full<1>>.
  732. Found 1-bit register for signal <uart_phy_storage_full<0>>.
  733. Found 1-bit register for signal <regs0>.
  734. Found 1-bit register for signal <regs1>.
  735. Found 13-bit register for signal <memadr>.
  736. Found 10-bit register for signal <memadr_1>.
  737. Found 1-bit register for signal <memadr_4>.
  738. Found 11-bit register for signal <crg_por>.
  739. Found finite state machine <FSM_0> for signal <minicon_state>.
  740. -----------------------------------------------------------------------
  741. | States | 16 |
  742. | Transitions | 23 |
  743. | Inputs | 7 |
  744. | Outputs | 13 |
  745. | Clock | sys_clk (rising_edge) |
  746. | Reset | sys_rst (positive) |
  747. | Reset type | synchronous |
  748. | Reset State | 0000 |
  749. | Power Up State | 0000 |
  750. | Encoding | auto |
  751. | Implementation | LUT |
  752. -----------------------------------------------------------------------
  753. Found finite state machine <FSM_1> for signal <cache_state>.
  754. -----------------------------------------------------------------------
  755. | States | 5 |
  756. | Transitions | 13 |
  757. | Inputs | 8 |
  758. | Outputs | 4 |
  759. | Clock | sys_clk (rising_edge) |
  760. | Reset | sys_rst (positive) |
  761. | Reset type | synchronous |
  762. | Reset State | 000 |
  763. | Power Up State | 000 |
  764. | Encoding | auto |
  765. | Implementation | LUT |
  766. -----------------------------------------------------------------------
  767. Found 11-bit subtractor for signal <crg_por[10]_GND_1_o_sub_555_OUT> created at line 2685.
  768. Found 5-bit subtractor for signal <uart_tx_fifo_level[4]_GND_1_o_sub_614_OUT> created at line 2879.
  769. Found 5-bit subtractor for signal <uart_rx_fifo_level[4]_GND_1_o_sub_623_OUT> created at line 2894.
  770. Found 64-bit subtractor for signal <timer0_value[63]_GND_1_o_sub_627_OUT> created at line 2901.
  771. Found 2-bit subtractor for signal <sdram_controller_write2precharge_timer_count[1]_GND_1_o_sub_648_OUT> created at line 2978.
  772. Found 9-bit subtractor for signal <sdram_controller_refresh_timer_count[8]_GND_1_o_sub_651_OUT> created at line 2985.
  773. Found 1-bit adder for signal <ddrphy_phase_sel_PWR_1_o_add_560_OUT<0>> created at line 2696.
  774. Found 1-bit adder for signal <ddrphy_phase_half_PWR_1_o_add_561_OUT<0>> created at line 2698.
  775. Found 2-bit adder for signal <counter[1]_GND_1_o_add_576_OUT> created at line 2787.
  776. Found 4-bit adder for signal <uart_phy_tx_bitcount[3]_GND_1_o_add_579_OUT> created at line 2801.
  777. Found 33-bit adder for signal <n2295> created at line 2817.
  778. Found 4-bit adder for signal <uart_phy_rx_bitcount[3]_GND_1_o_add_591_OUT> created at line 2830.
  779. Found 33-bit adder for signal <n2300> created at line 2849.
  780. Found 4-bit adder for signal <uart_tx_fifo_produce[3]_GND_1_o_add_607_OUT> created at line 2868.
  781. Found 4-bit adder for signal <uart_tx_fifo_consume[3]_GND_1_o_add_609_OUT> created at line 2871.
  782. Found 5-bit adder for signal <uart_tx_fifo_level[4]_GND_1_o_add_611_OUT> created at line 2875.
  783. Found 4-bit adder for signal <uart_rx_fifo_produce[3]_GND_1_o_add_616_OUT> created at line 2883.
  784. Found 4-bit adder for signal <uart_rx_fifo_consume[3]_GND_1_o_add_618_OUT> created at line 2886.
  785. Found 5-bit adder for signal <uart_rx_fifo_level[4]_GND_1_o_add_620_OUT> created at line 2890.
  786. Found 4-bit adder for signal <ddrphy_bitslip_cnt[3]_GND_1_o_add_631_OUT> created at line 2920.
  787. Found 8-bit 29-to-1 multiplexer for signal <basesoc_interface0_adr[4]_GND_1_o_wide_mux_653_OUT> created at line 3012.
  788. Found 8-bit 31-to-1 multiplexer for signal <basesoc_interface1_adr[4]_GND_1_o_wide_mux_660_OUT> created at line 3158.
  789. Found 8-bit 7-to-1 multiplexer for signal <basesoc_interface2_adr[2]_GND_1_o_wide_mux_662_OUT> created at line 3308.
  790. Found 8-bit 7-to-1 multiplexer for signal <basesoc_interface3_adr[2]_GND_1_o_wide_mux_664_OUT> created at line 3352.
  791. Found 8-bit 4-to-1 multiplexer for signal <basesoc_interface4_adr[1]_basesoc_csrbank4_tuning_word0_w[7]_wide_mux_667_OUT> created at line 3379.
  792. Found 13-bit comparator equal for signal <sdram_controller_bank0_row0[12]_sdram_controller_bank0_row1[12]_equal_107_o> created at line 1529
  793. Found 13-bit comparator equal for signal <sdram_controller_bank1_row0[12]_sdram_controller_bank1_row1[12]_equal_108_o> created at line 1530
  794. Found 13-bit comparator equal for signal <sdram_controller_bank2_row0[12]_sdram_controller_bank2_row1[12]_equal_109_o> created at line 1531
  795. Found 13-bit comparator equal for signal <sdram_controller_bank3_row0[12]_sdram_controller_bank3_row1[12]_equal_110_o> created at line 1532
  796. Found 30-bit comparator equal for signal <tag_do_tag[29]_GND_1_o_equal_149_o> created at line 1724
  797. Found 11-bit comparator greater for signal <GND_1_o_crg_por[10]_LessThan_552_o> created at line 2681
  798. Found 1-bit comparator equal for signal <ddrphy_phase_half_ddrphy_phase_sys_equal_560_o> created at line 2693
  799. Found 20-bit comparator equal for signal <dbus_adr[29]_GND_1_o_equal_572_o> created at line 2762
  800. WARNING:Xst:2404 - FFs/Latches <ddrphy_record3_wrdata_mask<3:0>> (without init value) have a constant value of 0 in block <top>.
  801. WARNING:Xst:2404 - FFs/Latches <ddrphy_record2_wrdata_mask<1:0>> (without init value) have a constant value of 0 in block <top>.
  802. Summary:
  803. inferred 6 RAM(s).
  804. inferred 18 Adder/Subtractor(s).
  805. inferred 955 D-type flip-flop(s).
  806. inferred 8 Comparator(s).
  807. inferred 112 Multiplexer(s).
  808. inferred 2 Finite State Machine(s).
  809. Unit <top> synthesized.
  810.  
  811. Synthesizing Unit <lm32_cpu>.
  812. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v".
  813. eba_reset = 32'b00000000000000000000000000000000
  814. icache_associativity = 1
  815. icache_sets = 256
  816. icache_bytes_per_line = 16
  817. icache_base_address = 32'b00000000000000000000000000000000
  818. icache_limit = 32'b01111111111111111111111111111111
  819. dcache_associativity = 1
  820. dcache_sets = 256
  821. dcache_bytes_per_line = 16
  822. dcache_base_address = 32'b00000000000000000000000000000000
  823. dcache_limit = 32'b01111111111111111111111111111111
  824. watchpoints = 0
  825. breakpoints = 0
  826. interrupts = 32
  827. WARNING:Xst:647 - Input <I_RTY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  828. INFO:Xst:3210 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" line 845: Output port <pc_x> of the instance <instruction_unit> is unconnected or connected to loadless signal.
  829. INFO:Xst:3210 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" line 845: Output port <pc_w> of the instance <instruction_unit> is unconnected or connected to loadless signal.
  830. INFO:Xst:3210 - "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_cpu.v" line 953: Output port <x_result_sel_logic> of the instance <decoder> is unconnected or connected to loadless signal.
  831. Found 32-bit register for signal <cc>.
  832. Found 1-bit register for signal <data_bus_error_exception>.
  833. Found 1-bit register for signal <valid_f>.
  834. Found 1-bit register for signal <valid_d>.
  835. Found 1-bit register for signal <valid_x>.
  836. Found 1-bit register for signal <valid_m>.
  837. Found 1-bit register for signal <valid_w>.
  838. Found 32-bit register for signal <operand_0_x>.
  839. Found 32-bit register for signal <operand_1_x>.
  840. Found 32-bit register for signal <store_operand_x>.
  841. Found 30-bit register for signal <branch_target_x>.
  842. Found 1-bit register for signal <x_result_sel_csr_x>.
  843. Found 1-bit register for signal <x_result_sel_mc_arith_x>.
  844. Found 1-bit register for signal <x_result_sel_sext_x>.
  845. Found 1-bit register for signal <x_result_sel_add_x>.
  846. Found 1-bit register for signal <m_result_sel_compare_x>.
  847. Found 1-bit register for signal <m_result_sel_shift_x>.
  848. Found 1-bit register for signal <w_result_sel_load_x>.
  849. Found 1-bit register for signal <w_result_sel_mul_x>.
  850. Found 1-bit register for signal <x_bypass_enable_x>.
  851. Found 1-bit register for signal <m_bypass_enable_x>.
  852. Found 1-bit register for signal <write_enable_x>.
  853. Found 5-bit register for signal <write_idx_x>.
  854. Found 3-bit register for signal <csr_x>.
  855. Found 1-bit register for signal <load_x>.
  856. Found 1-bit register for signal <store_x>.
  857. Found 2-bit register for signal <size_x>.
  858. Found 1-bit register for signal <sign_extend_x>.
  859. Found 1-bit register for signal <adder_op_x>.
  860. Found 1-bit register for signal <adder_op_x_n>.
  861. Found 4-bit register for signal <logic_op_x>.
  862. Found 1-bit register for signal <direction_x>.
  863. Found 1-bit register for signal <branch_x>.
  864. Found 1-bit register for signal <branch_predict_x>.
  865. Found 1-bit register for signal <branch_predict_taken_x>.
  866. Found 3-bit register for signal <condition_x>.
  867. Found 1-bit register for signal <scall_x>.
  868. Found 1-bit register for signal <eret_x>.
  869. Found 1-bit register for signal <bus_error_x>.
  870. Found 1-bit register for signal <data_bus_error_exception_m>.
  871. Found 1-bit register for signal <csr_write_enable_x>.
  872. Found 32-bit register for signal <operand_m>.
  873. Found 30-bit register for signal <branch_target_m>.
  874. Found 1-bit register for signal <m_result_sel_compare_m>.
  875. Found 1-bit register for signal <m_result_sel_shift_m>.
  876. Found 1-bit register for signal <w_result_sel_load_m>.
  877. Found 1-bit register for signal <w_result_sel_mul_m>.
  878. Found 1-bit register for signal <m_bypass_enable_m>.
  879. Found 1-bit register for signal <branch_m>.
  880. Found 1-bit register for signal <branch_predict_m>.
  881. Found 1-bit register for signal <branch_predict_taken_m>.
  882. Found 1-bit register for signal <exception_m>.
  883. Found 1-bit register for signal <load_m>.
  884. Found 1-bit register for signal <store_m>.
  885. Found 1-bit register for signal <write_enable_m>.
  886. Found 5-bit register for signal <write_idx_m>.
  887. Found 1-bit register for signal <condition_met_m>.
  888. Found 1-bit register for signal <dflush_m>.
  889. Found 32-bit register for signal <operand_w>.
  890. Found 1-bit register for signal <w_result_sel_load_w>.
  891. Found 1-bit register for signal <w_result_sel_mul_w>.
  892. Found 5-bit register for signal <write_idx_w>.
  893. Found 1-bit register for signal <write_enable_w>.
  894. Found 1-bit register for signal <exception_w>.
  895. Found 30-bit register for signal <memop_pc_w>.
  896. Found 23-bit register for signal <eba>.
  897. Found 30-bit adder for signal <branch_target_d> created at line 1573.
  898. Found 32-bit adder for signal <cc[31]_GND_3_o_add_198_OUT> created at line 2549.
  899. Found 32x32-bit dual-port RAM <Mram_registers> for signal <registers>.
  900. Found 32-bit 3-to-1 multiplexer for signal <d_result_1> created at line 1584.
  901. Found 1-bit 8-to-1 multiplexer for signal <condition_met_x> created at line 1617.
  902. Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_0_d[4]_equal_3_o> created at line 1511
  903. Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_0_d[4]_equal_5_o> created at line 1512
  904. Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_0_d[4]_equal_7_o> created at line 1513
  905. Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_1_d[4]_equal_9_o> created at line 1514
  906. Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_1_d[4]_equal_11_o> created at line 1515
  907. Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_1_d[4]_equal_13_o> created at line 1516
  908. Found 32-bit comparator equal for signal <cmp_zero> created at line 1611
  909. Found 1-bit comparator equal for signal <cmp_negative_cmp_overflow_equal_47_o> created at line 1624
  910. Summary:
  911. inferred 2 RAM(s).
  912. inferred 2 Adder/Subtractor(s).
  913. inferred 381 D-type flip-flop(s).
  914. inferred 8 Comparator(s).
  915. inferred 42 Multiplexer(s).
  916. Unit <lm32_cpu> synthesized.
  917.  
  918. Synthesizing Unit <lm32_instruction_unit>.
  919. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_instruction_unit.v".
  920. eba_reset = 32'b00000000000000000000000000000000
  921. associativity = 1
  922. sets = 256
  923. bytes_per_line = 16
  924. base_address = 32'b00000000000000000000000000000000
  925. limit = 32'b01111111111111111111111111111111
  926. Found 30-bit register for signal <pc_d>.
  927. Found 30-bit register for signal <pc_x>.
  928. Found 30-bit register for signal <pc_m>.
  929. Found 30-bit register for signal <pc_w>.
  930. Found 30-bit register for signal <restart_address>.
  931. Found 1-bit register for signal <i_cyc_o>.
  932. Found 1-bit register for signal <i_stb_o>.
  933. Found 32-bit register for signal <i_adr_o>.
  934. Found 3-bit register for signal <i_cti_o>.
  935. Found 1-bit register for signal <i_lock_o>.
  936. Found 32-bit register for signal <icache_refill_data>.
  937. Found 1-bit register for signal <icache_refill_ready>.
  938. Found 1-bit register for signal <bus_error_f>.
  939. Found 32-bit register for signal <instruction_d>.
  940. Found 1-bit register for signal <bus_error_d>.
  941. Found 30-bit register for signal <pc_f>.
  942. Found 30-bit adder for signal <pc_f[31]_GND_4_o_add_11_OUT> created at line 565.
  943. Found 2-bit adder for signal <i_adr_o[3]_GND_4_o_add_60_OUT> created at line 791.
  944. Summary:
  945. inferred 2 Adder/Subtractor(s).
  946. inferred 284 D-type flip-flop(s).
  947. inferred 11 Multiplexer(s).
  948. Unit <lm32_instruction_unit> synthesized.
  949.  
  950. Synthesizing Unit <lm32_icache>.
  951. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_icache.v".
  952. associativity = 1
  953. sets = 256
  954. bytes_per_line = 16
  955. base_address = 32'b00000000000000000000000000000000
  956. limit = 32'b01111111111111111111111111111111
  957. WARNING:Xst:647 - Input <address_a<31:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  958. Found 4-bit register for signal <state>.
  959. Found 8-bit register for signal <flush_set>.
  960. Found 30-bit register for signal <refill_address>.
  961. Found 1-bit register for signal <restart_request>.
  962. Found 2-bit register for signal <refill_offset>.
  963. Found 1-bit register for signal <refilling>.
  964. Found finite state machine <FSM_2> for signal <state>.
  965. -----------------------------------------------------------------------
  966. | States | 4 |
  967. | Transitions | 18 |
  968. | Inputs | 11 |
  969. | Outputs | 8 |
  970. | Clock | clk_i (rising_edge) |
  971. | Reset | rst_i (positive) |
  972. | Reset type | synchronous |
  973. | Reset State | 0001 |
  974. | Encoding | auto |
  975. | Implementation | LUT |
  976. -----------------------------------------------------------------------
  977. Found 8-bit subtractor for signal <flush_set[7]_GND_5_o_sub_22_OUT> created at line 421.
  978. Found 2-bit adder for signal <refill_offset[3]_GND_5_o_add_59_OUT> created at line 507.
  979. Found 21-bit comparator equal for signal <way_match> created at line 294
  980. Summary:
  981. inferred 2 Adder/Subtractor(s).
  982. inferred 42 D-type flip-flop(s).
  983. inferred 1 Comparator(s).
  984. inferred 8 Multiplexer(s).
  985. inferred 1 Finite State Machine(s).
  986. Unit <lm32_icache> synthesized.
  987.  
  988. Synthesizing Unit <lm32_ram_1>.
  989. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_ram.v".
  990. data_width = 32
  991. address_width = 10
  992. init_file = "NONE"
  993. WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  994. Found 1024x32-bit dual-port RAM <Mram_mem> for signal <mem>.
  995. Found 10-bit register for signal <ra>.
  996. Summary:
  997. inferred 1 RAM(s).
  998. inferred 10 D-type flip-flop(s).
  999. Unit <lm32_ram_1> synthesized.
  1000.  
  1001. Synthesizing Unit <lm32_ram_2>.
  1002. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_ram.v".
  1003. data_width = 21
  1004. address_width = 8
  1005. init_file = "NONE"
  1006. WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1007. Found 256x21-bit dual-port RAM <Mram_mem> for signal <mem>.
  1008. Found 8-bit register for signal <ra>.
  1009. Summary:
  1010. inferred 1 RAM(s).
  1011. inferred 8 D-type flip-flop(s).
  1012. Unit <lm32_ram_2> synthesized.
  1013.  
  1014. Synthesizing Unit <lm32_decoder>.
  1015. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_decoder.v".
  1016. Summary:
  1017. inferred 14 Multiplexer(s).
  1018. Unit <lm32_decoder> synthesized.
  1019.  
  1020. Synthesizing Unit <lm32_load_store_unit>.
  1021. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_load_store_unit.v".
  1022. associativity = 1
  1023. sets = 256
  1024. bytes_per_line = 16
  1025. base_address = 32'b00000000000000000000000000000000
  1026. limit = 32'b01111111111111111111111111111111
  1027. WARNING:Xst:647 - Input <load_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1028. WARNING:Xst:647 - Input <store_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1029. WARNING:Xst:647 - Input <store_q_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1030. WARNING:Xst:647 - Input <d_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1031. Found 1-bit register for signal <d_stb_o>.
  1032. Found 32-bit register for signal <d_dat_o>.
  1033. Found 32-bit register for signal <d_adr_o>.
  1034. Found 4-bit register for signal <d_sel_o>.
  1035. Found 1-bit register for signal <d_we_o>.
  1036. Found 3-bit register for signal <d_cti_o>.
  1037. Found 1-bit register for signal <d_lock_o>.
  1038. Found 32-bit register for signal <wb_data_m>.
  1039. Found 1-bit register for signal <wb_load_complete>.
  1040. Found 1-bit register for signal <stall_wb_load>.
  1041. Found 1-bit register for signal <dcache_refill_ready>.
  1042. Found 1-bit register for signal <sign_extend_m>.
  1043. Found 2-bit register for signal <size_m>.
  1044. Found 4-bit register for signal <byte_enable_m>.
  1045. Found 32-bit register for signal <store_data_m>.
  1046. Found 1-bit register for signal <dcache_select_m>.
  1047. Found 1-bit register for signal <wb_select_m>.
  1048. Found 2-bit register for signal <size_w>.
  1049. Found 32-bit register for signal <data_w>.
  1050. Found 1-bit register for signal <sign_extend_w>.
  1051. Found 1-bit register for signal <d_cyc_o>.
  1052. Found 2-bit adder for signal <d_adr_o[3]_GND_9_o_add_36_OUT> created at line 718.
  1053. Found 32-bit 3-to-1 multiplexer for signal <store_data_x> created at line 509.
  1054. Found 32-bit comparator greater for signal <wb_select_x> created at line 481
  1055. Summary:
  1056. inferred 1 Adder/Subtractor(s).
  1057. inferred 185 D-type flip-flop(s).
  1058. inferred 1 Comparator(s).
  1059. inferred 12 Multiplexer(s).
  1060. Unit <lm32_load_store_unit> synthesized.
  1061.  
  1062. Synthesizing Unit <lm32_dcache>.
  1063. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_dcache.v".
  1064. associativity = 1
  1065. sets = 256
  1066. bytes_per_line = 16
  1067. base_address = 32'b00000000000000000000000000000000
  1068. limit = 32'b01111111111111111111111111111111
  1069. WARNING:Xst:647 - Input <address_x<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1070. WARNING:Xst:647 - Input <address_x<31:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1071. Found 3-bit register for signal <state>.
  1072. Found 8-bit register for signal <flush_set>.
  1073. Found 1-bit register for signal <refill_request>.
  1074. Found 32-bit register for signal <refill_address>.
  1075. Found 1-bit register for signal <restart_request>.
  1076. Found 2-bit register for signal <refill_offset>.
  1077. Found 1-bit register for signal <refilling>.
  1078. Found finite state machine <FSM_3> for signal <state>.
  1079. -----------------------------------------------------------------------
  1080. | States | 3 |
  1081. | Transitions | 15 |
  1082. | Inputs | 9 |
  1083. | Outputs | 6 |
  1084. | Clock | clk_i (rising_edge) |
  1085. | Reset | rst_i (positive) |
  1086. | Reset type | synchronous |
  1087. | Reset State | 001 |
  1088. | Encoding | auto |
  1089. | Implementation | LUT |
  1090. -----------------------------------------------------------------------
  1091. Found 8-bit subtractor for signal <flush_set[7]_GND_10_o_sub_38_OUT> created at line 469.
  1092. Found 2-bit adder for signal <refill_offset[3]_GND_10_o_add_68_OUT> created at line 528.
  1093. Found 21-bit comparator equal for signal <way_match> created at line 308
  1094. Summary:
  1095. inferred 2 Adder/Subtractor(s).
  1096. inferred 45 D-type flip-flop(s).
  1097. inferred 1 Comparator(s).
  1098. inferred 13 Multiplexer(s).
  1099. inferred 1 Finite State Machine(s).
  1100. Unit <lm32_dcache> synthesized.
  1101.  
  1102. Synthesizing Unit <lm32_adder>.
  1103. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_adder.v".
  1104. Summary:
  1105. no macro.
  1106. Unit <lm32_adder> synthesized.
  1107.  
  1108. Synthesizing Unit <lm32_addsub>.
  1109. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_addsub.v".
  1110. Found 33-bit subtractor for signal <GND_12_o_GND_12_o_sub_3_OUT> created at line 90.
  1111. Found 33-bit subtractor for signal <tmp_subResult> created at line 90.
  1112. Found 33-bit adder for signal <n0025> created at line 89.
  1113. Found 33-bit adder for signal <tmp_addResult> created at line 89.
  1114. Summary:
  1115. inferred 4 Adder/Subtractor(s).
  1116. inferred 2 Multiplexer(s).
  1117. Unit <lm32_addsub> synthesized.
  1118.  
  1119. Synthesizing Unit <lm32_logic_op>.
  1120. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_logic_op.v".
  1121. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<0>> created at line 93.
  1122. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<1>> created at line 93.
  1123. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<2>> created at line 93.
  1124. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<3>> created at line 93.
  1125. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<4>> created at line 93.
  1126. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<5>> created at line 93.
  1127. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<6>> created at line 93.
  1128. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<7>> created at line 93.
  1129. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<8>> created at line 93.
  1130. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<9>> created at line 93.
  1131. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<10>> created at line 93.
  1132. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<11>> created at line 93.
  1133. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<12>> created at line 93.
  1134. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<13>> created at line 93.
  1135. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<14>> created at line 93.
  1136. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<15>> created at line 93.
  1137. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<16>> created at line 93.
  1138. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<17>> created at line 93.
  1139. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<18>> created at line 93.
  1140. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<19>> created at line 93.
  1141. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<20>> created at line 93.
  1142. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<21>> created at line 93.
  1143. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<22>> created at line 93.
  1144. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<23>> created at line 93.
  1145. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<24>> created at line 93.
  1146. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<25>> created at line 93.
  1147. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<26>> created at line 93.
  1148. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<27>> created at line 93.
  1149. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<28>> created at line 93.
  1150. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<29>> created at line 93.
  1151. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<30>> created at line 93.
  1152. Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<31>> created at line 93.
  1153. Summary:
  1154. inferred 32 Multiplexer(s).
  1155. Unit <lm32_logic_op> synthesized.
  1156.  
  1157. Synthesizing Unit <lm32_shifter>.
  1158. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_shifter.v".
  1159. WARNING:Xst:647 - Input <operand_1_x<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  1160. Found 1-bit register for signal <direction_m>.
  1161. Found 32-bit register for signal <right_shift_result>.
  1162. Found 64-bit shifter logical right for signal <n0028> created at line 149
  1163. Summary:
  1164. inferred 33 D-type flip-flop(s).
  1165. inferred 3 Multiplexer(s).
  1166. inferred 1 Combinational logic shifter(s).
  1167. Unit <lm32_shifter> synthesized.
  1168.  
  1169. Synthesizing Unit <lm32_multiplier>.
  1170. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_multiplier.v".
  1171. Found 32-bit register for signal <multiplier>.
  1172. Found 32-bit register for signal <product>.
  1173. Found 32-bit register for signal <result>.
  1174. Found 32-bit register for signal <muliplicand>.
  1175. Found 32x32-bit multiplier for signal <n0023> created at line 115.
  1176. Summary:
  1177. inferred 1 Multiplier(s).
  1178. inferred 128 D-type flip-flop(s).
  1179. Unit <lm32_multiplier> synthesized.
  1180.  
  1181. Synthesizing Unit <lm32_mc_arithmetic>.
  1182. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_mc_arithmetic.v".
  1183. Found 32-bit register for signal <p>.
  1184. Found 32-bit register for signal <a>.
  1185. Found 32-bit register for signal <b>.
  1186. Found 1-bit register for signal <divide_by_zero_x>.
  1187. Found 32-bit register for signal <result_x>.
  1188. Found 3-bit register for signal <state>.
  1189. Found 6-bit register for signal <cycles>.
  1190. Found finite state machine <FSM_4> for signal <state>.
  1191. -----------------------------------------------------------------------
  1192. | States | 3 |
  1193. | Transitions | 8 |
  1194. | Inputs | 4 |
  1195. | Outputs | 5 |
  1196. | Clock | clk_i (rising_edge) |
  1197. | Reset | rst_i (positive) |
  1198. | Reset type | synchronous |
  1199. | Reset State | 000 |
  1200. | Encoding | auto |
  1201. | Implementation | LUT |
  1202. -----------------------------------------------------------------------
  1203. Found 33-bit subtractor for signal <t> created at line 156.
  1204. Found 6-bit subtractor for signal <cycles[5]_GND_17_o_sub_21_OUT> created at line 250.
  1205. Summary:
  1206. inferred 2 Adder/Subtractor(s).
  1207. inferred 135 D-type flip-flop(s).
  1208. inferred 7 Multiplexer(s).
  1209. inferred 1 Finite State Machine(s).
  1210. Unit <lm32_mc_arithmetic> synthesized.
  1211.  
  1212. Synthesizing Unit <lm32_interrupt>.
  1213. Related source file is "D:/cygwin64/home/fevi8970/misoc/misoc/cores/lm32/verilog/submodule/rtl/lm32_interrupt.v".
  1214. interrupts = 32
  1215. Found 1-bit register for signal <eie>.
  1216. Found 32-bit register for signal <im>.
  1217. Found 1-bit register for signal <ie>.
  1218. Found 32-bit 3-to-1 multiplexer for signal <csr_read_data> created at line 122.
  1219. Summary:
  1220. inferred 34 D-type flip-flop(s).
  1221. inferred 4 Multiplexer(s).
  1222. Unit <lm32_interrupt> synthesized.
  1223.  
  1224. =========================================================================
  1225. HDL Synthesis Report
  1226.  
  1227. Macro Statistics
  1228. # RAMs : 12
  1229. 1024x32-bit dual-port RAM : 3
  1230. 16x9-bit dual-port RAM : 2
  1231. 256x21-bit dual-port RAM : 2
  1232. 2x31-bit dual-port RAM : 1
  1233. 2x64-bit dual-port RAM : 1
  1234. 32x32-bit dual-port RAM : 2
  1235. 5000x32-bit single-port Read Only RAM : 1
  1236. # Multipliers : 1
  1237. 32x32-bit multiplier : 1
  1238. # Adders/Subtractors : 33
  1239. 1-bit adder : 2
  1240. 11-bit subtractor : 1
  1241. 2-bit adder : 5
  1242. 2-bit subtractor : 1
  1243. 30-bit adder : 2
  1244. 32-bit adder : 1
  1245. 33-bit adder : 4
  1246. 33-bit subtractor : 3
  1247. 4-bit adder : 7
  1248. 5-bit addsub : 2
  1249. 6-bit subtractor : 1
  1250. 64-bit subtractor : 1
  1251. 8-bit subtractor : 2
  1252. 9-bit subtractor : 1
  1253. # Registers : 306
  1254. 1-bit register : 167
  1255. 10-bit register : 3
  1256. 11-bit register : 1
  1257. 13-bit register : 8
  1258. 14-bit register : 1
  1259. 16-bit register : 1
  1260. 2-bit register : 14
  1261. 23-bit register : 1
  1262. 3-bit register : 4
  1263. 30-bit register : 10
  1264. 32-bit register : 31
  1265. 4-bit register : 12
  1266. 5-bit register : 6
  1267. 6-bit register : 3
  1268. 64-bit register : 2
  1269. 8-bit register : 41
  1270. 9-bit register : 1
  1271. # Comparators : 19
  1272. 1-bit comparator equal : 2
  1273. 11-bit comparator greater : 1
  1274. 13-bit comparator equal : 4
  1275. 20-bit comparator equal : 1
  1276. 21-bit comparator equal : 2
  1277. 30-bit comparator equal : 1
  1278. 32-bit comparator equal : 1
  1279. 32-bit comparator greater : 1
  1280. 5-bit comparator equal : 6
  1281. # Multiplexers : 260
  1282. 1-bit 2-to-1 multiplexer : 102
  1283. 1-bit 4-to-1 multiplexer : 32
  1284. 1-bit 8-to-1 multiplexer : 1
  1285. 10-bit 2-to-1 multiplexer : 1
  1286. 13-bit 2-to-1 multiplexer : 10
  1287. 2-bit 2-to-1 multiplexer : 11
  1288. 3-bit 2-to-1 multiplexer : 2
  1289. 30-bit 2-to-1 multiplexer : 10
  1290. 32-bit 2-to-1 multiplexer : 44
  1291. 32-bit 3-to-1 multiplexer : 3
  1292. 4-bit 2-to-1 multiplexer : 6
  1293. 5-bit 2-to-1 multiplexer : 3
  1294. 6-bit 2-to-1 multiplexer : 1
  1295. 64-bit 2-to-1 multiplexer : 4
  1296. 8-bit 2-to-1 multiplexer : 24
  1297. 8-bit 29-to-1 multiplexer : 1
  1298. 8-bit 31-to-1 multiplexer : 1
  1299. 8-bit 4-to-1 multiplexer : 1
  1300. 8-bit 7-to-1 multiplexer : 2
  1301. 9-bit 2-to-1 multiplexer : 1
  1302. # Logic shifters : 1
  1303. 64-bit shifter logical right : 1
  1304. # FSMs : 5
  1305.  
  1306. =========================================================================
  1307.  
  1308. =========================================================================
  1309. * Advanced HDL Synthesis *
  1310. =========================================================================
  1311.  
  1312.  
  1313. Synthesizing (advanced) Unit <lm32_cpu>.
  1314. The following registers are absorbed into counter <cc>: 1 register on signal <cc>.
  1315. INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_registers> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
  1316. -----------------------------------------------------------------------
  1317. | ram_type | Distributed | |
  1318. -----------------------------------------------------------------------
  1319. | Port A |
  1320. | aspect ratio | 32-word x 32-bit | |
  1321. | clkA | connected to signal <clk_i> | rise |
  1322. | weA | connected to signal <reg_write_enable_q_w> | high |
  1323. | addrA | connected to signal <write_idx_w> | |
  1324. | diA | connected to signal <w_result> | |
  1325. -----------------------------------------------------------------------
  1326. | Port B |
  1327. | aspect ratio | 32-word x 32-bit | |
  1328. | addrB | connected to signal <read_idx_0_d> | |
  1329. | doB | connected to signal <reg_data_0> | |
  1330. -----------------------------------------------------------------------
  1331. INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_registers1> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
  1332. -----------------------------------------------------------------------
  1333. | ram_type | Distributed | |
  1334. -----------------------------------------------------------------------
  1335. | Port A |
  1336. | aspect ratio | 32-word x 32-bit | |
  1337. | clkA | connected to signal <clk_i> | rise |
  1338. | weA | connected to signal <reg_write_enable_q_w> | high |
  1339. | addrA | connected to signal <write_idx_w> | |
  1340. | diA | connected to signal <w_result> | |
  1341. -----------------------------------------------------------------------
  1342. | Port B |
  1343. | aspect ratio | 32-word x 32-bit | |
  1344. | addrB | connected to signal <read_idx_1_d> | |
  1345. | doB | connected to signal <reg_data_1> | |
  1346. -----------------------------------------------------------------------
  1347. Unit <lm32_cpu> synthesized (advanced).
  1348.  
  1349. Synthesizing (advanced) Unit <lm32_dcache>.
  1350. The following registers are absorbed into counter <flush_set>: 1 register on signal <flush_set>.
  1351. Unit <lm32_dcache> synthesized (advanced).
  1352.  
  1353. Synthesizing (advanced) Unit <lm32_icache>.
  1354. The following registers are absorbed into counter <flush_set>: 1 register on signal <flush_set>.
  1355. Unit <lm32_icache> synthesized (advanced).
  1356.  
  1357. Synthesizing (advanced) Unit <lm32_mc_arithmetic>.
  1358. The following registers are absorbed into counter <cycles>: 1 register on signal <cycles>.
  1359. Unit <lm32_mc_arithmetic> synthesized (advanced).
  1360.  
  1361. Synthesizing (advanced) Unit <lm32_multiplier>.
  1362. Found pipelined multiplier on signal <n0023>:
  1363. - 1 pipeline level(s) found in a register connected to the multiplier macro output.
  1364. Pushing register(s) into the multiplier macro.
  1365. INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_n0023 by adding 6 register level(s).
  1366. Unit <lm32_multiplier> synthesized (advanced).
  1367.  
  1368. Synthesizing (advanced) Unit <lm32_ram_1>.
  1369. INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <ra>
  1370. -----------------------------------------------------------------------
  1371. | ram_type | Block | |
  1372. -----------------------------------------------------------------------
  1373. | Port A |
  1374. | aspect ratio | 1024-word x 32-bit | |
  1375. | mode | write-first | |
  1376. | clkA | connected to signal <write_clk> | rise |
  1377. | weA | connected to internal node | high |
  1378. | addrA | connected to signal <write_address> | |
  1379. | diA | connected to signal <write_data> | |
  1380. -----------------------------------------------------------------------
  1381. | optimization | speed | |
  1382. -----------------------------------------------------------------------
  1383. | Port B |
  1384. | aspect ratio | 1024-word x 32-bit | |
  1385. | mode | write-first | |
  1386. | clkB | connected to signal <read_clk> | rise |
  1387. | addrB | connected to signal <read_address> | |
  1388. | doB | connected to internal node | |
  1389. -----------------------------------------------------------------------
  1390. | optimization | speed | |
  1391. -----------------------------------------------------------------------
  1392. Unit <lm32_ram_1> synthesized (advanced).
  1393.  
  1394. Synthesizing (advanced) Unit <lm32_ram_2>.
  1395. INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <ra>
  1396. -----------------------------------------------------------------------
  1397. | ram_type | Block | |
  1398. -----------------------------------------------------------------------
  1399. | Port A |
  1400. | aspect ratio | 256-word x 21-bit | |
  1401. | mode | write-first | |
  1402. | clkA | connected to signal <write_clk> | rise |
  1403. | weA | connected to internal node | high |
  1404. | addrA | connected to signal <write_address> | |
  1405. | diA | connected to signal <write_data> | |
  1406. -----------------------------------------------------------------------
  1407. | optimization | speed | |
  1408. -----------------------------------------------------------------------
  1409. | Port B |
  1410. | aspect ratio | 256-word x 21-bit | |
  1411. | mode | write-first | |
  1412. | clkB | connected to signal <read_clk> | rise |
  1413. | addrB | connected to signal <read_address> | |
  1414. | doB | connected to internal node | |
  1415. -----------------------------------------------------------------------
  1416. | optimization | speed | |
  1417. -----------------------------------------------------------------------
  1418. Unit <lm32_ram_2> synthesized (advanced).
  1419.  
  1420. Synthesizing (advanced) Unit <top>.
  1421. The following registers are absorbed into counter <crg_por>: 1 register on signal <crg_por>.
  1422. The following registers are absorbed into counter <ddrphy_phase_half>: 1 register on signal <ddrphy_phase_half>.
  1423. The following registers are absorbed into counter <ddrphy_phase_sel>: 1 register on signal <ddrphy_phase_sel>.
  1424. The following registers are absorbed into counter <uart_phy_tx_bitcount>: 1 register on signal <uart_phy_tx_bitcount>.
  1425. The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
  1426. The following registers are absorbed into counter <uart_phy_rx_bitcount>: 1 register on signal <uart_phy_rx_bitcount>.
  1427. The following registers are absorbed into counter <uart_tx_fifo_consume>: 1 register on signal <uart_tx_fifo_consume>.
  1428. The following registers are absorbed into counter <uart_tx_fifo_produce>: 1 register on signal <uart_tx_fifo_produce>.
  1429. The following registers are absorbed into counter <uart_tx_fifo_level>: 1 register on signal <uart_tx_fifo_level>.
  1430. The following registers are absorbed into counter <uart_rx_fifo_consume>: 1 register on signal <uart_rx_fifo_consume>.
  1431. The following registers are absorbed into counter <uart_rx_fifo_produce>: 1 register on signal <uart_rx_fifo_produce>.
  1432. The following registers are absorbed into counter <uart_rx_fifo_level>: 1 register on signal <uart_rx_fifo_level>.
  1433. The following registers are absorbed into counter <ddrphy_bitslip_cnt>: 1 register on signal <ddrphy_bitslip_cnt>.
  1434. The following registers are absorbed into counter <sdram_controller_write2precharge_timer_count>: 1 register on signal <sdram_controller_write2precharge_timer_count>.
  1435. The following registers are absorbed into counter <sdram_controller_refresh_timer_count>: 1 register on signal <sdram_controller_refresh_timer_count>.
  1436. INFO:Xst:3231 - The small RAM <Mram_data_mem> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
  1437. -----------------------------------------------------------------------
  1438. | ram_type | Distributed | |
  1439. -----------------------------------------------------------------------
  1440. | Port A |
  1441. | aspect ratio | 2-word x 64-bit | |
  1442. | clkA | connected to signal <sys_clk> | rise |
  1443. | weA | connected to signal <VCC> | high |
  1444. | addrA | connected to signal <comb_array_muxed16<1>> | |
  1445. | diA | connected to signal <(_n2434,_n2433,_n2432,_n2431,_n2430,_n2429,_n2428,_n2427)> | |
  1446. | doA | connected to internal node | |
  1447. -----------------------------------------------------------------------
  1448. | Port B |
  1449. | aspect ratio | 2-word x 64-bit | |
  1450. | addrB | connected to signal <memadr_4> | |
  1451. | doB | connected to signal <bridge_if_bus_dat_w> | |
  1452. -----------------------------------------------------------------------
  1453. INFO:Xst:3231 - The small RAM <Mram_tag_mem> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
  1454. -----------------------------------------------------------------------
  1455. | ram_type | Distributed | |
  1456. -----------------------------------------------------------------------
  1457. | Port A |
  1458. | aspect ratio | 2-word x 31-bit | |
  1459. | clkA | connected to signal <sys_clk> | rise |
  1460. | weA | connected to signal <tag_port_we> | high |
  1461. | addrA | connected to signal <comb_array_muxed16<1>> | |
  1462. | diA | connected to signal <(tag_di_dirty,"00",comb_array_muxed16<29:2>)> | |
  1463. -----------------------------------------------------------------------
  1464. | Port B |
  1465. | aspect ratio | 2-word x 31-bit | |
  1466. | addrB | connected to signal <memadr_4> | |
  1467. | doB | connected to internal node | |
  1468. -----------------------------------------------------------------------
  1469. INFO:Xst:3231 - The small RAM <Mram_storage_1> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
  1470. -----------------------------------------------------------------------
  1471. | ram_type | Distributed | |
  1472. -----------------------------------------------------------------------
  1473. | Port A |
  1474. | aspect ratio | 16-word x 9-bit | |
  1475. | clkA | connected to signal <sys_clk> | rise |
  1476. | weA | connected to signal <uart_tx_fifo_wrport_we> | high |
  1477. | addrA | connected to signal <uart_tx_fifo_produce> | |
  1478. | diA | connected to signal <("0",interface_dat_w)> | |
  1479. -----------------------------------------------------------------------
  1480. | Port B |
  1481. | aspect ratio | 16-word x 9-bit | |
  1482. | addrB | connected to signal <uart_tx_fifo_consume> | |
  1483. | doB | connected to signal <uart_tx_fifo_syncfifo_dout> | |
  1484. -----------------------------------------------------------------------
  1485. INFO:Xst:3226 - The RAM <Mram_mem_1> will be implemented as a BLOCK RAM, absorbing the following register(s): <memadr_1>
  1486. -----------------------------------------------------------------------
  1487. | ram_type | Block | |
  1488. -----------------------------------------------------------------------
  1489. | Port A |
  1490. | aspect ratio | 1024-word x 32-bit | |
  1491. | mode | write-first | |
  1492. | clkA | connected to signal <sys_clk> | rise |
  1493. | weA<3> | connected to signal <sram_we<3>> | high |
  1494. | weA<2> | connected to signal <sram_we<2>> | high |
  1495. | weA<1> | connected to signal <sram_we<1>> | high |
  1496. | weA<0> | connected to signal <sram_we<0>> | high |
  1497. | addrA | connected to signal <comb_array_muxed16<9:0>> | |
  1498. | diA | connected to signal <comb_array_muxed17> | |
  1499. | doA | connected to signal <sram_bus_dat_r> | |
  1500. -----------------------------------------------------------------------
  1501. | optimization | speed | |
  1502. -----------------------------------------------------------------------
  1503. INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <memadr>
  1504. -----------------------------------------------------------------------
  1505. | ram_type | Block | |
  1506. -----------------------------------------------------------------------
  1507. | Port A |
  1508. | aspect ratio | 5000-word x 32-bit | |
  1509. | mode | write-first | |
  1510. | clkA | connected to signal <sys_clk> | rise |
  1511. | weA | connected to signal <GND> | high |
  1512. | addrA | connected to signal <comb_array_muxed16<12:0>> | |
  1513. | diA | connected to signal <GND> | |
  1514. | doA | connected to signal <rom_bus_dat_r> | |
  1515. -----------------------------------------------------------------------
  1516. | optimization | speed | |
  1517. -----------------------------------------------------------------------
  1518. INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_storage_2> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
  1519. -----------------------------------------------------------------------
  1520. | ram_type | Distributed | |
  1521. -----------------------------------------------------------------------
  1522. | Port A |
  1523. | aspect ratio | 16-word x 9-bit | |
  1524. | clkA | connected to signal <sys_clk> | rise |
  1525. | weA | connected to signal <uart_rx_fifo_wrport_we> | high |
  1526. | addrA | connected to signal <uart_rx_fifo_produce> | |
  1527. | diA | connected to signal <("0",uart_phy_source_payload_data)> | |
  1528. -----------------------------------------------------------------------
  1529. | Port B |
  1530. | aspect ratio | 16-word x 9-bit | |
  1531. | addrB | connected to signal <uart_rx_fifo_consume> | |
  1532. | doB | connected to signal <uart_rx_fifo_syncfifo_dout> | |
  1533. -----------------------------------------------------------------------
  1534. Unit <top> synthesized (advanced).
  1535. WARNING:Xst:2677 - Node <interface_adr_5> of sequential type is unconnected in block <top>.
  1536. WARNING:Xst:2677 - Node <interface_adr_6> of sequential type is unconnected in block <top>.
  1537. WARNING:Xst:2677 - Node <interface_adr_7> of sequential type is unconnected in block <top>.
  1538. WARNING:Xst:2677 - Node <interface_adr_8> of sequential type is unconnected in block <top>.
  1539.  
  1540. =========================================================================
  1541. Advanced HDL Synthesis Report
  1542.  
  1543. Macro Statistics
  1544. # RAMs : 12
  1545. 1024x32-bit dual-port block RAM : 2
  1546. 1024x32-bit single-port block RAM : 1
  1547. 16x9-bit dual-port distributed RAM : 2
  1548. 256x21-bit dual-port block RAM : 2
  1549. 2x31-bit dual-port distributed RAM : 1
  1550. 2x64-bit dual-port distributed RAM : 1
  1551. 32x32-bit dual-port distributed RAM : 2
  1552. 5000x32-bit single-port block Read Only RAM : 1
  1553. # Multipliers : 1
  1554. 32x32-bit registered multiplier : 1
  1555. # Adders/Subtractors : 12
  1556. 2-bit adder : 4
  1557. 30-bit adder : 2
  1558. 33-bit adder : 2
  1559. 33-bit adder carry in : 1
  1560. 33-bit subtractor : 1
  1561. 33-bit subtractor borrow in : 1
  1562. 64-bit subtractor : 1
  1563. # Counters : 19
  1564. 1-bit up counter : 2
  1565. 11-bit down counter : 1
  1566. 2-bit down counter : 1
  1567. 2-bit up counter : 1
  1568. 32-bit up counter : 1
  1569. 4-bit up counter : 7
  1570. 5-bit updown counter : 2
  1571. 6-bit down counter : 1
  1572. 8-bit down counter : 2
  1573. 9-bit down counter : 1
  1574. # Registers : 2085
  1575. Flip-Flops : 2085
  1576. # Comparators : 19
  1577. 1-bit comparator equal : 2
  1578. 11-bit comparator greater : 1
  1579. 13-bit comparator equal : 4
  1580. 20-bit comparator equal : 1
  1581. 21-bit comparator equal : 2
  1582. 30-bit comparator equal : 1
  1583. 32-bit comparator equal : 1
  1584. 32-bit comparator greater : 1
  1585. 5-bit comparator equal : 6
  1586. # Multiplexers : 751
  1587. 1-bit 2-to-1 multiplexer : 606
  1588. 1-bit 29-to-1 multiplexer : 8
  1589. 1-bit 31-to-1 multiplexer : 8
  1590. 1-bit 4-to-1 multiplexer : 32
  1591. 1-bit 8-to-1 multiplexer : 1
  1592. 10-bit 2-to-1 multiplexer : 1
  1593. 13-bit 2-to-1 multiplexer : 8
  1594. 2-bit 2-to-1 multiplexer : 7
  1595. 3-bit 2-to-1 multiplexer : 2
  1596. 30-bit 2-to-1 multiplexer : 7
  1597. 32-bit 2-to-1 multiplexer : 36
  1598. 32-bit 3-to-1 multiplexer : 3
  1599. 4-bit 2-to-1 multiplexer : 4
  1600. 5-bit 2-to-1 multiplexer : 3
  1601. 64-bit 2-to-1 multiplexer : 2
  1602. 8-bit 2-to-1 multiplexer : 20
  1603. 8-bit 4-to-1 multiplexer : 1
  1604. 8-bit 7-to-1 multiplexer : 2
  1605. # Logic shifters : 1
  1606. 64-bit shifter logical right : 1
  1607. # FSMs : 5
  1608.  
  1609. =========================================================================
  1610.  
  1611. =========================================================================
  1612. * Low Level Synthesis *
  1613. =========================================================================
  1614. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_31> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1615. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_30> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1616. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_29> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1617. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_28> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1618. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_27> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1619. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_26> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1620. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_25> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1621. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_24> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1622. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_23> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1623. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_22> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1624. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_21> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1625. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_20> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1626. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_19> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1627. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_18> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1628. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_17> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1629. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_16> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1630. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_15> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1631. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_14> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1632. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_13> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1633. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_12> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1634. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_11> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1635. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_10> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1636. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_9> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1637. WARNING:Xst:1293 - FF/Latch <bus_wishbone_dat_r_8> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1638. INFO:Xst:2261 - The FF/Latch <i_cyc_o> in Unit <lm32_instruction_unit> is equivalent to the following FF/Latch, which will be removed : <i_stb_o>
  1639. INFO:Xst:2261 - The FF/Latch <interface_adr_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <adr_offset_r>
  1640. WARNING:Xst:1710 - FF/Latch <bus_error_f> (without init value) has a constant value of 0 in block <lm32_instruction_unit>. This FF/Latch will be trimmed during the optimization process.
  1641. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bus_error_d> (without init value) has a constant value of 0 in block <lm32_instruction_unit>. This FF/Latch will be trimmed during the optimization process.
  1642. Analyzing FSM <MFsm> for best encoding.
  1643. Optimizing FSM <FSM_1> on signal <cache_state[1:3]> with user encoding.
  1644. -------------------
  1645. State | Encoding
  1646. -------------------
  1647. 000 | 000
  1648. 001 | 001
  1649. 010 | 010
  1650. 011 | 011
  1651. 100 | 100
  1652. -------------------
  1653. Analyzing FSM <MFsm> for best encoding.
  1654. Optimizing FSM <FSM_0> on signal <minicon_state[1:16]> with one-hot encoding.
  1655. ---------------------------
  1656. State | Encoding
  1657. ---------------------------
  1658. 0000 | 0000000000000001
  1659. 0111 | 0000000000000010
  1660. 0110 | 0000000000000100
  1661. 0001 | 0000000000001000
  1662. 0011 | 0000000000010000
  1663. 0101 | 0000000000100000
  1664. 0010 | 0000000001000000
  1665. 0100 | 0000000010000000
  1666. 1011 | 0000000100000000
  1667. 1001 | 0000001000000000
  1668. 1010 | 0000010000000000
  1669. 1100 | 0000100000000000
  1670. 1000 | 0001000000000000
  1671. 1101 | 0010000000000000
  1672. 1110 | 0100000000000000
  1673. 1111 | 1000000000000000
  1674. ---------------------------
  1675. Analyzing FSM <MFsm> for best encoding.
  1676. Optimizing FSM <lm32_cpu/instruction_unit/icache/FSM_2> on signal <state[1:2]> with gray encoding.
  1677. -------------------
  1678. State | Encoding
  1679. -------------------
  1680. 0001 | 00
  1681. 0010 | 01
  1682. 0100 | 11
  1683. 1000 | 10
  1684. -------------------
  1685. Analyzing FSM <MFsm> for best encoding.
  1686. Optimizing FSM <lm32_cpu/load_store_unit/dcache/FSM_3> on signal <state[1:2]> with gray encoding.
  1687. -------------------
  1688. State | Encoding
  1689. -------------------
  1690. 001 | 00
  1691. 010 | 01
  1692. 100 | 11
  1693. -------------------
  1694. Analyzing FSM <MFsm> for best encoding.
  1695. Optimizing FSM <lm32_cpu/mc_arithmetic/FSM_4> on signal <state[1:2]> with sequential encoding.
  1696. -------------------
  1697. State | Encoding
  1698. -------------------
  1699. 000 | 00
  1700. 011 | 01
  1701. 010 | 10
  1702. -------------------
  1703. WARNING:Xst:2677 - Node <Mmult_n00233> of sequential type is unconnected in block <lm32_multiplier>.
  1704. WARNING:Xst:2677 - Node <Mram_storage_29> of sequential type is unconnected in block <top>.
  1705. WARNING:Xst:2677 - Node <Mram_storage_19> of sequential type is unconnected in block <top>.
  1706. WARNING:Xst:1710 - FF/Latch <i_adr_o_0> (without init value) has a constant value of 0 in block <lm32_instruction_unit>. This FF/Latch will be trimmed during the optimization process.
  1707. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <i_adr_o_1> (without init value) has a constant value of 0 in block <lm32_instruction_unit>. This FF/Latch will be trimmed during the optimization process.
  1708. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <i_cti_o_1> (without init value) has a constant value of 1 in block <lm32_instruction_unit>. This FF/Latch will be trimmed during the optimization process.
  1709. WARNING:Xst:1710 - FF/Latch <d_cti_o_1> (without init value) has a constant value of 1 in block <lm32_load_store_unit>. This FF/Latch will be trimmed during the optimization process.
  1710. INFO:Xst:2261 - The FF/Latch <i_cti_o_0> in Unit <lm32_instruction_unit> is equivalent to the following FF/Latch, which will be removed : <i_cti_o_2>
  1711. INFO:Xst:2261 - The FF/Latch <d_cti_o_0> in Unit <lm32_load_store_unit> is equivalent to the following FF/Latch, which will be removed : <d_cti_o_2>
  1712.  
  1713. Optimizing unit <top> ...
  1714.  
  1715. Optimizing unit <lm32_cpu> ...
  1716.  
  1717. Optimizing unit <lm32_interrupt> ...
  1718.  
  1719. Optimizing unit <lm32_instruction_unit> ...
  1720.  
  1721. Optimizing unit <lm32_icache> ...
  1722.  
  1723. Optimizing unit <lm32_ram_1> ...
  1724.  
  1725. Optimizing unit <lm32_ram_2> ...
  1726.  
  1727. Optimizing unit <lm32_load_store_unit> ...
  1728.  
  1729. Optimizing unit <lm32_dcache> ...
  1730.  
  1731. Optimizing unit <lm32_shifter> ...
  1732.  
  1733. Optimizing unit <lm32_multiplier> ...
  1734.  
  1735. Optimizing unit <lm32_mc_arithmetic> ...
  1736.  
  1737. Optimizing unit <lm32_decoder> ...
  1738. WARNING:Xst:1710 - FF/Latch <lm32_cpu/bus_error_x> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1739. WARNING:Xst:2677 - Node <lm32_cpu/instruction_unit/i_cti_o_0> of sequential type is unconnected in block <top>.
  1740. WARNING:Xst:2677 - Node <lm32_cpu/load_store_unit/d_cti_o_0> of sequential type is unconnected in block <top>.
  1741. WARNING:Xst:2677 - Node <lm32_cpu/load_store_unit/d_adr_o_1> of sequential type is unconnected in block <top>.
  1742. WARNING:Xst:2677 - Node <lm32_cpu/load_store_unit/d_adr_o_0> of sequential type is unconnected in block <top>.
  1743. WARNING:Xst:2677 - Node <lm32_cpu/load_store_unit/dcache/refill_address_3> of sequential type is unconnected in block <top>.
  1744. WARNING:Xst:2677 - Node <lm32_cpu/load_store_unit/dcache/refill_address_2> of sequential type is unconnected in block <top>.
  1745. WARNING:Xst:2677 - Node <lm32_cpu/load_store_unit/dcache/refill_address_1> of sequential type is unconnected in block <top>.
  1746. WARNING:Xst:2677 - Node <lm32_cpu/load_store_unit/dcache/refill_address_0> of sequential type is unconnected in block <top>.
  1747. INFO:Xst:2399 - RAMs <Mram_tag_mem29>, <Mram_tag_mem30> are equivalent, second RAM is removed
  1748. WARNING:Xst:1293 - FF/Latch <ddrphy_bitslip_cnt_1> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1749. WARNING:Xst:1293 - FF/Latch <ddrphy_bitslip_cnt_2> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1750. WARNING:Xst:1293 - FF/Latch <ddrphy_bitslip_cnt_3> has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
  1751. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_2>
  1752. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_3>
  1753. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_4>
  1754. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_5>
  1755. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_6>
  1756. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_7>
  1757. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_8>
  1758. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/dcache/memories[0].way_0_tag_ram/ra_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/dcache/memories[0].data_memories.way_0_data_ram/ra_9>
  1759. INFO:Xst:2261 - The FF/Latch <lm32_cpu/direction_x> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/logic_op_x_3>
  1760. INFO:Xst:2261 - The FF/Latch <lm32_cpu/condition_x_0> in Unit <top> is equivalent to the following 2 FFs/Latches, which will be removed : <lm32_cpu/logic_op_x_0> <lm32_cpu/size_x_0>
  1761. INFO:Xst:2261 - The FF/Latch <lm32_cpu/condition_x_1> in Unit <top> is equivalent to the following 2 FFs/Latches, which will be removed : <lm32_cpu/logic_op_x_1> <lm32_cpu/size_x_1>
  1762. INFO:Xst:2261 - The FF/Latch <lm32_cpu/condition_x_2> in Unit <top> is equivalent to the following 2 FFs/Latches, which will be removed : <lm32_cpu/logic_op_x_2> <lm32_cpu/sign_extend_x>
  1763. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_0>
  1764. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_1>
  1765. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_2>
  1766. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_3>
  1767. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_4>
  1768. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_5>
  1769. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_8> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_6>
  1770. INFO:Xst:2261 - The FF/Latch <lm32_cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_9> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_7>
  1771. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_store_unit/d_cyc_o> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/load_store_unit/d_stb_o>
  1772. INFO:Xst:2261 - The FF/Latch <lm32_cpu/load_x> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <lm32_cpu/w_result_sel_load_x>
  1773.  
  1774. Mapping all equations...
  1775. Building and optimizing final netlist ...
  1776. Found area constraint ratio of 100 (+ 0) on block top, actual ratio is 15.
  1777. INFO:Xst:2261 - The FF/Latch <lm32_cpu/direction_x> in Unit <top> is equivalent to the following 2 FFs/Latches, which will be removed : <lm32_cpu/m_result_sel_compare_x_BRB0> <lm32_cpu/m_bypass_enable_x_BRB5>
  1778.  
  1779. Pipelining and Register Balancing Report ...
  1780.  
  1781. Processing Unit <top> :
  1782. Register(s) ddrphy_rddata_sr_1 has(ve) been backward balanced into : ddrphy_rddata_sr_1_BRB0 ddrphy_rddata_sr_1_BRB1 ddrphy_rddata_sr_1_BRB2 ddrphy_rddata_sr_1_BRB3 ddrphy_rddata_sr_1_BRB4 ddrphy_rddata_sr_1_BRB5.
  1783. Register(s) ddrphy_rddata_sr_2 has(ve) been backward balanced into : ddrphy_rddata_sr_2_BRB0 ddrphy_rddata_sr_2_BRB1 ddrphy_rddata_sr_2_BRB2 ddrphy_rddata_sr_2_BRB3 ddrphy_rddata_sr_2_BRB4 ddrphy_rddata_sr_2_BRB5.
  1784. Register(s) ddrphy_rddata_sr_3 has(ve) been backward balanced into : ddrphy_rddata_sr_3_BRB0 ddrphy_rddata_sr_3_BRB1 ddrphy_rddata_sr_3_BRB2 ddrphy_rddata_sr_3_BRB3 ddrphy_rddata_sr_3_BRB4 ddrphy_rddata_sr_3_BRB5.
  1785. Register(s) ddrphy_rddata_sr_4 has(ve) been backward balanced into : ddrphy_rddata_sr_4_BRB0 ddrphy_rddata_sr_4_BRB1 ddrphy_rddata_sr_4_BRB2 ddrphy_rddata_sr_4_BRB3 ddrphy_rddata_sr_4_BRB4 ddrphy_rddata_sr_4_BRB5.
  1786. Register(s) ddrphy_record0_cas_n has(ve) been backward balanced into : ddrphy_record0_cas_n_BRB0 .
  1787. Register(s) ddrphy_record0_cke has(ve) been backward balanced into : ddrphy_record0_cke_BRB0 .
  1788. Register(s) ddrphy_record0_ras_n has(ve) been backward balanced into : ddrphy_record0_ras_n_BRB0 ddrphy_record0_ras_n_BRB1.
  1789. Register(s) ddrphy_record0_we_n has(ve) been backward balanced into : ddrphy_record0_we_n_BRB0 .
  1790. Register(s) ddrphy_record1_cas_n has(ve) been backward balanced into : ddrphy_record1_cas_n_BRB0 ddrphy_record1_cas_n_BRB1.
  1791. Register(s) ddrphy_record1_ras_n has(ve) been backward balanced into : ddrphy_record1_ras_n_BRB0 ddrphy_record1_ras_n_BRB1.
  1792. Register(s) ddrphy_record1_we_n has(ve) been backward balanced into : ddrphy_record1_we_n_BRB0 .
  1793. Register(s) lm32_cpu/branch_predict_x has(ve) been backward balanced into : lm32_cpu/branch_predict_x_BRB0 lm32_cpu/branch_predict_x_BRB1.
  1794. Register(s) lm32_cpu/branch_x has(ve) been backward balanced into : lm32_cpu/branch_x_BRB0 lm32_cpu/branch_x_BRB1 .
  1795. Register(s) lm32_cpu/m_bypass_enable_x has(ve) been backward balanced into : lm32_cpu/m_bypass_enable_x_BRB4 .
  1796. Register(s) lm32_cpu/m_result_sel_compare_x has(ve) been backward balanced into : lm32_cpu/m_result_sel_compare_x_BRB1 .
  1797. Register(s) lm32_cpu/m_result_sel_shift_x has(ve) been backward balanced into : lm32_cpu/m_result_sel_shift_x_BRB0 lm32_cpu/m_result_sel_shift_x_BRB1 lm32_cpu/m_result_sel_shift_x_BRB2 lm32_cpu/m_result_sel_shift_x_BRB3 lm32_cpu/m_result_sel_shift_x_BRB4.
  1798. Register(s) lm32_cpu/w_result_sel_load_m has(ve) been backward balanced into : lm32_cpu/w_result_sel_load_m_BRB1.
  1799. Register(s) lm32_cpu/w_result_sel_mul_m has(ve) been backward balanced into : lm32_cpu/w_result_sel_mul_m_BRB0 lm32_cpu/w_result_sel_mul_m_BRB1.
  1800. Register(s) lm32_cpu/w_result_sel_mul_x has(ve) been backward balanced into : lm32_cpu/w_result_sel_mul_x_BRB0 lm32_cpu/w_result_sel_mul_x_BRB2.
  1801. Unit <top> processed.
  1802. FlipFlop interface_adr_10 has been replicated 1 time(s)
  1803. FlipFlop interface_adr_11 has been replicated 1 time(s)
  1804. FlipFlop interface_adr_12 has been replicated 1 time(s)
  1805. FlipFlop interface_adr_13 has been replicated 1 time(s)
  1806. FlipFlop interface_adr_9 has been replicated 1 time(s)
  1807. FlipFlop lm32_cpu/exception_m has been replicated 1 time(s)
  1808. FlipFlop lm32_cpu/instruction_unit/i_cyc_o has been replicated 1 time(s)
  1809. FlipFlop lm32_cpu/instruction_unit/icache/state_FSM_FFd1 has been replicated 1 time(s)
  1810. FlipFlop lm32_cpu/load_store_unit/dcache/state_FSM_FFd1 has been replicated 1 time(s)
  1811.  
  1812. Final Macro Processing ...
  1813.  
  1814. Processing Unit <top> :
  1815. Found 2-bit shift register for signal <ddrphy_r_dfi_wrdata_en_1>.
  1816. Found 4-bit shift register for signal <minicon_state_FSM_FFd1>.
  1817. Found 4-bit shift register for signal <ddrphy_rddata_sr_1_BRB1>.
  1818. Found 4-bit shift register for signal <ddrphy_rddata_sr_1_BRB2>.
  1819. Found 4-bit shift register for signal <ddrphy_rddata_sr_1_BRB3>.
  1820. Found 4-bit shift register for signal <ddrphy_rddata_sr_1_BRB4>.
  1821. Found 4-bit shift register for signal <ddrphy_rddata_sr_1_BRB5>.
  1822. INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <ddrphy_rddata_sr_1_BRB0> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
  1823. Unit <top> processed.
  1824.  
  1825. =========================================================================
  1826. Final Register Report
  1827.  
  1828. Macro Statistics
  1829. # Registers : 2125
  1830. Flip-Flops : 2125
  1831. # Shift Registers : 7
  1832. 2-bit shift register : 1
  1833. 4-bit shift register : 6
  1834.  
  1835. =========================================================================
  1836.  
  1837. =========================================================================
  1838. * Partition Report *
  1839. =========================================================================
  1840.  
  1841. Partition Implementation Status
  1842. -------------------------------
  1843.  
  1844. No Partitions were found in this design.
  1845.  
  1846. -------------------------------
  1847.  
  1848. =========================================================================
  1849. * Design Summary *
  1850. =========================================================================
  1851.  
  1852. Top Level Output File Name : top.ngc
  1853.  
  1854. Primitive and Black Box Usage:
  1855. ------------------------------
  1856. # BELS : 3610
  1857. # GND : 1
  1858. # INV : 104
  1859. # LUT1 : 64
  1860. # LUT2 : 439
  1861. # LUT3 : 532
  1862. # LUT4 : 191
  1863. # LUT5 : 495
  1864. # LUT6 : 973
  1865. # MUXCY : 417
  1866. # MUXF7 : 39
  1867. # VCC : 1
  1868. # XORCY : 354
  1869. # FlipFlops/Latches : 2143
  1870. # FD : 71
  1871. # FDE : 94
  1872. # FDP : 4
  1873. # FDR : 499
  1874. # FDRE : 1378
  1875. # FDS : 10
  1876. # FDSE : 81
  1877. # ODDR2 : 6
  1878. # RAMS : 198
  1879. # RAM16X1D : 110
  1880. # RAM32X1D : 64
  1881. # RAMB16BWER : 22
  1882. # RAMB8BWER : 2
  1883. # Shift Registers : 7
  1884. # SRLC16E : 7
  1885. # Clock Buffers : 3
  1886. # BUFG : 3
  1887. # IO Buffers : 46
  1888. # BUFIO2 : 1
  1889. # IBUF : 2
  1890. # IBUFG : 1
  1891. # IOBUF : 16
  1892. # OBUF : 24
  1893. # OBUFT : 2
  1894. # DSPs : 3
  1895. # DSP48A1 : 3
  1896. # Others : 36
  1897. # BUFPLL : 1
  1898. # ISERDES2 : 16
  1899. # OSERDES2 : 18
  1900. # PLL_ADV : 1
  1901.  
  1902. Device utilization summary:
  1903. ---------------------------
  1904.  
  1905. Selected Device : 6slx45csg324-2
  1906.  
  1907.  
  1908. Slice Logic Utilization:
  1909. Number of Slice Registers: 2143 out of 54576 3%
  1910. Number of Slice LUTs: 3153 out of 27288 11%
  1911. Number used as Logic: 2798 out of 27288 10%
  1912. Number used as Memory: 355 out of 6408 5%
  1913. Number used as RAM: 348
  1914. Number used as SRL: 7
  1915.  
  1916. Slice Logic Distribution:
  1917. Number of LUT Flip Flop pairs used: 3888
  1918. Number with an unused Flip Flop: 1745 out of 3888 44%
  1919. Number with an unused LUT: 735 out of 3888 18%
  1920. Number of fully used LUT-FF pairs: 1408 out of 3888 36%
  1921. Number of unique control sets: 92
  1922.  
  1923. IO Utilization:
  1924. Number of IOs: 47
  1925. Number of bonded IOBs: 45 out of 218 20%
  1926.  
  1927. Specific Feature Utilization:
  1928. Number of Block RAM/FIFO: 23 out of 116 19%
  1929. Number using Block RAM only: 23
  1930. Number of BUFG/BUFGCTRLs: 3 out of 16 18%
  1931. Number of DSP48A1s: 3 out of 58 5%
  1932. Number of PLL_ADVs: 1 out of 4 25%
  1933.  
  1934. ---------------------------
  1935. Partition Resource Summary:
  1936. ---------------------------
  1937.  
  1938. No Partitions were found in this design.
  1939.  
  1940. ---------------------------
  1941.  
  1942.  
  1943. =========================================================================
  1944. Timing Report
  1945.  
  1946. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  1947. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  1948. GENERATED AFTER PLACE-and-ROUTE.
  1949.  
  1950. Clock Information:
  1951. ------------------
  1952. -----------------------------------+------------------------+-------+
  1953. Clock Signal | Clock buffer(FF name) | Load |
  1954. -----------------------------------+------------------------+-------+
  1955. clk100 | PLL_ADV:CLKOUT5 | 2281 |
  1956. clk100 | PLL_ADV:CLKOUT2 | 72 |
  1957. clk100 | PLL_ADV:CLKOUT3 | 4 |
  1958. -----------------------------------+------------------------+-------+
  1959.  
  1960. Asynchronous Control Signals Information:
  1961. ----------------------------------------
  1962. No asynchronous control signals found in this design
  1963.  
  1964. Timing Summary:
  1965. ---------------
  1966. Speed Grade: -2
  1967.  
  1968. Minimum period: 8.698ns (Maximum Frequency: 114.967MHz)
  1969. Minimum input arrival time before clock: 2.512ns
  1970. Maximum output required time after clock: 6.300ns
  1971. Maximum combinational path delay: 3.593ns
  1972.  
  1973. Timing Details:
  1974. ---------------
  1975. All values displayed in nanoseconds (ns)
  1976.  
  1977. =========================================================================
  1978. Timing constraint: Default period analysis for Clock 'clk100'
  1979. Clock period: 8.698ns (frequency: 114.967MHz)
  1980. Total number of paths / destination ports: 288467 / 7574
  1981. -------------------------------------------------------------------------
  1982. Delay: 13.917ns (Levels of Logic = 1)
  1983. Source: lm32_cpu/multiplier/Mmult_n0023 (DSP)
  1984. Destination: lm32_cpu/multiplier/Mmult_n00232 (DSP)
  1985. Source Clock: clk100 rising 0.6X
  1986. Destination Clock: clk100 rising 0.6X
  1987.  
  1988. Data Path: lm32_cpu/multiplier/Mmult_n0023 to lm32_cpu/multiplier/Mmult_n00232
  1989. Gate Net
  1990. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1991. ---------------------------------------- ------------
  1992. DSP48A1:CLK->P47 18 7.889 1.234 lm32_cpu/multiplier/Mmult_n0023 (lm32_cpu/multiplier/Mmult_n0023_P47_to_Mmult_n00231)
  1993. DSP48A1:C30->PCOUT47 1 3.149 0.000 lm32_cpu/multiplier/Mmult_n00231 (lm32_cpu/multiplier/Mmult_n00231_PCOUT_to_Mmult_n00232_PCIN_47)
  1994. DSP48A1:PCIN47 1.645 lm32_cpu/multiplier/Mmult_n00232
  1995. ----------------------------------------
  1996. Total 13.917ns (12.683ns logic, 1.234ns route)
  1997. (91.1% logic, 8.9% route)
  1998.  
  1999. =========================================================================
  2000. Timing constraint: Default OFFSET IN BEFORE for Clock 'clk100'
  2001. Total number of paths / destination ports: 131 / 131
  2002. -------------------------------------------------------------------------
  2003. Offset: 2.512ns (Levels of Logic = 1)
  2004. Source: reset (PAD)
  2005. Destination: FDPE (FF)
  2006. Destination Clock: clk100 rising 0.6X
  2007.  
  2008. Data Path: reset to FDPE
  2009. Gate Net
  2010. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  2011. ---------------------------------------- ------------
  2012. IBUF:I->O 2 1.328 0.725 reset_IBUF (reset_IBUF)
  2013. FDP:PRE 0.459 FDPE
  2014. ----------------------------------------
  2015. Total 2.512ns (1.787ns logic, 0.725ns route)
  2016. (71.1% logic, 28.9% route)
  2017.  
  2018. =========================================================================
  2019. Timing constraint: Default OFFSET OUT AFTER for Clock 'clk100'
  2020. Total number of paths / destination ports: 628 / 180
  2021. -------------------------------------------------------------------------
  2022. Offset: 6.300ns (Levels of Logic = 3)
  2023. Source: interface_we (FF)
  2024. Destination: OSERDES2:T4 (PAD)
  2025. Source Clock: clk100 rising 0.6X
  2026.  
  2027. Data Path: interface_we to OSERDES2:T4
  2028. Gate Net
  2029. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  2030. ---------------------------------------- ------------
  2031. FD:C->Q 21 0.525 1.310 interface_we (interface_we)
  2032. LUT6:I5->O 19 0.254 1.261 basesoc_csrbank0_sel_basesoc_interface0_we_AND_112_o1 (basesoc_csrbank0_sel_basesoc_interface0_we_AND_112_o)
  2033. LUT6:I5->O 4 0.254 1.234 phaseinjector0_command_issue_re1 (phaseinjector0_command_issue_re)
  2034. LUT6:I1->O 17 0.254 1.208 ddrphy_drive_dq_n01 (ddrphy_drive_dq_n0)
  2035. OSERDES2:T4 0.000 OSERDES2
  2036. ----------------------------------------
  2037. Total 6.300ns (1.287ns logic, 5.013ns route)
  2038. (20.4% logic, 79.6% route)
  2039.  
  2040. =========================================================================
  2041. Timing constraint: Default path analysis
  2042. Total number of paths / destination ports: 119 / 103
  2043. -------------------------------------------------------------------------
  2044. Delay: 3.593ns (Levels of Logic = 1)
  2045. Source: OSERDES2_15:OQ (PAD)
  2046. Destination: ddram_dq<15> (PAD)
  2047.  
  2048. Data Path: OSERDES2_15:OQ to ddram_dq<15>
  2049. Gate Net
  2050. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  2051. ---------------------------------------- ------------
  2052. OSERDES2:OQ 1 0.000 0.681 OSERDES2_15 (ddrphy_dq_o<15>)
  2053. IOBUF:I->IO 2.912 IOBUF_15 (ddram_dq<15>)
  2054. ----------------------------------------
  2055. Total 3.593ns (2.912ns logic, 0.681ns route)
  2056. (81.0% logic, 19.0% route)
  2057.  
  2058. =========================================================================
  2059.  
  2060. Cross Clock Domains Report:
  2061. --------------------------
  2062.  
  2063. Clock to Setup on destination clock clk100
  2064. ---------------+---------+---------+---------+---------+
  2065. | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
  2066. Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
  2067. ---------------+---------+---------+---------+---------+
  2068. clk100 | 13.917| | 2.270| |
  2069. ---------------+---------+---------+---------+---------+
  2070.  
  2071. =========================================================================
  2072.  
  2073.  
  2074. Total REAL time to Xst completion: 23.00 secs
  2075. Total CPU time to Xst completion: 22.86 secs
  2076.  
  2077. -->
  2078.  
  2079. Total memory usage is 302128 kilobytes
  2080.  
  2081. Number of errors : 0 ( 0 filtered)
  2082. Number of warnings : 217 ( 0 filtered)
  2083. Number of infos : 49 ( 0 filtered)
  2084.  
  2085. Release 14.7 - ngdbuild P.20131013 (nt64)
  2086. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  2087.  
  2088. Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -uc
  2089. top.ucf top.ngc top.ngd
  2090.  
  2091. Reading NGO file
  2092. "D:/cygwin64/home/fevi8970/misoc_basesoc_saturn/gateware/top.ngc" ...
  2093. Gathering constraint information from source properties...
  2094. Done.
  2095.  
  2096. Annotating constraints to design from ucf file "top.ucf" ...
  2097. Resolving constraint associations...
  2098. Checking Constraint Associations...
  2099. INFO:ConstraintSystem:178 - TNM 'PRDclk100', used in period specification
  2100. 'TSclk100', was traced into BUFIO2 instance BUFIO2. The following new TNM
  2101. groups and period specifications were generated at the BUFIO2 output(s):
  2102. DIVCLK: <TIMESPEC TS_crg_clk100b = PERIOD "crg_clk100b" TSclk100 HIGH 50%>
  2103.  
  2104. INFO:ConstraintSystem:178 - TNM 'crg_clk100b', used in period specification
  2105. 'TS_crg_clk100b', was traced into PLL_ADV instance PLL_ADV. The following new
  2106. TNM groups and period specifications were generated at the PLL_ADV output(s):
  2107.  
  2108. CLKOUT3: <TIMESPEC TS_crg_pll_3_ = PERIOD "crg_pll_3_" TS_crg_clk100b / 1.25
  2109. PHASE 5 ns HIGH 50%>
  2110.  
  2111. INFO:ConstraintSystem:178 - TNM 'crg_clk100b', used in period specification
  2112. 'TS_crg_clk100b', was traced into PLL_ADV instance PLL_ADV. The following new
  2113. TNM groups and period specifications were generated at the PLL_ADV output(s):
  2114.  
  2115. CLKOUT5: <TIMESPEC TS_crg_pll_5_ = PERIOD "crg_pll_5_" TS_crg_clk100b / 0.625
  2116. HIGH 50%>
  2117.  
  2118. INFO:ConstraintSystem:178 - TNM 'crg_clk100b', used in period specification
  2119. 'TS_crg_clk100b', was traced into PLL_ADV instance PLL_ADV. The following new
  2120. TNM groups and period specifications were generated at the PLL_ADV output(s):
  2121.  
  2122. CLKOUT0: <TIMESPEC TS_crg_pll_0_ = PERIOD "crg_pll_0_" TS_crg_clk100b / 2.5
  2123. HIGH 50%>
  2124.  
  2125. INFO:ConstraintSystem:178 - TNM 'crg_clk100b', used in period specification
  2126. 'TS_crg_clk100b', was traced into PLL_ADV instance PLL_ADV. The following new
  2127. TNM groups and period specifications were generated at the PLL_ADV output(s):
  2128.  
  2129. CLKOUT2: <TIMESPEC TS_crg_pll_2_ = PERIOD "crg_pll_2_" TS_crg_clk100b / 1.25
  2130. PHASE 6 ns HIGH 50%>
  2131.  
  2132. Done...
  2133.  
  2134. Checking expanded design ...
  2135.  
  2136. Partition Implementation Status
  2137. -------------------------------
  2138.  
  2139. No Partitions were found in this design.
  2140.  
  2141. -------------------------------
  2142.  
  2143. NGDBUILD Design Results Summary:
  2144. Number of errors: 0
  2145. Number of warnings: 0
  2146.  
  2147. Writing NGD file "top.ngd" ...
  2148. Total REAL time to NGDBUILD completion: 4 sec
  2149. Total CPU time to NGDBUILD completion: 4 sec
  2150.  
  2151. Writing NGDBUILD log file "top.bld"...
  2152.  
  2153. NGDBUILD done.
  2154. Release 14.7 - Map P.20131013 (nt64)
  2155. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  2156. Using target part "6slx45csg324-2".
  2157. Mapping design into LUTs...
  2158. Writing file top_map.ngm...
  2159. Running directed packing...
  2160. Running delay-based LUT packing...
  2161. Updating timing models...
  2162. INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
  2163. (.mrp).
  2164. Running timing-driven placement...
  2165. Total REAL time at the beginning of Placer: 9 secs
  2166. Total CPU time at the beginning of Placer: 8 secs
  2167.  
  2168. Phase 1.1 Initial Placement Analysis
  2169. Phase 1.1 Initial Placement Analysis (Checksum:40fc997) REAL time: 10 secs
  2170.  
  2171. Phase 2.7 Design Feasibility Check
  2172. Phase 2.7 Design Feasibility Check (Checksum:40fc997) REAL time: 10 secs
  2173.  
  2174. Phase 3.31 Local Placement Optimization
  2175. Phase 3.31 Local Placement Optimization (Checksum:40fc997) REAL time: 10 secs
  2176.  
  2177. Phase 4.2 Initial Placement for Architecture Specific Features
  2178.  
  2179. Phase 4.2 Initial Placement for Architecture Specific Features
  2180. (Checksum:bc7d087b) REAL time: 27 secs
  2181.  
  2182. Phase 5.36 Local Placement Optimization
  2183. Phase 5.36 Local Placement Optimization (Checksum:bc7d087b) REAL time: 27 secs
  2184.  
  2185. Phase 6.30 Global Clock Region Assignment
  2186. Phase 6.30 Global Clock Region Assignment (Checksum:bc7d087b) REAL time: 27 secs
  2187.  
  2188. Phase 7.3 Local Placement Optimization
  2189. Phase 7.3 Local Placement Optimization (Checksum:bc7d087b) REAL time: 27 secs
  2190.  
  2191. Phase 8.5 Local Placement Optimization
  2192. Phase 8.5 Local Placement Optimization (Checksum:bc7d087b) REAL time: 27 secs
  2193.  
  2194. Phase 9.8 Global Placement
  2195. ............................
  2196. ................................
  2197. ...................................................................
  2198. .................
  2199. Phase 9.8 Global Placement (Checksum:6af9f96e) REAL time: 55 secs
  2200.  
  2201. Phase 10.5 Local Placement Optimization
  2202. Phase 10.5 Local Placement Optimization (Checksum:6af9f96e) REAL time: 55 secs
  2203.  
  2204. Phase 11.18 Placement Optimization
  2205. Phase 11.18 Placement Optimization (Checksum:e409888e) REAL time: 1 mins
  2206.  
  2207. Phase 12.5 Local Placement Optimization
  2208. Phase 12.5 Local Placement Optimization (Checksum:e409888e) REAL time: 1 mins
  2209.  
  2210. Phase 13.34 Placement Validation
  2211. Phase 13.34 Placement Validation (Checksum:52a2e50c) REAL time: 1 mins 1 secs
  2212.  
  2213. Total REAL time to Placer completion: 1 mins 4 secs
  2214. Total CPU time to Placer completion: 1 mins 4 secs
  2215. Running post-placement packing...
  2216. Writing output files...
  2217.  
  2218. Design Summary:
  2219. Number of errors: 0
  2220. Number of warnings: 1
  2221. Slice Logic Utilization:
  2222. Number of Slice Registers: 2,140 out of 54,576 3%
  2223. Number used as Flip Flops: 2,137
  2224. Number used as Latches: 0
  2225. Number used as Latch-thrus: 0
  2226. Number used as AND/OR logics: 3
  2227. Number of Slice LUTs: 2,563 out of 27,288 9%
  2228. Number used as logic: 2,367 out of 27,288 8%
  2229. Number using O6 output only: 1,773
  2230. Number using O5 output only: 62
  2231. Number using O5 and O6: 532
  2232. Number used as ROM: 0
  2233. Number used as Memory: 183 out of 6,408 2%
  2234. Number used as Dual Port RAM: 176
  2235. Number using O6 output only: 4
  2236. Number using O5 output only: 0
  2237. Number using O5 and O6: 172
  2238. Number used as Single Port RAM: 0
  2239. Number used as Shift Register: 7
  2240. Number using O6 output only: 7
  2241. Number using O5 output only: 0
  2242. Number using O5 and O6: 0
  2243. Number used exclusively as route-thrus: 13
  2244. Number with same-slice register load: 11
  2245. Number with same-slice carry load: 2
  2246. Number with other load: 0
  2247.  
  2248. Slice Logic Distribution:
  2249. Number of occupied Slices: 1,046 out of 6,822 15%
  2250. Number of MUXCYs used: 460 out of 13,644 3%
  2251. Number of LUT Flip Flop pairs used: 3,263
  2252. Number with an unused Flip Flop: 1,357 out of 3,263 41%
  2253. Number with an unused LUT: 700 out of 3,263 21%
  2254. Number of fully used LUT-FF pairs: 1,206 out of 3,263 36%
  2255. Number of unique control sets: 95
  2256. Number of slice register sites lost
  2257. to control set restrictions: 180 out of 54,576 1%
  2258.  
  2259. A LUT Flip Flop pair for this architecture represents one LUT paired with
  2260. one Flip Flop within a slice. A control set is a unique combination of
  2261. clock, reset, set, and enable signals for a registered element.
  2262. The Slice Logic Distribution report is not meaningful if the design is
  2263. over-mapped for a non-slice resource or if Placement fails.
  2264.  
  2265. IO Utilization:
  2266. Number of bonded IOBs: 47 out of 218 21%
  2267. Number of LOCed IOBs: 47 out of 47 100%
  2268. IOB Flip Flops: 6
  2269.  
  2270. Specific Feature Utilization:
  2271. Number of RAMB16BWERs: 22 out of 116 18%
  2272. Number of RAMB8BWERs: 2 out of 232 1%
  2273. Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
  2274. Number used as BUFIO2s: 1
  2275. Number used as BUFIO2_2CLKs: 0
  2276. Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
  2277. Number of BUFG/BUFGMUXs: 3 out of 16 18%
  2278. Number used as BUFGs: 3
  2279. Number used as BUFGMUX: 0
  2280. Number of DCM/DCM_CLKGENs: 0 out of 8 0%
  2281. Number of ILOGIC2/ISERDES2s: 16 out of 376 4%
  2282. Number used as ILOGIC2s: 0
  2283. Number used as ISERDES2s: 16
  2284. Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
  2285. Number of OLOGIC2/OSERDES2s: 22 out of 376 5%
  2286. Number used as OLOGIC2s: 4
  2287. Number used as OSERDES2s: 18
  2288. Number of BSCANs: 0 out of 4 0%
  2289. Number of BUFHs: 0 out of 256 0%
  2290. Number of BUFPLLs: 1 out of 8 12%
  2291. Number of BUFPLL_MCBs: 0 out of 4 0%
  2292. Number of DSP48A1s: 3 out of 58 5%
  2293. Number of ICAPs: 0 out of 1 0%
  2294. Number of MCBs: 0 out of 2 0%
  2295. Number of PCILOGICSEs: 0 out of 2 0%
  2296. Number of PLL_ADVs: 1 out of 4 25%
  2297. Number of PMVs: 0 out of 1 0%
  2298. Number of STARTUPs: 0 out of 1 0%
  2299. Number of SUSPEND_SYNCs: 0 out of 1 0%
  2300.  
  2301. Average Fanout of Non-Clock Nets: 3.82
  2302.  
  2303. Peak Memory Usage: 568 MB
  2304. Total REAL time to MAP completion: 1 mins 6 secs
  2305. Total CPU time to MAP completion: 1 mins 6 secs
  2306.  
  2307. Mapping completed.
  2308. See MAP report file "top_map.mrp" for details.
  2309. Release 14.7 - par P.20131013 (nt64)
  2310. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  2311.  
  2312.  
  2313.  
  2314. Constraints file: top.pcf.
  2315. Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
  2316. "top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
  2317.  
  2318. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
  2319. Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
  2320.  
  2321.  
  2322. Device speed data version: "PRODUCTION 1.23 2013-10-13".
  2323.  
  2324.  
  2325.  
  2326. Device Utilization Summary:
  2327.  
  2328. Slice Logic Utilization:
  2329. Number of Slice Registers: 2,140 out of 54,576 3%
  2330. Number used as Flip Flops: 2,137
  2331. Number used as Latches: 0
  2332. Number used as Latch-thrus: 0
  2333. Number used as AND/OR logics: 3
  2334. Number of Slice LUTs: 2,563 out of 27,288 9%
  2335. Number used as logic: 2,367 out of 27,288 8%
  2336. Number using O6 output only: 1,773
  2337. Number using O5 output only: 62
  2338. Number using O5 and O6: 532
  2339. Number used as ROM: 0
  2340. Number used as Memory: 183 out of 6,408 2%
  2341. Number used as Dual Port RAM: 176
  2342. Number using O6 output only: 4
  2343. Number using O5 output only: 0
  2344. Number using O5 and O6: 172
  2345. Number used as Single Port RAM: 0
  2346. Number used as Shift Register: 7
  2347. Number using O6 output only: 7
  2348. Number using O5 output only: 0
  2349. Number using O5 and O6: 0
  2350. Number used exclusively as route-thrus: 13
  2351. Number with same-slice register load: 11
  2352. Number with same-slice carry load: 2
  2353. Number with other load: 0
  2354.  
  2355. Slice Logic Distribution:
  2356. Number of occupied Slices: 1,046 out of 6,822 15%
  2357. Number of MUXCYs used: 460 out of 13,644 3%
  2358. Number of LUT Flip Flop pairs used: 3,263
  2359. Number with an unused Flip Flop: 1,357 out of 3,263 41%
  2360. Number with an unused LUT: 700 out of 3,263 21%
  2361. Number of fully used LUT-FF pairs: 1,206 out of 3,263 36%
  2362. Number of slice register sites lost
  2363. to control set restrictions: 0 out of 54,576 0%
  2364.  
  2365. A LUT Flip Flop pair for this architecture represents one LUT paired with
  2366. one Flip Flop within a slice. A control set is a unique combination of
  2367. clock, reset, set, and enable signals for a registered element.
  2368. The Slice Logic Distribution report is not meaningful if the design is
  2369. over-mapped for a non-slice resource or if Placement fails.
  2370.  
  2371. IO Utilization:
  2372. Number of bonded IOBs: 47 out of 218 21%
  2373. Number of LOCed IOBs: 47 out of 47 100%
  2374. IOB Flip Flops: 6
  2375.  
  2376. Specific Feature Utilization:
  2377. Number of RAMB16BWERs: 22 out of 116 18%
  2378. Number of RAMB8BWERs: 2 out of 232 1%
  2379. Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
  2380. Number used as BUFIO2s: 1
  2381. Number used as BUFIO2_2CLKs: 0
  2382. Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
  2383. Number of BUFG/BUFGMUXs: 3 out of 16 18%
  2384. Number used as BUFGs: 3
  2385. Number used as BUFGMUX: 0
  2386. Number of DCM/DCM_CLKGENs: 0 out of 8 0%
  2387. Number of ILOGIC2/ISERDES2s: 16 out of 376 4%
  2388. Number used as ILOGIC2s: 0
  2389. Number used as ISERDES2s: 16
  2390. Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
  2391. Number of OLOGIC2/OSERDES2s: 22 out of 376 5%
  2392. Number used as OLOGIC2s: 4
  2393. Number used as OSERDES2s: 18
  2394. Number of BSCANs: 0 out of 4 0%
  2395. Number of BUFHs: 0 out of 256 0%
  2396. Number of BUFPLLs: 1 out of 8 12%
  2397. Number of BUFPLL_MCBs: 0 out of 4 0%
  2398. Number of DSP48A1s: 3 out of 58 5%
  2399. Number of ICAPs: 0 out of 1 0%
  2400. Number of MCBs: 0 out of 2 0%
  2401. Number of PCILOGICSEs: 0 out of 2 0%
  2402. Number of PLL_ADVs: 1 out of 4 25%
  2403. Number of PMVs: 0 out of 1 0%
  2404. Number of STARTUPs: 0 out of 1 0%
  2405. Number of SUSPEND_SYNCs: 0 out of 1 0%
  2406.  
  2407.  
  2408. Overall effort level (-ol): High
  2409. Router effort level (-rl): High
  2410.  
  2411. Starting initial Timing Analysis. REAL time: 5 secs
  2412. Finished initial Timing Analysis. REAL time: 5 secs
  2413.  
  2414. WARNING:Par:288 - The signal serial_cts_IBUF has no load. PAR will not attempt to route this signal.
  2415. WARNING:Par:288 - The signal serial_rts_IBUF has no load. PAR will not attempt to route this signal.
  2416. Starting Router
  2417.  
  2418.  
  2419. Phase 1 : 17717 unrouted; REAL time: 6 secs
  2420.  
  2421. Phase 2 : 15108 unrouted; REAL time: 7 secs
  2422.  
  2423. Phase 3 : 6421 unrouted; REAL time: 12 secs
  2424.  
  2425. Phase 4 : 6420 unrouted; (Setup:0, Hold:40818, Component Switching Limit:0) REAL time: 14 secs
  2426.  
  2427. Updating file: top.ncd with current fully routed design.
  2428.  
  2429. Phase 5 : 0 unrouted; (Setup:0, Hold:39589, Component Switching Limit:0) REAL time: 22 secs
  2430.  
  2431. Phase 6 : 0 unrouted; (Setup:0, Hold:39589, Component Switching Limit:0) REAL time: 22 secs
  2432.  
  2433. Phase 7 : 0 unrouted; (Setup:0, Hold:39589, Component Switching Limit:0) REAL time: 22 secs
  2434.  
  2435. Phase 8 : 0 unrouted; (Setup:0, Hold:39589, Component Switching Limit:0) REAL time: 22 secs
  2436.  
  2437. Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
  2438.  
  2439. Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
  2440. Total REAL time to Router completion: 23 secs
  2441. Total CPU time to Router completion: 24 secs
  2442.  
  2443. Partition Implementation Status
  2444. -------------------------------
  2445.  
  2446. No Partitions were found in this design.
  2447.  
  2448. -------------------------------
  2449.  
  2450. Generating "PAR" statistics.
  2451.  
  2452. **************************
  2453. Generating Clock Report
  2454. **************************
  2455.  
  2456. +---------------------+--------------+------+------+------------+-------------+
  2457. | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
  2458. +---------------------+--------------+------+------+------------+-------------+
  2459. | sys_clk | BUFGMUX_X2Y2| No | 732 | 0.170 | 1.879 |
  2460. +---------------------+--------------+------+------+------------+-------------+
  2461. | sdram_half_clk | BUFGMUX_X3Y13| No | 20 | 0.583 | 2.339 |
  2462. +---------------------+--------------+------+------+------------+-------------+
  2463. |crg_clk_sdram_half_s | | | | | |
  2464. | hifted | BUFGMUX_X2Y3| No | 4 | 0.000 | 2.427 |
  2465. +---------------------+--------------+------+------+------------+-------------+
  2466. | sdram_full_wr_clk | Local| | 34 | 0.028 | 1.541 |
  2467. +---------------------+--------------+------+------+------------+-------------+
  2468.  
  2469. * Net Skew is the difference between the minimum and maximum routing
  2470. only delays for the net. Note this is different from Clock Skew which
  2471. is reported in TRCE timing report. Clock Skew is the difference between
  2472. the minimum and maximum path delays which includes logic delays.
  2473.  
  2474. * The fanout is the number of component pins not the individual BEL loads,
  2475. for example SLICE loads not FF loads.
  2476.  
  2477. Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
  2478.  
  2479. Number of Timing Constraints that were not applied: 4
  2480.  
  2481. Asterisk (*) preceding a constraint indicates it was not met.
  2482. This may be due to a setup or hold violation.
  2483.  
  2484. ----------------------------------------------------------------------------------------------------------
  2485. Constraint | Check | Worst Case | Best Case | Timing | Timing
  2486. | | Slack | Achievable | Errors | Score
  2487. ----------------------------------------------------------------------------------------------------------
  2488. TS_crg_pll_2_ = PERIOD TIMEGRP "crg_pll_2 | SETUP | 0.064ns| 7.914ns| 0| 0
  2489. _" TS_crg_clk100b / 1.25 PHASE 6 ns | HOLD | 0.414ns| | 0| 0
  2490. HIGH 50% | | | | |
  2491. ----------------------------------------------------------------------------------------------------------
  2492. TS_crg_pll_5_ = PERIOD TIMEGRP "crg_pll_5 | SETUP | 0.312ns| 15.561ns| 0| 0
  2493. _" TS_crg_clk100b / 0.625 HIGH 50% | HOLD | 0.234ns| | 0| 0
  2494. ----------------------------------------------------------------------------------------------------------
  2495. TS_crg_clk100b = PERIOD TIMEGRP "crg_clk1 | MINLOWPULSE | 6.666ns| 3.334ns| 0| 0
  2496. 00b" TSclk100 HIGH 50% | | | | |
  2497. ----------------------------------------------------------------------------------------------------------
  2498. TS_crg_pll_3_ = PERIOD TIMEGRP "crg_pll_3 | MINPERIOD | 5.334ns| 2.666ns| 0| 0
  2499. _" TS_crg_clk100b / 1.25 PHASE 5 ns | | | | |
  2500. HIGH 50% | | | | |
  2501. ----------------------------------------------------------------------------------------------------------
  2502. TSclk100 = PERIOD TIMEGRP "PRDclk100" 10 | MINPERIOD | 8.948ns| 1.052ns| 0| 0
  2503. ns HIGH 50% | | | | |
  2504. ----------------------------------------------------------------------------------------------------------
  2505. TS_crg_pll_0_ = PERIOD TIMEGRP "crg_pll_0 | N/A | N/A| N/A| N/A| N/A
  2506. _" TS_crg_clk100b / 2.5 HIGH 50% | | | | |
  2507. ----------------------------------------------------------------------------------------------------------
  2508.  
  2509.  
  2510. Derived Constraint Report
  2511. Review Timing Report for more details on the following derived constraints.
  2512. To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
  2513. or "Run Timing Analysis" from Timing Analyzer (timingan).
  2514. Derived Constraints for TSclk100
  2515. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  2516. | | Period | Actual Period | Timing Errors | Paths Analyzed |
  2517. | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
  2518. | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
  2519. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  2520. |TSclk100 | 10.000ns| 1.052ns| 9.893ns| 0| 0| 0| 308516|
  2521. | TS_crg_clk100b | 10.000ns| 3.334ns| 9.893ns| 0| 0| 0| 308516|
  2522. | TS_crg_pll_3_ | 8.000ns| 2.666ns| N/A| 0| 0| 0| 0|
  2523. | TS_crg_pll_5_ | 16.000ns| 15.561ns| N/A| 0| 0| 308170| 0|
  2524. | TS_crg_pll_0_ | 4.000ns| N/A| N/A| 0| 0| 0| 0|
  2525. | TS_crg_pll_2_ | 8.000ns| 7.914ns| N/A| 0| 0| 346| 0|
  2526. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  2527.  
  2528. All constraints were met.
  2529. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
  2530. constraint is not analyzed due to the following: No paths covered by this
  2531. constraint; Other constraints intersect with this constraint; or This
  2532. constraint was disabled by a Path Tracing Control. Please run the Timespec
  2533. Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
  2534.  
  2535.  
  2536. Generating Pad Report.
  2537.  
  2538. All signals are completely routed.
  2539.  
  2540. WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
  2541.  
  2542. Total REAL time to PAR completion: 25 secs
  2543. Total CPU time to PAR completion: 26 secs
  2544.  
  2545. Peak Memory Usage: 531 MB
  2546.  
  2547. Placer: Placement generated during map.
  2548. Routing: Completed - No errors found.
  2549. Timing: Completed - No errors found.
  2550.  
  2551. Number of error messages: 0
  2552. Number of warning messages: 4
  2553. Number of info messages: 0
  2554.  
  2555. Writing design to file top.ncd
  2556.  
  2557.  
  2558.  
  2559. PAR done!
  2560. Release 14.7 - Bitgen P.20131013 (nt64)
  2561. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  2562. Loading device for application Rf_Device from file '6slx45.nph' in environment
  2563. C:\Xilinx\14.7\ISE_DS\ISE\.
  2564. "top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
  2565. Opened constraints file top.pcf.
  2566.  
  2567. Mon Nov 20 19:48:16 2017
  2568.  
  2569. INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER).
  2570. 9K Block RAM initialization data, both user defined and default, requires a
  2571. special bit stream format. For more information, please reference Xilinx
  2572. Answer Record 39999.
  2573. Running DRC.
  2574. WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
  2575. (RAMB8BWER). 9K Block RAM initialization data, both user defined and
  2576. default, may be incorrect and should not be used. For more information,
  2577. please reference Xilinx Answer Record 39999.
  2578. DRC detected 0 errors and 1 warnings. Please see the previously displayed
  2579. individual error or warning messages for more details.
  2580. Creating bit map...
  2581. Saving bit stream in "top.bit".
  2582. Saving bit stream in "top.bin".
  2583. Bitstream generation is complete.
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