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Hello world

krzys_h Jul 28th, 2019 94 Never
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer: krzys_h
  5. //
  6. // Create Date:    21:35:34 07/28/2019
  7. // Design Name:
  8. // Module Name:    helloWorld
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22. module uart_tx #(parameter baudrate = 9600, parameter clock_rate = 100000000) (
  23.     output reg tx,
  24.     input [7:0] data,
  25.     input do_send,
  26.     output reg done_send,
  27.     input CLK
  28. );
  29.  
  30. localparam clks_per_bit = clock_rate / baudrate;
  31. localparam counter_len = 32; // $clog2(clks_per_bit)
  32.  
  33. localparam STATE_IDLE = 0;
  34. localparam STATE_STARTBIT = 1;
  35. localparam STATE_DATA = 2;
  36. localparam STATE_STOPBIT = 3;
  37.  
  38. reg [7:0] send_buffer;
  39. reg [1:0] state = STATE_IDLE;
  40. reg [2:0] current_bit;
  41. reg [counter_len:0] clock_counter;
  42.  
  43. always @(posedge CLK)
  44. begin
  45.     case(state)
  46.         STATE_IDLE:
  47.             begin
  48.                 tx <= 1;
  49.                 done_send <= 0;
  50.                 if (do_send)
  51.                 begin
  52.                     send_buffer <= data;
  53.                     clock_counter <= 0;
  54.                     state <= STATE_STARTBIT;
  55.                 end
  56.             end
  57.         STATE_STARTBIT:
  58.             begin
  59.                 tx <= 0;
  60.                 if (clock_counter < clks_per_bit)
  61.                 begin
  62.                     clock_counter <= clock_counter + 1;
  63.                 end
  64.                 else
  65.                 begin
  66.                     clock_counter <= 0;
  67.                     current_bit <= 0;
  68.                     state <= STATE_DATA;
  69.                 end
  70.             end
  71.         STATE_DATA:
  72.             begin
  73.                 tx <= send_buffer[current_bit];
  74.                 if (clock_counter < clks_per_bit)
  75.                 begin
  76.                     clock_counter <= clock_counter + 1;
  77.                 end
  78.                 else
  79.                 begin
  80.                     clock_counter <= 0;
  81.                     if (current_bit == 7)
  82.                         state <= STATE_STOPBIT;
  83.                     else
  84.                         current_bit <= current_bit + 1;
  85.                 end
  86.             end
  87.         STATE_STOPBIT:
  88.             begin
  89.                 tx <= 1;
  90.                 if (clock_counter < clks_per_bit)
  91.                 begin
  92.                     clock_counter <= clock_counter + 1;
  93.                 end
  94.                 else
  95.                 begin
  96.                     state <= STATE_IDLE;
  97.                     done_send <= 1;
  98.                 end
  99.             end
  100.     endcase
  101. end
  102.  
  103. endmodule
  104.  
  105. module helloWorld(
  106.     output [3:3] IO_P1,
  107.     input CLK
  108. );
  109.  
  110. reg [31:0] counter = 0;
  111. reg [7:0] num = 0;
  112. parameter [7:0] str[0:13] = "Hello world!\r\n";
  113. reg do_send = 1;
  114.  
  115. uart_tx tx(
  116.     .tx(IO_P1[3]),
  117.     .CLK(CLK),
  118.     .data(str[num]),
  119.     .do_send(do_send),
  120.     .done_send(done_send)
  121. );
  122.  
  123. always @(posedge CLK)
  124. begin
  125.     if (counter == 100000000)
  126.     begin
  127.         counter <= 0;
  128.         num <= 0;
  129.         do_send <= 1;
  130.     end
  131.     else
  132.         counter <= counter + 1;
  133.        
  134.     if (do_send)
  135.     begin
  136.         do_send <= 0;
  137.     end
  138.    
  139.     if (done_send)
  140.     begin
  141.         if (num != 13)
  142.         begin
  143.             do_send <= 1;
  144.             num <= num + 1;
  145.         end
  146.         else
  147.         begin
  148.             do_send <= 0;
  149.         end
  150.     end
  151. end
  152.  
  153. endmodule
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