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  1. /dts-v1/;
  2.  
  3. / {
  4. interrupt-parent = <0x1>;
  5. #address-cells = <0x1>;
  6. #size-cells = <0x1>;
  7. model = "Xunlong Orange Pi PC Plus";
  8. compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3";
  9.  
  10. chosen {
  11. #address-cells = <0x1>;
  12. #size-cells = <0x1>;
  13. ranges;
  14. stdout-path = "serial0:115200n8";
  15.  
  16. framebuffer-hdmi {
  17. compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  18. allwinner,pipeline = "mixer0-lcd0-hdmi";
  19. clocks = <0x2 0x6 0x3 0x66 0x3 0x6f>;
  20. status = "disabled";
  21. };
  22.  
  23. framebuffer-tve {
  24. compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  25. allwinner,pipeline = "mixer1-lcd1-tve";
  26. clocks = <0x2 0x7 0x3 0x67>;
  27. status = "disabled";
  28. };
  29. };
  30.  
  31. sound {
  32. compatible = "simple-audio-card";
  33. simple-audio-card,format = "i2s";
  34. simple-audio-card,name = "allwinner-hdmi";
  35. simple-audio-card,mclk-fs = <0x100>;
  36. phandle = <0x3a>;
  37.  
  38. simple-audio-card,codec {
  39. sound-dai = <0x4>;
  40. };
  41.  
  42. simple-audio-card,cpu {
  43. sound-dai = <0x5>;
  44. dai-tdm-slot-num = <0x2>;
  45. dai-tdm-slot-width = <0x20>;
  46. };
  47. };
  48.  
  49. clocks {
  50. #address-cells = <0x1>;
  51. #size-cells = <0x1>;
  52. ranges;
  53.  
  54. osc24M_clk {
  55. #clock-cells = <0x0>;
  56. compatible = "fixed-clock";
  57. clock-frequency = <0x16e3600>;
  58. clock-accuracy = <0xc350>;
  59. clock-output-names = "osc24M";
  60. phandle = <0x12>;
  61. };
  62.  
  63. osc32k_clk {
  64. #clock-cells = <0x0>;
  65. compatible = "fixed-clock";
  66. clock-frequency = <0x8000>;
  67. clock-accuracy = <0xc350>;
  68. clock-output-names = "ext_osc32k";
  69. phandle = <0x26>;
  70. };
  71. };
  72.  
  73. opp_table0 {
  74. compatible = "operating-points-v2";
  75. opp-shared;
  76. phandle = <0x2c>;
  77.  
  78. opp-480000000 {
  79. opp-hz = <0x0 0x1c9c3800>;
  80. opp-microvolt = <0xfde80 0xfde80 0x13d620>;
  81. clock-latency-ns = <0x3b9b0>;
  82. };
  83.  
  84. opp-648000000 {
  85. opp-hz = <0x0 0x269fb200>;
  86. opp-microvolt = <0xfde80 0xfde80 0x13d620>;
  87. clock-latency-ns = <0x3b9b0>;
  88. };
  89.  
  90. opp-816000000 {
  91. opp-hz = <0x0 0x30a32c00>;
  92. opp-microvolt = <0x10c8e0 0x10c8e0 0x13d620>;
  93. clock-latency-ns = <0x3b9b0>;
  94. };
  95.  
  96. opp-960000000 {
  97. opp-hz = <0x0 0x39387000>;
  98. opp-microvolt = <0x124f80 0x124f80 0x13d620>;
  99. clock-latency-ns = <0x3b9b0>;
  100. };
  101.  
  102. opp-1008000000 {
  103. opp-hz = <0x0 0x3c14dc00>;
  104. opp-microvolt = <0x124f80 0x124f80 0x13d620>;
  105. clock-latency-ns = <0x3b9b0>;
  106. };
  107.  
  108. opp-1104000000 {
  109. opp-hz = <0x0 0x41cdb400>;
  110. opp-microvolt = <0x142440 0x142440 0x142440>;
  111. clock-latency-ns = <0x3b9b0>;
  112. };
  113.  
  114. opp-1200000000 {
  115. opp-hz = <0x0 0x47868c00>;
  116. opp-microvolt = <0x142440 0x142440 0x142440>;
  117. clock-latency-ns = <0x3b9b0>;
  118. };
  119.  
  120. opp-1296000000 {
  121. opp-hz = <0x0 0x4d3f6400>;
  122. opp-microvolt = <0x147260 0x147260 0x147260>;
  123. clock-latency-ns = <0x3b9b0>;
  124. };
  125.  
  126. opp-1368000000 {
  127. opp-hz = <0x0 0x518a0600>;
  128. opp-microvolt = <0x155cc0 0x155cc0 0x155cc0>;
  129. clock-latency-ns = <0x3b9b0>;
  130. };
  131. };
  132.  
  133. display-engine {
  134. compatible = "allwinner,sun8i-h3-display-engine";
  135. allwinner,pipelines = <0x6>;
  136. status = "okay";
  137. phandle = <0x3b>;
  138. };
  139.  
  140. soc {
  141. compatible = "simple-bus";
  142. #address-cells = <0x1>;
  143. #size-cells = <0x1>;
  144. ranges;
  145.  
  146. clock@1000000 {
  147. reg = <0x1000000 0x10000>;
  148. clocks = <0x3 0x30 0x3 0x65>;
  149. clock-names = "bus", "mod";
  150. resets = <0x3 0x22>;
  151. #clock-cells = <0x1>;
  152. #reset-cells = <0x1>;
  153. compatible = "allwinner,sun8i-h3-de2-clk";
  154. phandle = <0x2>;
  155. };
  156.  
  157. mixer@1100000 {
  158. compatible = "allwinner,sun8i-h3-de2-mixer-0";
  159. reg = <0x1100000 0x100000>;
  160. clocks = <0x2 0x0 0x2 0x6>;
  161. clock-names = "bus", "mod";
  162. resets = <0x2 0x0>;
  163. phandle = <0x6>;
  164.  
  165. ports {
  166. #address-cells = <0x1>;
  167. #size-cells = <0x0>;
  168.  
  169. port@1 {
  170. reg = <0x1>;
  171. phandle = <0x3c>;
  172.  
  173. endpoint {
  174. remote-endpoint = <0x7>;
  175. phandle = <0x8>;
  176. };
  177. };
  178. };
  179. };
  180.  
  181. dma-controller@1c02000 {
  182. compatible = "allwinner,sun8i-h3-dma";
  183. reg = <0x1c02000 0x1000>;
  184. interrupts = <0x0 0x32 0x4>;
  185. clocks = <0x3 0x15>;
  186. resets = <0x3 0x6>;
  187. #dma-cells = <0x1>;
  188. phandle = <0x17>;
  189. };
  190.  
  191. lcd-controller@1c0c000 {
  192. compatible = "allwinner,sun8i-h3-tcon-tv", "allwinner,sun8i-a83t-tcon-tv";
  193. reg = <0x1c0c000 0x1000>;
  194. interrupts = <0x0 0x56 0x4>;
  195. clocks = <0x3 0x2a 0x3 0x66>;
  196. clock-names = "ahb", "tcon-ch1";
  197. resets = <0x3 0x1b>;
  198. reset-names = "lcd";
  199. phandle = <0x3d>;
  200.  
  201. ports {
  202. #address-cells = <0x1>;
  203. #size-cells = <0x0>;
  204.  
  205. port@0 {
  206. reg = <0x0>;
  207. phandle = <0x3e>;
  208.  
  209. endpoint {
  210. remote-endpoint = <0x8>;
  211. phandle = <0x7>;
  212. };
  213. };
  214.  
  215. port@1 {
  216. #address-cells = <0x1>;
  217. #size-cells = <0x0>;
  218. reg = <0x1>;
  219. phandle = <0x3f>;
  220.  
  221. endpoint@1 {
  222. reg = <0x1>;
  223. remote-endpoint = <0x9>;
  224. phandle = <0x24>;
  225. };
  226. };
  227. };
  228. };
  229.  
  230. mmc@1c0f000 {
  231. reg = <0x1c0f000 0x1000>;
  232. pinctrl-names = "default";
  233. pinctrl-0 = <0xa>;
  234. resets = <0x3 0x7>;
  235. reset-names = "ahb";
  236. interrupts = <0x0 0x3c 0x4>;
  237. bus-width = <0x4>;
  238. status = "okay";
  239. #address-cells = <0x1>;
  240. #size-cells = <0x0>;
  241. compatible = "allwinner,sun7i-a20-mmc";
  242. clocks = <0x3 0x16 0x3 0x47 0x3 0x49 0x3 0x48>;
  243. clock-names = "ahb", "mmc", "output", "sample";
  244. vmmc-supply = <0xb>;
  245. cd-gpios = <0xc 0x5 0x6 0x1>;
  246. phandle = <0x40>;
  247. };
  248.  
  249. mmc@1c10000 {
  250. reg = <0x1c10000 0x1000>;
  251. pinctrl-names = "default";
  252. pinctrl-0 = <0xd>;
  253. resets = <0x3 0x8>;
  254. reset-names = "ahb";
  255. interrupts = <0x0 0x3d 0x4>;
  256. status = "okay";
  257. #address-cells = <0x1>;
  258. #size-cells = <0x0>;
  259. compatible = "allwinner,sun7i-a20-mmc";
  260. clocks = <0x3 0x17 0x3 0x4a 0x3 0x4c 0x3 0x4b>;
  261. clock-names = "ahb", "mmc", "output", "sample";
  262. vmmc-supply = <0xb>;
  263. mmc-pwrseq = <0xe>;
  264. bus-width = <0x4>;
  265. non-removable;
  266. phandle = <0x41>;
  267.  
  268. sdio_wifi@1 {
  269. reg = <0x1>;
  270. phandle = <0x42>;
  271. };
  272. };
  273.  
  274. mmc@1c11000 {
  275. reg = <0x1c11000 0x1000>;
  276. resets = <0x3 0x9>;
  277. reset-names = "ahb";
  278. interrupts = <0x0 0x3e 0x4>;
  279. status = "okay";
  280. #address-cells = <0x1>;
  281. #size-cells = <0x0>;
  282. compatible = "allwinner,sun7i-a20-mmc";
  283. clocks = <0x3 0x18 0x3 0x4d 0x3 0x4f 0x3 0x4e>;
  284. clock-names = "ahb", "mmc", "output", "sample";
  285. pinctrl-names = "default";
  286. pinctrl-0 = <0xf>;
  287. vmmc-supply = <0xb>;
  288. bus-width = <0x8>;
  289. non-removable;
  290. cap-mmc-hw-reset;
  291. phandle = <0x43>;
  292. };
  293.  
  294. eeprom@1c14000 {
  295. reg = <0x1c14000 0x400>;
  296. compatible = "allwinner,sun8i-h3-sid";
  297. #address-cells = <0x1>;
  298. #size-cells = <0x1>;
  299. phandle = <0x44>;
  300.  
  301. thermal-sensor-calibration@34 {
  302. reg = <0x34 0x4>;
  303. phandle = <0x2b>;
  304. };
  305. };
  306.  
  307. usb@1c19000 {
  308. compatible = "allwinner,sun8i-h3-musb";
  309. reg = <0x1c19000 0x400>;
  310. clocks = <0x3 0x20>;
  311. resets = <0x3 0x11>;
  312. interrupts = <0x0 0x47 0x4>;
  313. interrupt-names = "mc";
  314. phys = <0x10 0x0>;
  315. phy-names = "usb";
  316. extcon = <0x10 0x0>;
  317. dr_mode = "otg";
  318. status = "okay";
  319. phandle = <0x45>;
  320. };
  321.  
  322. phy@1c19400 {
  323. compatible = "allwinner,sun8i-h3-usb-phy";
  324. reg = <0x1c19400 0x2c 0x1c1a800 0x4 0x1c1b800 0x4 0x1c1c800 0x4 0x1c1d800 0x4>;
  325. reg-names = "phy_ctrl", "pmu0", "pmu1", "pmu2", "pmu3";
  326. clocks = <0x3 0x58 0x3 0x59 0x3 0x5a 0x3 0x5b>;
  327. clock-names = "usb0_phy", "usb1_phy", "usb2_phy", "usb3_phy";
  328. resets = <0x3 0x0 0x3 0x1 0x3 0x2 0x3 0x3>;
  329. reset-names = "usb0_reset", "usb1_reset", "usb2_reset", "usb3_reset";
  330. status = "okay";
  331. #phy-cells = <0x1>;
  332. usb0_id_det-gpios = <0xc 0x6 0xc 0x0>;
  333. usb0_vbus-supply = <0x11>;
  334. phandle = <0x10>;
  335. };
  336.  
  337. usb@1c1a000 {
  338. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  339. reg = <0x1c1a000 0x100>;
  340. interrupts = <0x0 0x48 0x4>;
  341. clocks = <0x3 0x21 0x3 0x25>;
  342. resets = <0x3 0x12 0x3 0x16>;
  343. status = "okay";
  344. phandle = <0x46>;
  345. };
  346.  
  347. usb@1c1a400 {
  348. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  349. reg = <0x1c1a400 0x100>;
  350. interrupts = <0x0 0x49 0x4>;
  351. clocks = <0x3 0x21 0x3 0x25 0x3 0x5c>;
  352. resets = <0x3 0x12 0x3 0x16>;
  353. status = "okay";
  354. phandle = <0x47>;
  355. };
  356.  
  357. usb@1c1b000 {
  358. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  359. reg = <0x1c1b000 0x100>;
  360. interrupts = <0x0 0x4a 0x4>;
  361. clocks = <0x3 0x22 0x3 0x26>;
  362. resets = <0x3 0x13 0x3 0x17>;
  363. phys = <0x10 0x1>;
  364. phy-names = "usb";
  365. status = "okay";
  366. phandle = <0x48>;
  367. };
  368.  
  369. usb@1c1b400 {
  370. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  371. reg = <0x1c1b400 0x100>;
  372. interrupts = <0x0 0x4b 0x4>;
  373. clocks = <0x3 0x22 0x3 0x26 0x3 0x5d>;
  374. resets = <0x3 0x13 0x3 0x17>;
  375. phys = <0x10 0x1>;
  376. phy-names = "usb";
  377. status = "okay";
  378. phandle = <0x49>;
  379. };
  380.  
  381. usb@1c1c000 {
  382. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  383. reg = <0x1c1c000 0x100>;
  384. interrupts = <0x0 0x4c 0x4>;
  385. clocks = <0x3 0x23 0x3 0x27>;
  386. resets = <0x3 0x14 0x3 0x18>;
  387. phys = <0x10 0x2>;
  388. phy-names = "usb";
  389. status = "okay";
  390. phandle = <0x4a>;
  391. };
  392.  
  393. usb@1c1c400 {
  394. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  395. reg = <0x1c1c400 0x100>;
  396. interrupts = <0x0 0x4d 0x4>;
  397. clocks = <0x3 0x23 0x3 0x27 0x3 0x5e>;
  398. resets = <0x3 0x14 0x3 0x18>;
  399. phys = <0x10 0x2>;
  400. phy-names = "usb";
  401. status = "okay";
  402. phandle = <0x4b>;
  403. };
  404.  
  405. usb@1c1d000 {
  406. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  407. reg = <0x1c1d000 0x100>;
  408. interrupts = <0x0 0x4e 0x4>;
  409. clocks = <0x3 0x24 0x3 0x28>;
  410. resets = <0x3 0x15 0x3 0x19>;
  411. phys = <0x10 0x3>;
  412. phy-names = "usb";
  413. status = "okay";
  414. phandle = <0x4c>;
  415. };
  416.  
  417. usb@1c1d400 {
  418. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  419. reg = <0x1c1d400 0x100>;
  420. interrupts = <0x0 0x4f 0x4>;
  421. clocks = <0x3 0x24 0x3 0x28 0x3 0x5f>;
  422. resets = <0x3 0x15 0x3 0x19>;
  423. phys = <0x10 0x3>;
  424. phy-names = "usb";
  425. status = "okay";
  426. phandle = <0x4d>;
  427. };
  428.  
  429. clock@1c20000 {
  430. reg = <0x1c20000 0x400>;
  431. clocks = <0x12 0x13 0x0>;
  432. clock-names = "hosc", "losc";
  433. #clock-cells = <0x1>;
  434. #reset-cells = <0x1>;
  435. compatible = "allwinner,sun8i-h3-ccu";
  436. phandle = <0x3>;
  437. };
  438.  
  439. pinctrl@1c20800 {
  440. reg = <0x1c20800 0x400>;
  441. interrupts = <0x0 0xb 0x4 0x0 0x11 0x4>;
  442. clocks = <0x3 0x36 0x12 0x13 0x0>;
  443. clock-names = "apb", "hosc", "losc";
  444. gpio-controller;
  445. #gpio-cells = <0x3>;
  446. interrupt-controller;
  447. #interrupt-cells = <0x3>;
  448. compatible = "allwinner,sun8i-h3-pinctrl";
  449. phandle = <0xc>;
  450.  
  451. csi-pins {
  452. pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
  453. function = "csi";
  454. phandle = <0x22>;
  455. };
  456.  
  457. csi_mclk_pin: csi-mclk-pin {
  458. pins = "PE1";
  459. function = "csi";
  460. };
  461.  
  462. emac-rgmii-pins {
  463. pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", "PD12", "PD13", "PD15", "PD16", "PD17";
  464. function = "emac";
  465. drive-strength = <0x28>;
  466. phandle = <0x4e>;
  467. };
  468.  
  469. i2c0-pins {
  470. pins = "PA11", "PA12";
  471. function = "i2c0";
  472. phandle = <0x1f>;
  473. };
  474.  
  475. i2c1-pins {
  476. pins = "PA18", "PA19";
  477. function = "i2c1";
  478. phandle = <0x20>;
  479. };
  480.  
  481. i2c2-pins {
  482. pins = "PE12", "PE13";
  483. function = "i2c2";
  484. bias-pull-up;
  485. phandle = <0x21>;
  486. };
  487.  
  488. i2s0-pins {
  489. pins = "PA18", "PA19", "PA20", "PA21";
  490. function = "i2s0";
  491. phandle = <0x4f>;
  492. };
  493.  
  494. i2s1-pins {
  495. pins = "PG10", "PG11", "PG12", "PG13";
  496. function = "i2s1";
  497. phandle = <0x50>;
  498. };
  499.  
  500. mmc0-pins {
  501. pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  502. function = "mmc0";
  503. drive-strength = <0x1e>;
  504. bias-pull-up;
  505. phandle = <0xa>;
  506. };
  507.  
  508. mmc1-pins {
  509. pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  510. function = "mmc1";
  511. drive-strength = <0x1e>;
  512. bias-pull-up;
  513. phandle = <0xd>;
  514. };
  515.  
  516. mmc2-8bit-pins {
  517. pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  518. function = "mmc2";
  519. drive-strength = <0x28>;
  520. bias-pull-up;
  521. phandle = <0xf>;
  522. };
  523.  
  524. spdif-tx-pin {
  525. pins = "PA17";
  526. function = "spdif";
  527. phandle = <0x51>;
  528. };
  529.  
  530. spi0-pins {
  531. pins = "PC0", "PC1", "PC2", "PC3";
  532. function = "spi0";
  533. phandle = <0x18>;
  534. };
  535.  
  536. spi1-pins {
  537. pins = "PA15", "PA16", "PA14", "PA13";
  538. function = "spi1";
  539. phandle = <0x19>;
  540. };
  541.  
  542. uart0-pa-pins {
  543. pins = "PA4", "PA5";
  544. function = "uart0";
  545. phandle = <0x1b>;
  546. };
  547.  
  548. uart1-pins {
  549. pins = "PG6", "PG7";
  550. function = "uart1";
  551. phandle = <0x1c>;
  552. };
  553.  
  554. uart1-rts-cts-pins {
  555. pins = "PG8", "PG9";
  556. function = "uart1";
  557. phandle = <0x52>;
  558. };
  559.  
  560. uart2-pins {
  561. pins = "PA0", "PA1";
  562. function = "uart2";
  563. phandle = <0x1d>;
  564. };
  565.  
  566. uart2-rts-cts-pins {
  567. pins = "PA2", "PA3";
  568. function = "uart2";
  569. phandle = <0x53>;
  570. };
  571.  
  572. uart3-pins {
  573. pins = "PA13", "PA14";
  574. function = "uart3";
  575. phandle = <0x1e>;
  576. };
  577.  
  578. uart3-rts-cts-pins {
  579. pins = "PA15", "PA16";
  580. function = "uart3";
  581. phandle = <0x54>;
  582. };
  583. };
  584.  
  585. timer@1c20c00 {
  586. compatible = "allwinner,sun8i-a23-timer";
  587. reg = <0x1c20c00 0xa0>;
  588. interrupts = <0x0 0x12 0x4 0x0 0x13 0x4>;
  589. clocks = <0x12>;
  590. };
  591.  
  592. ethernet@1c30000 {
  593. compatible = "allwinner,sun8i-h3-emac";
  594. syscon = <0x14>;
  595. reg = <0x1c30000 0x10000>;
  596. interrupts = <0x0 0x52 0x4>;
  597. interrupt-names = "macirq";
  598. resets = <0x3 0xc>;
  599. reset-names = "stmmaceth";
  600. clocks = <0x3 0x1b>;
  601. clock-names = "stmmaceth";
  602. status = "okay";
  603. phy-handle = <0x15>;
  604. phy-mode = "mii";
  605. phandle = <0x55>;
  606.  
  607. mdio {
  608. #address-cells = <0x1>;
  609. #size-cells = <0x0>;
  610. compatible = "snps,dwmac-mdio";
  611. phandle = <0x16>;
  612. };
  613.  
  614. mdio-mux {
  615. compatible = "allwinner,sun8i-h3-mdio-mux";
  616. #address-cells = <0x1>;
  617. #size-cells = <0x0>;
  618. mdio-parent-bus = <0x16>;
  619.  
  620. mdio@1 {
  621. compatible = "allwinner,sun8i-h3-mdio-internal";
  622. reg = <0x1>;
  623. #address-cells = <0x1>;
  624. #size-cells = <0x0>;
  625. phandle = <0x56>;
  626.  
  627. ethernet-phy@1 {
  628. compatible = "ethernet-phy-ieee802.3-c22";
  629. reg = <0x1>;
  630. clocks = <0x3 0x43>;
  631. resets = <0x3 0x27>;
  632. phandle = <0x15>;
  633. };
  634. };
  635.  
  636. mdio@2 {
  637. reg = <0x2>;
  638. #address-cells = <0x1>;
  639. #size-cells = <0x0>;
  640. phandle = <0x57>;
  641. };
  642. };
  643. };
  644.  
  645. spi@1c68000 {
  646. compatible = "allwinner,sun8i-h3-spi";
  647. reg = <0x1c68000 0x1000>;
  648. interrupts = <0x0 0x41 0x4>;
  649. clocks = <0x3 0x1e 0x3 0x52>;
  650. clock-names = "ahb", "mod";
  651. dmas = <0x17 0x17 0x17 0x17>;
  652. dma-names = "rx", "tx";
  653. pinctrl-names = "default";
  654. pinctrl-0 = <0x18>;
  655. resets = <0x3 0xf>;
  656. status = "disabled";
  657. #address-cells = <0x1>;
  658. #size-cells = <0x0>;
  659. phandle = <0x58>;
  660. };
  661.  
  662. spi@1c69000 {
  663. compatible = "allwinner,sun8i-h3-spi";
  664. reg = <0x1c69000 0x1000>;
  665. interrupts = <0x0 0x42 0x4>;
  666. clocks = <0x3 0x1f 0x3 0x53>;
  667. clock-names = "ahb", "mod";
  668. dmas = <0x17 0x18 0x17 0x18>;
  669. dma-names = "rx", "tx";
  670. pinctrl-names = "default";
  671. pinctrl-0 = <0x19>;
  672. resets = <0x3 0x10>;
  673. status = "disabled";
  674. #address-cells = <0x1>;
  675. #size-cells = <0x0>;
  676. phandle = <0x59>;
  677. };
  678.  
  679. watchdog@1c20ca0 {
  680. compatible = "allwinner,sun6i-a31-wdt";
  681. reg = <0x1c20ca0 0x20>;
  682. interrupts = <0x0 0x19 0x4>;
  683. clocks = <0x12>;
  684. phandle = <0x5a>;
  685. };
  686.  
  687. spdif@1c21000 {
  688. #sound-dai-cells = <0x0>;
  689. compatible = "allwinner,sun8i-h3-spdif";
  690. reg = <0x1c21000 0x400>;
  691. interrupts = <0x0 0xc 0x4>;
  692. clocks = <0x3 0x35 0x3 0x57>;
  693. resets = <0x3 0x29>;
  694. clock-names = "apb", "spdif";
  695. dmas = <0x17 0x2>;
  696. dma-names = "tx";
  697. status = "disabled";
  698. phandle = <0x5b>;
  699. };
  700.  
  701. pwm@1c21400 {
  702. compatible = "allwinner,sun8i-h3-pwm";
  703. reg = <0x1c21400 0x8>;
  704. clocks = <0x12>;
  705. #pwm-cells = <0x3>;
  706. status = "disabled";
  707. phandle = <0x5c>;
  708. };
  709.  
  710. i2s@1c22000 {
  711. #sound-dai-cells = <0x0>;
  712. compatible = "allwinner,sun8i-h3-i2s";
  713. reg = <0x1c22000 0x400>;
  714. interrupts = <0x0 0xd 0x4>;
  715. clocks = <0x3 0x38 0x3 0x54>;
  716. clock-names = "apb", "mod";
  717. dmas = <0x17 0x3 0x17 0x3>;
  718. resets = <0x3 0x2b>;
  719. dma-names = "rx", "tx";
  720. status = "disabled";
  721. phandle = <0x5d>;
  722. };
  723.  
  724. i2s@1c22400 {
  725. #sound-dai-cells = <0x0>;
  726. compatible = "allwinner,sun8i-h3-i2s";
  727. reg = <0x1c22400 0x400>;
  728. interrupts = <0x0 0xe 0x4>;
  729. clocks = <0x3 0x39 0x3 0x55>;
  730. clock-names = "apb", "mod";
  731. dmas = <0x17 0x4 0x17 0x4>;
  732. resets = <0x3 0x2c>;
  733. dma-names = "rx", "tx";
  734. status = "disabled";
  735. phandle = <0x5e>;
  736. };
  737.  
  738. i2s@1c22800 {
  739. #sound-dai-cells = <0x0>;
  740. compatible = "allwinner,sun8i-h3-i2s";
  741. reg = <0x1c22800 0x400>;
  742. interrupts = <0x0 0xf 0x4>;
  743. clocks = <0x3 0x3a 0x3 0x56>;
  744. clock-names = "apb", "mod";
  745. dmas = <0x17 0x1b>;
  746. resets = <0x3 0x2d>;
  747. dma-names = "tx";
  748. allwinner,playback-channels = <0x8>;
  749. phandle = <0x5>;
  750. };
  751.  
  752. codec@1c22c00 {
  753. #sound-dai-cells = <0x0>;
  754. compatible = "allwinner,sun8i-h3-codec";
  755. reg = <0x1c22c00 0x400>;
  756. interrupts = <0x0 0x1d 0x4>;
  757. clocks = <0x3 0x34 0x3 0x6d>;
  758. clock-names = "apb", "codec";
  759. resets = <0x3 0x28>;
  760. dmas = <0x17 0xf 0x17 0xf>;
  761. dma-names = "rx", "tx";
  762. allwinner,codec-analog-controls = <0x1a>;
  763. status = "okay";
  764. allwinner,audio-routing = "Line Out", "LINEOUT", "MIC1", "Mic", "Mic", "MBIAS";
  765. phandle = <0x5f>;
  766. };
  767.  
  768. serial@1c28000 {
  769. compatible = "snps,dw-apb-uart";
  770. reg = <0x1c28000 0x400>;
  771. interrupts = <0x0 0x0 0x4>;
  772. reg-shift = <0x2>;
  773. reg-io-width = <0x4>;
  774. clocks = <0x3 0x3e>;
  775. resets = <0x3 0x31>;
  776. dmas = <0x17 0x6 0x17 0x6>;
  777. dma-names = "rx", "tx";
  778. status = "okay";
  779. pinctrl-names = "default";
  780. pinctrl-0 = <0x1b>;
  781. phandle = <0x60>;
  782. };
  783.  
  784. serial@1c28400 {
  785. compatible = "snps,dw-apb-uart";
  786. reg = <0x1c28400 0x400>;
  787. interrupts = <0x0 0x1 0x4>;
  788. reg-shift = <0x2>;
  789. reg-io-width = <0x4>;
  790. clocks = <0x3 0x3f>;
  791. resets = <0x3 0x32>;
  792. dmas = <0x17 0x7 0x17 0x7>;
  793. dma-names = "rx", "tx";
  794. status = "disabled";
  795. pinctrl-names = "default";
  796. pinctrl-0 = <0x1c>;
  797. phandle = <0x61>;
  798. };
  799.  
  800. serial@1c28800 {
  801. compatible = "snps,dw-apb-uart";
  802. reg = <0x1c28800 0x400>;
  803. interrupts = <0x0 0x2 0x4>;
  804. reg-shift = <0x2>;
  805. reg-io-width = <0x4>;
  806. clocks = <0x3 0x40>;
  807. resets = <0x3 0x33>;
  808. dmas = <0x17 0x8 0x17 0x8>;
  809. dma-names = "rx", "tx";
  810. status = "disabled";
  811. pinctrl-names = "default";
  812. pinctrl-0 = <0x1d>;
  813. phandle = <0x62>;
  814. };
  815.  
  816. serial@1c28c00 {
  817. compatible = "snps,dw-apb-uart";
  818. reg = <0x1c28c00 0x400>;
  819. interrupts = <0x0 0x3 0x4>;
  820. reg-shift = <0x2>;
  821. reg-io-width = <0x4>;
  822. clocks = <0x3 0x41>;
  823. resets = <0x3 0x34>;
  824. dmas = <0x17 0x9 0x17 0x9>;
  825. dma-names = "rx", "tx";
  826. status = "disabled";
  827. pinctrl-names = "default";
  828. pinctrl-0 = <0x1e>;
  829. phandle = <0x63>;
  830. };
  831.  
  832. i2c@1c2ac00 {
  833. compatible = "allwinner,sun6i-a31-i2c";
  834. reg = <0x1c2ac00 0x400>;
  835. interrupts = <0x0 0x6 0x4>;
  836. clocks = <0x3 0x3b>;
  837. resets = <0x3 0x2e>;
  838. pinctrl-names = "default";
  839. pinctrl-0 = <0x1f>;
  840. status = "disabled";
  841. #address-cells = <0x1>;
  842. #size-cells = <0x0>;
  843. phandle = <0x64>;
  844. };
  845.  
  846. i2c@1c2b000 {
  847. compatible = "allwinner,sun6i-a31-i2c";
  848. reg = <0x1c2b000 0x400>;
  849. interrupts = <0x0 0x7 0x4>;
  850. clocks = <0x3 0x3c>;
  851. resets = <0x3 0x2f>;
  852. pinctrl-names = "default";
  853. pinctrl-0 = <0x20>;
  854. status = "disabled";
  855. #address-cells = <0x1>;
  856. #size-cells = <0x0>;
  857. phandle = <0x65>;
  858. };
  859.  
  860. /*
  861. i2c@1c2b400 {
  862. compatible = "allwinner,sun6i-a31-i2c";
  863. reg = <0x1c2b400 0x400>;
  864. interrupts = <0x0 0x8 0x4>;
  865. clocks = <0x3 0x3d>;
  866. resets = <0x3 0x30>;
  867. pinctrl-names = "default";
  868. pinctrl-0 = <0x21>;
  869. status = "disabled";
  870. #address-cells = <0x1>;
  871. #size-cells = <0x0>;
  872. phandle = <0x66>;
  873. };
  874. */
  875.  
  876. camxclk {
  877. /* Use a stable clock source with known fixed rate for MCLK */
  878. assigned-clocks = <0x3 107>;
  879. assigned-clock-parents = <0x12>;
  880. assigned-clock-rates = <24000000>;
  881. };
  882.  
  883. csi@1cb0000 {
  884. status = "okay";
  885. compatible = "allwinner,sun8i-h3-csi";
  886. reg = <0x1cb0000 0x1000>;
  887. interrupts = <0x0 0x54 0x4>;
  888. clocks = <0x3 0x2d 0x3 0x6a 0x3 0x62>;
  889. clock-names = "bus", "mod", "ram";
  890. resets = <0x3 0x1e>;
  891. pinctrl-names = "default";
  892. pinctrl-0 = <0x22>;
  893. phandle = <0x67>;
  894.  
  895. port {
  896. #address-cells = <1>;
  897. #size-cells = <0>;
  898.  
  899. /* Parallel bus endpoint */
  900. csi_ep: endpoint {
  901. remote-endpoint = <&ov5640_ep>;
  902. bus-width = <8>;
  903. hsync-active = <1>; /* Active high */
  904. vsync-active = <0>; /* Active low */
  905. data-active = <1>; /* Active high */
  906. pclk-sample = <1>; /* Rising */
  907. };
  908. };
  909. };
  910.  
  911. i2c2@1c2b400 {
  912. /*allows to check device by i2cdetect */
  913. compatible = "allwinner,sun6i-a31-i2c";
  914. reg = <0x1c2b400 0x400>;
  915. interrupts = <0x0 0x8 0x4>;
  916. clocks = <0x3 0x3d>;
  917. resets = <0x3 0x30>;
  918. pinctrl-names = "default";
  919. pinctrl-0 = <0x21>;
  920. #address-cells = <0x1>;
  921. #size-cells = <0x0>;
  922. phandle = <0x66>;
  923.  
  924. status = "okay";
  925.  
  926. ov5640: camera@3c {
  927. compatible = "ovti,ov5640";
  928. reg = <0x3c>;
  929. pinctrl-names = "default";
  930. //pinctrl-0 = <0x21>;
  931. pinctrl-0 = <&csi_mclk_pin>;
  932. clocks = <0x3 107>;
  933. clock-names = "xclk";
  934.  
  935. /*interrupts = <0x0 0x8 0x4>;
  936. resets = <0x3 0x30>;
  937. #address-cells = <0x1>;
  938. #size-cells = <0x0>;
  939. phandle = <0x66>;*/
  940.  
  941.  
  942.  
  943. AVDD-supply = <&reg_vcc_af_csi>;
  944. DOVDD-supply = <&reg_vdd_1v5_csi>;
  945. DVDD-supply = <&reg_vcc_csi>;
  946. reset-gpios = <0xc 4 14 1>; /* CSI-RST-R: PE14 */
  947. powerdown-gpios = <0xc 4 15 0>; /* CSI-STBY-R: PE15 */
  948.  
  949. port {
  950. ov5640_ep: endpoint {
  951. remote-endpoint = <&csi_ep>;
  952. bus-width = <8>;
  953. data-shift = <2>; /* lines 9:2 are used */
  954. hsync-active = <1>; /* Active high */
  955. vsync-active = <0>; /* Active low */
  956. data-active = <1>; /* Active high */
  957. pclk-sample = <1>; /* Rising */
  958. };
  959. };
  960. };
  961. };
  962.  
  963.  
  964. interrupt-controller@1c81000 {
  965. compatible = "arm,gic-400";
  966. reg = <0x1c81000 0x1000 0x1c82000 0x2000 0x1c84000 0x2000 0x1c86000 0x2000>;
  967. interrupt-controller;
  968. #interrupt-cells = <0x3>;
  969. interrupts = <0x1 0x9 0xf04>;
  970. phandle = <0x1>;
  971. };
  972.  
  973. /*
  974. camera@1cb0000 {
  975. compatible = "allwinner,sun8i-h3-csi";
  976. reg = <0x1cb0000 0x1000>;
  977. interrupts = <0x0 0x54 0x4>;
  978. clocks = <0x3 0x2d 0x3 0x6a 0x3 0x62>;
  979. clock-names = "bus", "mod", "ram";
  980. resets = <0x3 0x1e>;
  981. pinctrl-names = "default";
  982. pinctrl-0 = <0x22>;
  983. status = "disabled";
  984. phandle = <0x67>;
  985. };*/
  986.  
  987. hdmi@1ee0000 {
  988. #sound-dai-cells = <0x0>;
  989. compatible = "allwinner,sun8i-h3-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi";
  990. reg = <0x1ee0000 0x10000>;
  991. reg-io-width = <0x1>;
  992. interrupts = <0x0 0x58 0x4>;
  993. clocks = <0x3 0x2f 0x3 0x70 0x3 0x6f>;
  994. clock-names = "iahb", "isfr", "tmds";
  995. resets = <0x3 0x21>;
  996. reset-names = "ctrl";
  997. phys = <0x23>;
  998. phy-names = "phy";
  999. status = "okay";
  1000. phandle = <0x4>;
  1001.  
  1002. ports {
  1003. #address-cells = <0x1>;
  1004. #size-cells = <0x0>;
  1005.  
  1006. port@0 {
  1007. reg = <0x0>;
  1008. phandle = <0x68>;
  1009.  
  1010. endpoint {
  1011. remote-endpoint = <0x24>;
  1012. phandle = <0x9>;
  1013. };
  1014. };
  1015.  
  1016. port@1 {
  1017. reg = <0x1>;
  1018. phandle = <0x69>;
  1019.  
  1020. endpoint {
  1021. remote-endpoint = <0x25>;
  1022. phandle = <0x39>;
  1023. };
  1024. };
  1025. };
  1026. };
  1027.  
  1028. hdmi-phy@1ef0000 {
  1029. compatible = "allwinner,sun8i-h3-hdmi-phy";
  1030. reg = <0x1ef0000 0x10000>;
  1031. clocks = <0x3 0x2f 0x3 0x70 0x3 0x6>;
  1032. clock-names = "bus", "mod", "pll-0";
  1033. resets = <0x3 0x20>;
  1034. reset-names = "phy";
  1035. #phy-cells = <0x0>;
  1036. phandle = <0x23>;
  1037. };
  1038.  
  1039. rtc@1f00000 {
  1040. reg = <0x1f00000 0x400>;
  1041. interrupts = <0x0 0x28 0x4 0x0 0x29 0x4>;
  1042. clock-output-names = "osc32k", "osc32k-out", "iosc";
  1043. clocks = <0x26>;
  1044. #clock-cells = <0x1>;
  1045. compatible = "allwinner,sun8i-h3-rtc";
  1046. phandle = <0x13>;
  1047. };
  1048.  
  1049. clock@1f01400 {
  1050. compatible = "allwinner,sun8i-h3-r-ccu";
  1051. reg = <0x1f01400 0x100>;
  1052. clocks = <0x12 0x13 0x0 0x13 0x2 0x3 0x9>;
  1053. clock-names = "hosc", "losc", "iosc", "pll-periph";
  1054. #clock-cells = <0x1>;
  1055. #reset-cells = <0x1>;
  1056. phandle = <0x27>;
  1057. };
  1058.  
  1059. codec-analog@1f015c0 {
  1060. compatible = "allwinner,sun8i-h3-codec-analog";
  1061. reg = <0x1f015c0 0x4>;
  1062. phandle = <0x1a>;
  1063. };
  1064.  
  1065. ir@1f02000 {
  1066. compatible = "allwinner,sun6i-a31-ir";
  1067. clocks = <0x27 0x4 0x27 0xb>;
  1068. clock-names = "apb", "ir";
  1069. resets = <0x27 0x0>;
  1070. interrupts = <0x0 0x25 0x4>;
  1071. reg = <0x1f02000 0x400>;
  1072. status = "okay";
  1073. pinctrl-names = "default";
  1074. pinctrl-0 = <0x28>;
  1075. phandle = <0x6a>;
  1076. };
  1077.  
  1078. i2c@1f02400 {
  1079. compatible = "allwinner,sun6i-a31-i2c";
  1080. reg = <0x1f02400 0x400>;
  1081. interrupts = <0x0 0x2c 0x4>;
  1082. pinctrl-names = "default";
  1083. pinctrl-0 = <0x29>;
  1084. clocks = <0x27 0x9>;
  1085. resets = <0x27 0x5>;
  1086. status = "okay";
  1087. #address-cells = <0x1>;
  1088. #size-cells = <0x0>;
  1089. phandle = <0x6b>;
  1090.  
  1091. regulator@65 {
  1092. compatible = "silergy,sy8106a";
  1093. reg = <0x65>;
  1094. regulator-name = "vdd-cpux";
  1095. silergy,fixed-microvolt = <0x124f80>;
  1096. regulator-min-microvolt = <0xf4240>;
  1097. regulator-max-microvolt = <0x155cc0>;
  1098. regulator-ramp-delay = <0xc8>;
  1099. regulator-boot-on;
  1100. regulator-always-on;
  1101. phandle = <0x2d>;
  1102. };
  1103. };
  1104.  
  1105. pinctrl@1f02c00 {
  1106. compatible = "allwinner,sun8i-h3-r-pinctrl";
  1107. reg = <0x1f02c00 0x400>;
  1108. interrupts = <0x0 0x2d 0x4>;
  1109. clocks = <0x27 0x3 0x12 0x13 0x0>;
  1110. clock-names = "apb", "hosc", "losc";
  1111. gpio-controller;
  1112. #gpio-cells = <0x3>;
  1113. interrupt-controller;
  1114. #interrupt-cells = <0x3>;
  1115. phandle = <0x38>;
  1116.  
  1117. r-ir-rx-pin {
  1118. pins = "PL11";
  1119. function = "s_cir_rx";
  1120. phandle = <0x28>;
  1121. };
  1122.  
  1123. r-i2c-pins {
  1124. pins = "PL0", "PL1";
  1125. function = "s_i2c";
  1126. phandle = <0x29>;
  1127. };
  1128. };
  1129.  
  1130. system-control@1c00000 {
  1131. compatible = "allwinner,sun8i-h3-system-control";
  1132. reg = <0x1c00000 0x1000>;
  1133. #address-cells = <0x1>;
  1134. #size-cells = <0x1>;
  1135. ranges;
  1136. phandle = <0x14>;
  1137.  
  1138. sram@1d00000 {
  1139. compatible = "mmio-sram";
  1140. reg = <0x1d00000 0x80000>;
  1141. #address-cells = <0x1>;
  1142. #size-cells = <0x1>;
  1143. ranges = <0x0 0x1d00000 0x80000>;
  1144. phandle = <0x6c>;
  1145.  
  1146. sram-section@0 {
  1147. compatible = "allwinner,sun8i-h3-sram-c1", "allwinner,sun4i-a10-sram-c1";
  1148. reg = <0x0 0x80000>;
  1149. phandle = <0x2a>;
  1150. };
  1151. };
  1152. };
  1153.  
  1154. video-codec@1c0e000 {
  1155. compatible = "allwinner,sun8i-h3-video-engine";
  1156. reg = <0x1c0e000 0x1000>;
  1157. clocks = <0x3 0x29 0x3 0x6c 0x3 0x61>;
  1158. clock-names = "ahb", "mod", "ram";
  1159. resets = <0x3 0x1a>;
  1160. interrupts = <0x0 0x3a 0x4>;
  1161. allwinner,sram = <0x2a 0x1>;
  1162. };
  1163.  
  1164. gpu@1c40000 {
  1165. compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
  1166. reg = <0x1c40000 0x10000>;
  1167. interrupts = <0x0 0x61 0x4 0x0 0x62 0x4 0x0 0x63 0x4 0x0 0x64 0x4 0x0 0x66 0x4 0x0 0x67 0x4 0x0 0x65 0x4>;
  1168. interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1", "pmu";
  1169. clocks = <0x3 0x31 0x3 0x72>;
  1170. clock-names = "bus", "core";
  1171. resets = <0x3 0x23>;
  1172. assigned-clocks = <0x3 0x72>;
  1173. assigned-clock-rates = <0x16e36000>;
  1174. phandle = <0x6d>;
  1175. };
  1176.  
  1177. ths@1c25000 {
  1178. compatible = "allwinner,sun8i-h3-ths";
  1179. reg = <0x1c25000 0x400>;
  1180. interrupts = <0x0 0x1f 0x4>;
  1181. resets = <0x3 0x2a>;
  1182. clocks = <0x3 0x37 0x3 0x45>;
  1183. clock-names = "bus", "mod";
  1184. nvmem-cells = <0x2b>;
  1185. nvmem-cell-names = "calibration";
  1186. #thermal-sensor-cells = <0x0>;
  1187. phandle = <0x32>;
  1188. };
  1189. };
  1190.  
  1191. cpus {
  1192. #address-cells = <0x1>;
  1193. #size-cells = <0x0>;
  1194.  
  1195. cpu@0 {
  1196. compatible = "arm,cortex-a7";
  1197. device_type = "cpu";
  1198. reg = <0x0>;
  1199. clocks = <0x3 0xe>;
  1200. clock-names = "cpu";
  1201. operating-points-v2 = <0x2c>;
  1202. #cooling-cells = <0x2>;
  1203. cpu-supply = <0x2d>;
  1204. phandle = <0x2e>;
  1205. };
  1206.  
  1207. cpu@1 {
  1208. compatible = "arm,cortex-a7";
  1209. device_type = "cpu";
  1210. reg = <0x1>;
  1211. clocks = <0x3 0xe>;
  1212. clock-names = "cpu";
  1213. operating-points-v2 = <0x2c>;
  1214. #cooling-cells = <0x2>;
  1215. phandle = <0x2f>;
  1216. };
  1217.  
  1218. cpu@2 {
  1219. compatible = "arm,cortex-a7";
  1220. device_type = "cpu";
  1221. reg = <0x2>;
  1222. clocks = <0x3 0xe>;
  1223. clock-names = "cpu";
  1224. operating-points-v2 = <0x2c>;
  1225. #cooling-cells = <0x2>;
  1226. phandle = <0x30>;
  1227. };
  1228.  
  1229. cpu@3 {
  1230. compatible = "arm,cortex-a7";
  1231. device_type = "cpu";
  1232. reg = <0x3>;
  1233. clocks = <0x3 0xe>;
  1234. clock-names = "cpu";
  1235. operating-points-v2 = <0x2c>;
  1236. #cooling-cells = <0x2>;
  1237. phandle = <0x31>;
  1238. };
  1239. };
  1240.  
  1241. pmu {
  1242. compatible = "arm,cortex-a7-pmu";
  1243. interrupts = <0x0 0x78 0x4 0x0 0x79 0x4 0x0 0x7a 0x4 0x0 0x7b 0x4>;
  1244. interrupt-affinity = <0x2e 0x2f 0x30 0x31>;
  1245. };
  1246.  
  1247. timer {
  1248. compatible = "arm,armv7-timer";
  1249. interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>;
  1250. };
  1251.  
  1252. thermal-zones {
  1253.  
  1254. cpu_thermal {
  1255. polling-delay-passive = <0xfa>;
  1256. polling-delay = <0x3e8>;
  1257. thermal-sensors = <0x32>;
  1258.  
  1259. trips {
  1260.  
  1261. cpu_warm {
  1262. temperature = <0x124f8>;
  1263. hysteresis = <0x7d0>;
  1264. type = "passive";
  1265. phandle = <0x33>;
  1266. };
  1267.  
  1268. cpu_hot_pre {
  1269. temperature = <0x13880>;
  1270. hysteresis = <0x7d0>;
  1271. type = "passive";
  1272. phandle = <0x34>;
  1273. };
  1274.  
  1275. cpu_hot {
  1276. temperature = <0x14c08>;
  1277. hysteresis = <0x7d0>;
  1278. type = "passive";
  1279. phandle = <0x35>;
  1280. };
  1281.  
  1282. cpu_very_hot_pre {
  1283. temperature = <0x15f90>;
  1284. hysteresis = <0x7d0>;
  1285. type = "passive";
  1286. phandle = <0x36>;
  1287. };
  1288.  
  1289. cpu_very_hot {
  1290. temperature = <0x17318>;
  1291. hysteresis = <0x7d0>;
  1292. type = "passive";
  1293. phandle = <0x37>;
  1294. };
  1295.  
  1296. cpu_crit {
  1297. temperature = <0x19a28>;
  1298. hysteresis = <0x7d0>;
  1299. type = "critical";
  1300. phandle = <0x6e>;
  1301. };
  1302. };
  1303.  
  1304. cooling-maps {
  1305.  
  1306. cpu_warm_limit_cpu {
  1307. trip = <0x33>;
  1308. cooling-device = <0x2e 0xffffffff 0x2>;
  1309. };
  1310.  
  1311. cpu_hot_pre_limit_cpu {
  1312. trip = <0x34>;
  1313. cooling-device = <0x2e 0x2 0x3>;
  1314. };
  1315.  
  1316. cpu_hot_limit_cpu {
  1317. trip = <0x35>;
  1318. cooling-device = <0x2e 0x3 0x4>;
  1319. };
  1320.  
  1321. cpu_very_hot_pre_limit_cpu {
  1322. trip = <0x36>;
  1323. cooling-device = <0x2e 0x5 0x6>;
  1324. };
  1325.  
  1326. cpu_very_hot_limit_cpu {
  1327. trip = <0x37>;
  1328. cooling-device = <0x2e 0x7 0xffffffff>;
  1329. };
  1330. };
  1331. };
  1332. };
  1333.  
  1334. ahci-5v {
  1335. compatible = "regulator-fixed";
  1336. regulator-name = "ahci-5v";
  1337. regulator-min-microvolt = <0x4c4b40>;
  1338. regulator-max-microvolt = <0x4c4b40>;
  1339. regulator-boot-on;
  1340. enable-active-high;
  1341. gpio = <0xc 0x1 0x8 0x0>;
  1342. status = "disabled";
  1343. phandle = <0x6f>;
  1344. };
  1345.  
  1346. usb0-vbus {
  1347. compatible = "regulator-fixed";
  1348. regulator-name = "usb0-vbus";
  1349. regulator-min-microvolt = <0x4c4b40>;
  1350. regulator-max-microvolt = <0x4c4b40>;
  1351. enable-active-high;
  1352. gpio = <0x38 0x0 0x2 0x0>;
  1353. status = "okay";
  1354. phandle = <0x11>;
  1355. };
  1356.  
  1357. usb1-vbus {
  1358. compatible = "regulator-fixed";
  1359. regulator-name = "usb1-vbus";
  1360. regulator-min-microvolt = <0x4c4b40>;
  1361. regulator-max-microvolt = <0x4c4b40>;
  1362. regulator-boot-on;
  1363. enable-active-high;
  1364. gpio = <0xc 0x7 0x6 0x0>;
  1365. status = "disabled";
  1366. phandle = <0x70>;
  1367. };
  1368.  
  1369. usb2-vbus {
  1370. compatible = "regulator-fixed";
  1371. regulator-name = "usb2-vbus";
  1372. regulator-min-microvolt = <0x4c4b40>;
  1373. regulator-max-microvolt = <0x4c4b40>;
  1374. regulator-boot-on;
  1375. enable-active-high;
  1376. gpio = <0xc 0x7 0x3 0x0>;
  1377. status = "disabled";
  1378. phandle = <0x71>;
  1379. };
  1380.  
  1381. vcc3v0 {
  1382. compatible = "regulator-fixed";
  1383. regulator-name = "vcc3v0";
  1384. regulator-min-microvolt = <0x2dc6c0>;
  1385. regulator-max-microvolt = <0x2dc6c0>;
  1386. phandle = <0x72>;
  1387. };
  1388.  
  1389. vcc3v3 {
  1390. compatible = "regulator-fixed";
  1391. regulator-name = "vcc3v3";
  1392. regulator-min-microvolt = <0x325aa0>;
  1393. regulator-max-microvolt = <0x325aa0>;
  1394. phandle = <0xb>;
  1395. };
  1396.  
  1397. vcc5v0 {
  1398. compatible = "regulator-fixed";
  1399. regulator-name = "vcc5v0";
  1400. regulator-min-microvolt = <0x4c4b40>;
  1401. regulator-max-microvolt = <0x4c4b40>;
  1402. phandle = <0x73>;
  1403. };
  1404.  
  1405. aliases {
  1406. ethernet0 = "/soc/ethernet@1c30000";
  1407. serial0 = "/soc/serial@1c28000";
  1408. ethernet1 = "/soc/mmc@1c10000/sdio_wifi@1";
  1409. };
  1410.  
  1411. connector {
  1412. compatible = "hdmi-connector";
  1413. type = [61 00];
  1414.  
  1415. port {
  1416.  
  1417. endpoint {
  1418. remote-endpoint = <0x39>;
  1419. phandle = <0x25>;
  1420. };
  1421. };
  1422. };
  1423.  
  1424. leds {
  1425. compatible = "gpio-leds";
  1426.  
  1427. pwr_led {
  1428. label = "orangepi:green:pwr";
  1429. gpios = <0x38 0x0 0xa 0x0>;
  1430. default-state = "on";
  1431. };
  1432.  
  1433. status_led {
  1434. label = "orangepi:red:status";
  1435. gpios = <0xc 0x0 0xf 0x0>;
  1436. };
  1437. };
  1438.  
  1439. r_gpio_keys {
  1440. compatible = "gpio-keys";
  1441.  
  1442. sw4 {
  1443. label = "sw4";
  1444. linux,code = <0x74>;
  1445. gpios = <0x38 0x0 0x3 0x1>;
  1446. };
  1447. };
  1448.  
  1449. wifi_pwrseq {
  1450. compatible = "mmc-pwrseq-simple";
  1451. reset-gpios = <0x38 0x0 0x7 0x1>;
  1452. phandle = <0xe>;
  1453. };
  1454.  
  1455.  
  1456.  
  1457. reg_vdd_1v5_csi: vdd-1v5-csi {
  1458. compatible = "regulator-fixed";
  1459. regulator-name = "vdd1v5-csi";
  1460. regulator-min-microvolt = <1500000>;
  1461. regulator-max-microvolt = <1500000>;
  1462. gpio = <0xc 0 17 0>; /* PA17 */
  1463. enable-active-high;
  1464. regulator-boot-on;
  1465. regulator-always-on;
  1466. };
  1467.  
  1468. reg_vcc_csi: vcc-csi {
  1469. compatible = "regulator-fixed";
  1470. regulator-name = "vcc-csi";
  1471. regulator-min-microvolt = <2800000>;
  1472. regulator-max-microvolt = <2800000>;
  1473. gpio = <0xc 6 11 0>; /* PG11 */
  1474. enable-active-high;
  1475. regulator-boot-on;
  1476. regulator-always-on;
  1477. };
  1478.  
  1479. reg_vcc_af_csi: vcc-af-csi {
  1480. compatible = "regulator-fixed";
  1481. regulator-name = "vcc-af-csi";
  1482. regulator-min-microvolt = <2800000>;
  1483. regulator-max-microvolt = <2800000>;
  1484. gpio = <0xc 6 13 0>; /* PG13 */
  1485. enable-active-high;
  1486. regulator-boot-on;
  1487. regulator-always-on;
  1488. };
  1489.  
  1490.  
  1491. __symbols__ {
  1492. sound_hdmi = "/sound";
  1493. osc24M = "/clocks/osc24M_clk";
  1494. osc32k = "/clocks/osc32k_clk";
  1495. cpu0_opp_table = "/opp_table0";
  1496. de = "/display-engine";
  1497. display_clocks = "/soc/clock@1000000";
  1498. mixer0 = "/soc/mixer@1100000";
  1499. mixer0_out = "/soc/mixer@1100000/ports/port@1";
  1500. mixer0_out_tcon0 = "/soc/mixer@1100000/ports/port@1/endpoint";
  1501. dma = "/soc/dma-controller@1c02000";
  1502. tcon0 = "/soc/lcd-controller@1c0c000";
  1503. tcon0_in = "/soc/lcd-controller@1c0c000/ports/port@0";
  1504. tcon0_in_mixer0 = "/soc/lcd-controller@1c0c000/ports/port@0/endpoint";
  1505. tcon0_out = "/soc/lcd-controller@1c0c000/ports/port@1";
  1506. tcon0_out_hdmi = "/soc/lcd-controller@1c0c000/ports/port@1/endpoint@1";
  1507. mmc0 = "/soc/mmc@1c0f000";
  1508. mmc1 = "/soc/mmc@1c10000";
  1509. rtl8189ftv = "/soc/mmc@1c10000/sdio_wifi@1";
  1510. mmc2 = "/soc/mmc@1c11000";
  1511. sid = "/soc/eeprom@1c14000";
  1512. ths_calibration = "/soc/eeprom@1c14000/thermal-sensor-calibration@34";
  1513. usb_otg = "/soc/usb@1c19000";
  1514. usbphy = "/soc/phy@1c19400";
  1515. ehci0 = "/soc/usb@1c1a000";
  1516. ohci0 = "/soc/usb@1c1a400";
  1517. ehci1 = "/soc/usb@1c1b000";
  1518. ohci1 = "/soc/usb@1c1b400";
  1519. ehci2 = "/soc/usb@1c1c000";
  1520. ohci2 = "/soc/usb@1c1c400";
  1521. ehci3 = "/soc/usb@1c1d000";
  1522. ohci3 = "/soc/usb@1c1d400";
  1523. ccu = "/soc/clock@1c20000";
  1524. pio = "/soc/pinctrl@1c20800";
  1525. csi_pins = "/soc/pinctrl@1c20800/csi-pins";
  1526. emac_rgmii_pins = "/soc/pinctrl@1c20800/emac-rgmii-pins";
  1527. i2c0_pins = "/soc/pinctrl@1c20800/i2c0-pins";
  1528. i2c1_pins = "/soc/pinctrl@1c20800/i2c1-pins";
  1529. i2c2_pins = "/soc/pinctrl@1c20800/i2c2-pins";
  1530. i2s0_pins = "/soc/pinctrl@1c20800/i2s0-pins";
  1531. i2s1_pins = "/soc/pinctrl@1c20800/i2s1-pins";
  1532. mmc0_pins = "/soc/pinctrl@1c20800/mmc0-pins";
  1533. mmc1_pins = "/soc/pinctrl@1c20800/mmc1-pins";
  1534. mmc2_8bit_pins = "/soc/pinctrl@1c20800/mmc2-8bit-pins";
  1535. spdif_tx_pin = "/soc/pinctrl@1c20800/spdif-tx-pin";
  1536. spi0_pins = "/soc/pinctrl@1c20800/spi0-pins";
  1537. spi1_pins = "/soc/pinctrl@1c20800/spi1-pins";
  1538. uart0_pa_pins = "/soc/pinctrl@1c20800/uart0-pa-pins";
  1539. uart1_pins = "/soc/pinctrl@1c20800/uart1-pins";
  1540. uart1_rts_cts_pins = "/soc/pinctrl@1c20800/uart1-rts-cts-pins";
  1541. uart2_pins = "/soc/pinctrl@1c20800/uart2-pins";
  1542. uart2_rts_cts_pins = "/soc/pinctrl@1c20800/uart2-rts-cts-pins";
  1543. uart3_pins = "/soc/pinctrl@1c20800/uart3-pins";
  1544. uart3_rts_cts_pins = "/soc/pinctrl@1c20800/uart3-rts-cts-pins";
  1545. emac = "/soc/ethernet@1c30000";
  1546. mdio = "/soc/ethernet@1c30000/mdio";
  1547. internal_mdio = "/soc/ethernet@1c30000/mdio-mux/mdio@1";
  1548. int_mii_phy = "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1";
  1549. external_mdio = "/soc/ethernet@1c30000/mdio-mux/mdio@2";
  1550. spi0 = "/soc/spi@1c68000";
  1551. spi1 = "/soc/spi@1c69000";
  1552. wdt0 = "/soc/watchdog@1c20ca0";
  1553. spdif = "/soc/spdif@1c21000";
  1554. pwm = "/soc/pwm@1c21400";
  1555. i2s0 = "/soc/i2s@1c22000";
  1556. i2s1 = "/soc/i2s@1c22400";
  1557. i2s2 = "/soc/i2s@1c22800";
  1558. codec = "/soc/codec@1c22c00";
  1559. uart0 = "/soc/serial@1c28000";
  1560. uart1 = "/soc/serial@1c28400";
  1561. uart2 = "/soc/serial@1c28800";
  1562. uart3 = "/soc/serial@1c28c00";
  1563. i2c0 = "/soc/i2c@1c2ac00";
  1564. i2c1 = "/soc/i2c@1c2b000";
  1565. i2c2 = "/soc/i2c@1c2b400";
  1566. gic = "/soc/interrupt-controller@1c81000";
  1567. csi = "/soc/camera@1cb0000";
  1568. hdmi = "/soc/hdmi@1ee0000";
  1569. hdmi_in = "/soc/hdmi@1ee0000/ports/port@0";
  1570. hdmi_in_tcon0 = "/soc/hdmi@1ee0000/ports/port@0/endpoint";
  1571. hdmi_out = "/soc/hdmi@1ee0000/ports/port@1";
  1572. hdmi_out_con = "/soc/hdmi@1ee0000/ports/port@1/endpoint";
  1573. hdmi_phy = "/soc/hdmi-phy@1ef0000";
  1574. rtc = "/soc/rtc@1f00000";
  1575. r_ccu = "/soc/clock@1f01400";
  1576. codec_analog = "/soc/codec-analog@1f015c0";
  1577. ir = "/soc/ir@1f02000";
  1578. r_i2c = "/soc/i2c@1f02400";
  1579. reg_vdd_cpux = "/soc/i2c@1f02400/regulator@65";
  1580. r_pio = "/soc/pinctrl@1f02c00";
  1581. r_ir_rx_pin = "/soc/pinctrl@1f02c00/r-ir-rx-pin";
  1582. r_i2c_pins = "/soc/pinctrl@1f02c00/r-i2c-pins";
  1583. syscon = "/soc/system-control@1c00000";
  1584. sram_c = "/soc/system-control@1c00000/sram@1d00000";
  1585. ve_sram = "/soc/system-control@1c00000/sram@1d00000/sram-section@0";
  1586. mali = "/soc/gpu@1c40000";
  1587. ths = "/soc/ths@1c25000";
  1588. cpu0 = "/cpus/cpu@0";
  1589. cpu1 = "/cpus/cpu@1";
  1590. cpu2 = "/cpus/cpu@2";
  1591. cpu3 = "/cpus/cpu@3";
  1592. cpu_warm = "/thermal-zones/cpu_thermal/trips/cpu_warm";
  1593. cpu_hot_pre = "/thermal-zones/cpu_thermal/trips/cpu_hot_pre";
  1594. cpu_hot = "/thermal-zones/cpu_thermal/trips/cpu_hot";
  1595. cpu_very_hot_pre = "/thermal-zones/cpu_thermal/trips/cpu_very_hot_pre";
  1596. cpu_very_hot = "/thermal-zones/cpu_thermal/trips/cpu_very_hot";
  1597. cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
  1598. reg_ahci_5v = "/ahci-5v";
  1599. reg_usb0_vbus = "/usb0-vbus";
  1600. reg_usb1_vbus = "/usb1-vbus";
  1601. reg_usb2_vbus = "/usb2-vbus";
  1602. reg_vcc3v0 = "/vcc3v0";
  1603. reg_vcc3v3 = "/vcc3v3";
  1604. reg_vcc5v0 = "/vcc5v0";
  1605. hdmi_con_in = "/connector/port/endpoint";
  1606. wifi_pwrseq = "/wifi_pwrseq";
  1607. };
  1608. };
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