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May 27th, 2018
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  1. //code for alu
  2. module alu(result,A,B,control);
  3. output reg [0:31] result;
  4. input [0:31] A;
  5. input [0:31]B;
  6. input [0:5]control;
  7. always @(*)
  8. begin
  9. case(control)
  10. //F0 f1 ena enb inva inc fun
  11. 6'b011000:result=A;
  12. 6'b010100:result=B;
  13. 6'b011010:result=~A;
  14. 6'b101100:result=~B;
  15. 6'b111100:result=A+B;
  16. 6'b111101:result=A+B+1;
  17. 6'b111001:result=A+1;
  18. 6'b110101:result=B+1;
  19. 6'b111111:result=B-A;
  20. 6'b110110:result=-A;
  21. 6'b001100:result=A&B;
  22. 6'b011100:result=A|B;
  23. 6'b010000:result=0;
  24. 6'b110001:result=1;
  25. 6'b110010:result=-1;
  26. default:result=0;
  27. endcase
  28. end
  29. endmodule
  30.  
  31. //code for shifter
  32. module shifter(C,sll,sr,Alu_Out,clk);
  33. output reg [0:31]C;
  34. input clk;
  35. input sll,sr;
  36. input [0:31]Alu_Out;
  37. integer i;
  38. always @(posedge clk)
  39. begin
  40. if(sll==1'b1 && sr==1'b0)
  41. begin
  42. for(i=0;i<24;i=i+1)
  43. begin
  44. C[i]<=Alu_Out[i+8];
  45. end
  46. for(i=31;i>23;i=i-1)
  47. begin
  48. C[i]<=0;
  49. end
  50. end
  51. if(sll==1'b0 && sr==1'b1)
  52. begin
  53. C[0]<=Alu_Out[0];
  54. for(i=0;i<31;i=i+1)
  55. begin
  56. C[i+1]<=Alu_Out[i];
  57. end
  58. end
  59. end
  60. endmodule
  61.  
  62. module shifter(C,sll,sr,Alu_Out,clk,A,B,control);
  63. output reg [0:31]C;
  64. input clk;
  65. input sll,sr;
  66. input [0:31] A;
  67. input [0:31]B;
  68. input [0:5]control;
  69. input [0:31]Alu_Out;
  70.  
  71. alu first_call(Alu_out,A,B,control);
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