freq_dividor

module f_d(clk_in , mod2 , mod10);
//assume that clk_in is 25MHz

reg [24:0] freq_cnt ; //register bit numbers must more than the frequency you want to divide

always@(posedge clk_in) begin
    //this is how to deal with power of 2
    mod2 <= ~mod2;
end

always@(posedge clk_in) begin
if(freq_cnt == 9) begin //mod 10-1
    freq_cnt <= 0;
    mod10 <= ~mod10;
end
else begin
    freq_cnt <= freq_cnt + 1;
end

end


endmodule