PoC for dropping priority in GIC

 arch/arm/include/asm/arch_gicv3.h   | 6 ++++++
 arch/arm64/include/asm/arch_gicv3.h | 5 +++++
 drivers/irqchip/irq-gic-v3.c        | 4 ++++
 drivers/irqchip/irq-gic.c           | 5 +++++
 include/linux/irqchip/arm-gic-v3.h  | 1 +
 include/linux/irqchip/arm-gic.h     | 2 ++
 6 files changed, 23 insertions(+)

diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 1070044..06ea637 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -34,6 +34,7 @@
 #define ICC_SRE                __ACCESS_CP15(c12, 0, c12, 5)
 #define ICC_IGRPEN1            __ACCESS_CP15(c12, 0, c12, 7)
 #define ICC_BPR1           __ACCESS_CP15(c12, 0, c12, 3)
+#define ICC_RPR                __ACCESS_CP15(c12, 0, c11, 3)

 #define ICC_HSRE           __ACCESS_CP15(c12, 4, c9, 5)

@@ -228,6 +229,11 @@ static inline void gic_write_bpr1(u32 val)
    write_sysreg(val, ICC_BPR1);
 }

+static inline u32 gic_read_rpr(void)
+{
+   return read_sysreg(ICC_RPR);
+}
+
 /*
  * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
  * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 9becba9..18ab2c5 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -119,6 +119,11 @@ static inline void gic_write_bpr1(u32 val)
    write_sysreg_s(val, SYS_ICC_BPR1_EL1);
 }

+static inline u32 gic_read_rpr(void)
+{
+   return read_sysreg_s(SYS_ICC_RPR_EL1);
+}
+
 #define gic_read_typer(c)      readq_relaxed(c)
 #define gic_write_irouter(v, c)        writeq_relaxed(v, c)
 #define gic_read_lpir(c)       readq_relaxed(c)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index d99cc07..602e5a1 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -612,6 +612,10 @@ static void gic_cpu_init(void)

    gic_cpu_config(rbase, gic_redist_wait_for_rwp);

+   /* If the running priority isn't idle drop it */
+   if (gic_read_rpr() != ICC_RPR_IDLE)
+       gic_write_eoir(32);
+
    /* Give LPIs a spin */
    if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
        its_cpu_init();
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 5e5877e..10eddcc 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -532,6 +532,7 @@ static int gic_cpu_init(struct gic_chip_data *gic)
 {
    void __iomem *dist_base = gic_data_dist_base(gic);
    void __iomem *base = gic_data_cpu_base(gic);
+   void __iomem *cpu_base = gic_data_cpu_base(gic);
    unsigned int cpu_mask, cpu = smp_processor_id();
    int i;

@@ -562,6 +563,10 @@ static int gic_cpu_init(struct gic_chip_data *gic)

    gic_cpu_config(dist_base, NULL);

+   /* If the running priority isn't idle drop it */
+   if (readl_relaxed(cpu_base + GIC_CPU_RUNNINGPRI) != GIC_CPU_IDLE_PRIORITY)
+       writel_relaxed(32, cpu_base + GIC_CPU_EOI);
+
    writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
    gic_cpu_if_up(gic);

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index c00c4c33..1fce576 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -476,6 +476,7 @@
 #define ICC_SRE_EL1_DIB            (1U << 2)
 #define ICC_SRE_EL1_DFB            (1U << 1)
 #define ICC_SRE_EL1_SRE            (1U << 0)
+#define ICC_RPR_IDLE           0xff

 /*
  * Hypervisor interface registers (SRE only)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index d3453ee..df7edf6 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -38,6 +38,8 @@
 #define GIC_CPU_CTRL_EOImodeNS_SHIFT   9
 #define GIC_CPU_CTRL_EOImodeNS     (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT)

+#define GIC_CPU_IDLE_PRIORITY      0xff
+
 #define GICC_IAR_INT_ID_MASK       0x3ff
 #define GICC_INT_SPURIOUS      1023
 #define GICC_DIS_BYPASS_MASK       0x1e0
--
2.7.4