`timescale 1ns/1ns
module Medidor_Function_Test;

reg clock, reset_n, write, read;
reg [31:0] writedata;
wire [31:0] value_export, readdata;
wire [31:0] data_out;


Medidor_Interface DUV (clock, reset_n, write, writedata, read, readdata, value_export);

always
    #10 clock = !clock;

initial
begin
    $monitor ("time = %t readdata = %d, writedata = %d, write = %d", $time, readdata, writedata, write);
    clock = 0;
    reset_n = 0;
    #10 reset_n = 1;
    write = 0;
    read = 0;
    writedata = 0;

    #100  writedata = 0;//sum
    write = 1;
    #50 write = 0;
    #100  writedata = 1;//sum
    write = 1;
    #50 write = 0;
    #100  writedata = 2;//sum
    write = 1;
    #50 write = 0;
    #100  writedata = 0;//sum
    write = 1;
    #50 write = 0;

    #1000 $stop;
end

endmodule