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  1. nand-as3525.c
  2. /*
  3. * Copyright (C) 2006 Austriamicrosystems Corporation
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <inttypes.h>
  24. #include "config.h"
  25. #include "nand-as3525v2.h"
  26. #include "system.h"
  27. //#include "nand.h"
  28.  
  29. #define CCU_IO ( (AS352X_CCU_BASE) + 0x0C)
  30.  
  31. /*
  32. * hardware specific access to control-lines
  33. */
  34. #define NAND_CTL_SETNCE 1
  35. /* Deselect the chip by setting nCE to high */
  36. #define NAND_CTL_CLRNCE 2
  37. /* Select the command latch by setting CLE to high */
  38. #define NAND_CTL_SETCLE 3
  39. /* Deselect the command latch by setting CLE to low */
  40. #define NAND_CTL_CLRCLE 4
  41. /* Select the address latch by setting ALE to high */
  42. #define NAND_CTL_SETALE 5
  43. /* Deselect the address latch by setting ALE to low */
  44. #define NAND_CTL_CLRALE 6
  45. /* Set write protection by setting WP to high. Not used! */
  46. #define NAND_CTL_SETWP 7
  47. /* Clear write protection by setting WP to low. Not used! */
  48. #define NAND_CTL_CLRWP 8
  49.  
  50. #define NAF_X8_X16_CODE 0x03 /* only for big block nand */
  51. /*
  52. * Standard NAND flash commands
  53. */
  54. #define NAND_CMD_READ0 0
  55. #define NAND_CMD_READ1 1
  56. #define NAND_CMD_PAGEPROG 0x10
  57. #define NAND_CMD_READOOB 0x50
  58. #define NAND_CMD_ERASE1 0x60
  59. #define NAND_CMD_STATUS 0x70
  60. #define NAND_CMD_STATUS_MULTI 0x71
  61. #define NAND_CMD_SEQIN 0x80
  62. #define NAND_CMD_READID 0x90
  63. #define NAND_CMD_ERASE2 0xd0
  64. #define NAND_CMD_RESET 0xff
  65.  
  66. /* Extended commands for large page devices */
  67. #define NAND_CMD_READSTART 0x30
  68. #define NAND_CMD_CACHEDPROG 0x15
  69.  
  70. /* Status bits */
  71. #define NAND_STATUS_FAIL 0x01
  72. #define NAND_STATUS_FAIL_N1 0x02
  73. #define NAND_STATUS_TRUE_READY 0x20
  74. #define NAND_STATUS_READY 0x40
  75. #define NAND_STATUS_WP 0x80
  76. /**
  77. * Power bit in NAF mode register.
  78. **/
  79. #define NAF_POWER_ON 0x0C
  80. #define NAF_POWER_OFF 0x00
  81.  
  82. /**
  83. * NAF Config register bits.
  84. **/
  85. #define NAF_X16 0x00000001
  86. #define NAF_FIFO_ENABLE 0x00000004
  87. #define NAF_DMA_ON 0x00000008
  88.  
  89. #define NAF_READ_STROBE_H 0x00000020 /* read strobe high is 4 PLCK cycles */
  90. #define NAF_READ_STROBE_L 0x00000400 /* read strobe low is 5 PLCK cycles */
  91. #define NAF_WRITE_STROBE_H 0x00003000 /* write strobe high is 4 PCLK cycles */
  92. #define NAF_WRITE_STROBE_L 0x00040000 /* write strobe high is 4 PCLK cycles */
  93.  
  94. #define NAF_STROBE_CONFIG \
  95. ( NAF_READ_STROBE_H | NAF_READ_STROBE_L | NAF_WRITE_STROBE_H | \
  96. NAF_WRITE_STROBE_L )
  97.  
  98.  
  99. /**
  100. * NAF modi
  101. **/
  102. #define NAF_MODE_CLE 1<<0
  103. #define NAF_MODE_ALE 1<<1
  104. #define NAF_MODE_NCE 1<<4
  105. #define NAF_MODE_WP 1<<7
  106.  
  107. #define NAF_MODE_DATA_READ_NO_ECC 0x14
  108. #define NAF_MODE_DATA_WRITE_ECC_RESET 0xF4
  109. #define NAF_MODE_DATA_WRITE_NO_ECC 0x94
  110. /*
  111. * chip R/B detection
  112. */
  113. static int as352x_read_status;
  114.  
  115. static int as352x_nand_ready(void)
  116. {
  117. return ( ( rreg16( NAF_STATUS ) & 0x0080 ) == 0x0080 );
  118. }
  119. static int as352x_nand_strobe(void)
  120. {
  121. return ( ( rreg16( NAF_STATUS ) & 0x0100 ) == 0x0100 );
  122. }
  123. static int as352x_fifo_isfull(void)
  124. {
  125. return ( ( rreg16( NAF_STATUS ) & 0x01000 ) );
  126. }
  127.  
  128. static int as352x_fifo_isempty(void)
  129. {
  130. return ( ( rreg16( NAF_STATUS ) & 0x0200 ) );
  131. }
  132. /**
  133. * nand_read_byte - [DEFAULT] read one byte from the chip
  134. * @mtd: MTD device structure
  135. *
  136. * Default read function for 8bit buswith
  137. */
  138. uint8_t as352x_nand_read_byte(void)
  139. {
  140. uint8_t data = 0;
  141. unsigned char ct = 255;
  142. wreg8 ( NAF_CONTROL, 0x1 ); /* generate read strobe */
  143. while (!as352x_nand_strobe() && ct > 0)
  144. {
  145. udelay(10);
  146. ct--;
  147. }
  148.  
  149. data = rreg16( NAF_DATA );
  150. if (as352x_read_status)
  151. data |= 0x80;
  152.  
  153. return data;
  154. }
  155.  
  156. /**
  157. * nand_write_byte - [DEFAULT] write one byte to the chip
  158. * @mtd: MTD device structure
  159. * @byte: pointer to data byte to write
  160. *
  161. * Default write function for 8it buswith
  162. */
  163. static void as352x_nand_write_byte(uint8_t byte)
  164. {
  165. unsigned char ct = 255;
  166. wreg16( NAF_DATA, byte );
  167. while (!as352x_nand_strobe() && ct > 0)
  168. {
  169. udelay(10);
  170. ct--;
  171. }
  172. }
  173.  
  174. void as352x_nand_wait_fifo_empty(void)
  175. {
  176. while ( ( rreg16( NAF_STATUS ) & 0x0004 ) != 0x0004 ) ;
  177. /* wait for got empty and ready */
  178. }
  179.  
  180. /**
  181. * nand_write_buf - [DEFAULT] write buffer to chip
  182. * @mtd: MTD device structure
  183. * @buf: data buffer
  184. * @len: number of bytes to write
  185. *
  186. * Default write function for 8bit buswith
  187. */
  188. static void as352x_nand_write_buf(const uint8_t *buf, int len)
  189. {
  190. int i;
  191. uint32_t *p =(uint32_t *)buf;
  192. /* struct nand_chip *this = mtd->priv;
  193. * unused, incomplete
  194. */
  195. len /=4;
  196. wreg8( NAF_CLEAR, 0x7f );
  197. wreg32( NAF_WORDS, len );
  198. for (i=0; i<len; i++)
  199. {
  200. while (as352x_fifo_isfull());
  201. wreg32( NAF_FIFODATA, p[i] );
  202. }
  203. as352x_nand_wait_fifo_empty();
  204. }
  205.  
  206. /**
  207. * nand_read_buf - [DEFAULT] read chip data into buffer
  208. * @mtd: MTD device structure
  209. * @buf: buffer to store date
  210. * @len: number of bytes to read
  211. *
  212. * Default read function for 8bit buswith
  213. */
  214.  
  215. void as352x_nand_read_buf(uint8_t *buf, int len)
  216. {
  217. int i;
  218. /* struct nand_chip *this = mtd->priv;
  219. * unused, incomplete
  220. */
  221. uint32_t *p =(uint32_t *)buf;
  222. len /=4;
  223. wreg8( NAF_CLEAR, 0x7f );
  224. wreg32( NAF_WORDS, len );
  225. for (i=0; i<len; i++)
  226. {
  227. while (as352x_fifo_isempty());
  228. p[i] = rreg32( NAF_FIFODATA );
  229. }
  230. as352x_nand_wait_fifo_empty( );
  231. }
  232. /**
  233. * nand_verify_buf - [DEFAULT] Verify chip data against buffer
  234. * @mtd: MTD device structure
  235. * @buf: buffer containing the data to compare
  236. * @len: number of bytes to compare
  237. *
  238. * Default verify function for 8bit buswith
  239. */
  240. static int nand_verify_buf(const uint8_t *buf, int len)
  241. {
  242. int i;
  243.  
  244. /* struct nand_chip *this = mtd->priv;
  245. * unused, incomplete
  246. */
  247.  
  248. for (i=0; i<len; i++)
  249. if (buf[i] != as352x_nand_read_byte())
  250. return -14; /*EFAULT; - Bad address */
  251.  
  252. return 0;
  253. }
  254.  
  255. static void as352x_nand_hwcontrol(int cmd)
  256. {
  257. /* struct nand_chip *this = mtd->priv;
  258. * ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  259. * unused, incomplete
  260. */
  261. switch (cmd)
  262. {
  263. case NAND_CTL_SETCLE:
  264. {
  265. set_reg_bits16 ( NAF_MODE, NAF_MODE_CLE);
  266. }
  267. break;
  268. case NAND_CTL_CLRCLE:
  269. clr_reg_bits16( NAF_MODE, NAF_MODE_CLE);
  270. break;
  271. case NAND_CTL_SETALE:
  272. {
  273. set_reg_bits16 ( NAF_MODE, NAF_MODE_ALE);
  274. }
  275. break;
  276. case NAND_CTL_CLRALE:
  277. clr_reg_bits16( NAF_MODE, NAF_MODE_ALE);
  278. break;
  279. case NAND_CTL_SETNCE:
  280. set_reg_bits16 ( NAF_MODE, NAF_MODE_NCE);
  281. break;
  282. case NAND_CTL_CLRNCE:
  283. clr_reg_bits16( NAF_MODE, NAF_MODE_NCE);
  284. break;
  285. case NAND_CTL_SETWP:
  286. set_reg_bits16 ( NAF_MODE, NAF_MODE_WP);
  287. break;
  288. case NAND_CTL_CLRWP:
  289. clr_reg_bits16( NAF_MODE, NAF_MODE_WP);
  290. break;
  291. }
  292. }
  293.  
  294. void cmd_read_test(void)
  295. {
  296. int column = 1;
  297. int page_addr = 1;
  298. wreg8( NAF_MASK, 0xFF );
  299. wreg8( NAF_CLEAR, 0x7f );
  300. wreg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC);
  301.  
  302. as352x_nand_hwcontrol(NAND_CTL_CLRWP);
  303.  
  304. /* Begin command latch cycle */
  305. as352x_nand_hwcontrol(NAND_CTL_SETCLE);
  306. /* Write out the command to the device. */
  307. as352x_nand_write_byte(NAND_CMD_READ0);
  308. /* End command latch cycle */
  309. as352x_nand_hwcontrol(NAND_CTL_CLRCLE);
  310.  
  311. if (column != -1 || page_addr != -1)
  312. {
  313. as352x_nand_hwcontrol(NAND_CTL_SETALE);
  314.  
  315. /* Serially input address */
  316. if (column != -1)
  317. {
  318. /* Adjust columns for 16 bit buswidth */
  319. /* if (this->options & NAND_BUSWIDTH_16)
  320. column >>= 1;*/
  321. as352x_nand_write_byte(column & 0xff);
  322. as352x_nand_write_byte(column >> 8);
  323. }
  324.  
  325. if (page_addr != -1)
  326. {
  327. as352x_nand_write_byte((unsigned char) (page_addr & 0xff));
  328. as352x_nand_write_byte((unsigned char) ((page_addr >> 8) & 0xff));
  329. /* One more address cycle for devices > 128MiB */
  330. //if (this->chipsize > (128 << 20))
  331. as352x_nand_write_byte((unsigned char) ((page_addr >> 16) & 0xff));
  332. }
  333. /* Latch in address */
  334. as352x_nand_hwcontrol(NAND_CTL_CLRALE);
  335. }
  336. //case NAND_CMD_READ0:
  337. /* Begin command latch cycle */
  338. as352x_nand_hwcontrol(NAND_CTL_SETCLE);
  339. /* Write out the start read command */
  340. as352x_nand_write_byte(NAND_CMD_READSTART);
  341. /* End command latch cycle */
  342. as352x_nand_hwcontrol(NAND_CTL_CLRCLE);
  343. /* Fall through into ready check */
  344.  
  345. /* This applies to read commands */
  346. /*
  347. * If we don't have access to the busy pin, we apply the
  348. given
  349. * command delay
  350. */
  351. if (!as352x_nand_ready())
  352. {
  353. udelay (30);
  354. return;
  355. }
  356. }
  357.  
  358.  
  359. /**
  360. * nand_command_lp - [DEFAULT] Send command to NAND large page device
  361. * @mtd: MTD device structure
  362. * @command: the command to be sent
  363. * @column: the column address for this command, -1 if none
  364. * @page_addr: the page address for this command, -1 if none
  365. *
  366. * Send command to NAND device. This is the version for the new large
  367. page devices
  368. * We dont have the seperate regions as we have in the small page
  369. devices.
  370. * We must emulate NAND_CMD_READOOB to keep the code compatible.
  371. *
  372. */
  373. #if 0
  374. static void as352x_nand_command_lp (struct mtd_info *mtd, unsigned
  375. command, int column, int page_addr)
  376. {
  377. register struct nand_chip *this = mtd->priv;
  378.  
  379. /* Emulate NAND_CMD_READOOB */
  380. if (command == NAND_CMD_READOOB) {
  381. column += mtd->oobblock;
  382. command = NAND_CMD_READ0;
  383. }
  384.  
  385. as352x_read_status =0;
  386. switch (command)
  387. {
  388. case NAND_CMD_SEQIN:
  389. case NAND_CMD_ERASE1:
  390. case NAND_CMD_ERASE2:
  391. {
  392. wreg8( NAF_MASK, 0xFF );
  393. wreg8( NAF_CLEAR, 0x7f );
  394. }
  395. case NAND_CMD_CACHEDPROG:
  396. case NAND_CMD_PAGEPROG:
  397. {
  398. this->hwcontrol(mtd, NAND_CTL_SETWP);
  399. }
  400. break;
  401. case NAND_CMD_READ0:
  402. wreg8( NAF_MASK, 0xFF );
  403. wreg8( NAF_CLEAR, 0x7f );
  404. wreg8( NAF_MODE,NAF_MODE_DATA_READ_NO_ECC);
  405. default:
  406. this->hwcontrol(mtd, NAND_CTL_CLRWP);
  407. }
  408. /* Begin command latch cycle */
  409. this->hwcontrol(mtd, NAND_CTL_SETCLE);
  410. /* Write out the command to the device. */
  411. this->write_byte(mtd, command);
  412. /* End command latch cycle */
  413. this->hwcontrol(mtd, NAND_CTL_CLRCLE);
  414.  
  415. if (column != -1 || page_addr != -1) {
  416. this->hwcontrol(mtd, NAND_CTL_SETALE);
  417.  
  418. /* Serially input address */
  419. if (column != -1) {
  420. /* Adjust columns for 16 bit buswidth */
  421. if (this->options & NAND_BUSWIDTH_16)
  422. column >>= 1;
  423. this->write_byte(mtd, column & 0xff);
  424. this->write_byte(mtd, column >> 8);
  425. }
  426. if (page_addr != -1) {
  427. this->write_byte(mtd, (unsigned char) (page_addr
  428. & 0xff));
  429. this->write_byte(mtd, (unsigned char)
  430. ((page_addr >> 8) & 0xff));
  431. /* One more address cycle for devices > 128MiB
  432. */
  433. if (this->chipsize > (128 << 20))
  434. this->write_byte(mtd, (unsigned char)
  435. ((page_addr >> 16) & 0xff));
  436. }
  437. /* Latch in address */
  438. this->hwcontrol(mtd, NAND_CTL_CLRALE);
  439. }
  440.  
  441. /*
  442. * program and erase have their own busy handlers
  443. * status and sequential in needs no delay
  444. */
  445. switch (command) {
  446. case NAND_CMD_SEQIN:
  447. {
  448. wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_ECC_RESET );
  449. break;
  450. }
  451. case NAND_CMD_ERASE1:
  452. case NAND_CMD_ERASE2:
  453. break;
  454. case NAND_CMD_STATUS:
  455. as352x_read_status =1;
  456. break;
  457. case NAND_CMD_CACHEDPROG:
  458.  
  459. case NAND_CMD_PAGEPROG:
  460. wreg8( NAF_MODE, NAF_MODE_DATA_WRITE_NO_ECC );
  461. break;
  462.  
  463.  
  464. case NAND_CMD_RESET:
  465. if (this->dev_ready)
  466. break;
  467. udelay(this->chip_delay);
  468. this->hwcontrol(mtd, NAND_CTL_SETCLE);
  469. this->write_byte(mtd, NAND_CMD_STATUS);
  470. this->hwcontrol(mtd, NAND_CTL_CLRCLE);
  471. while ( !(this->read_byte(mtd) & 0x40));
  472. return;
  473.  
  474. case NAND_CMD_READ0:
  475. /* Begin command latch cycle */
  476. this->hwcontrol(mtd, NAND_CTL_SETCLE);
  477. /* Write out the start read command */
  478. this->write_byte(mtd, NAND_CMD_READSTART);
  479. /* End command latch cycle */
  480. this->hwcontrol(mtd, NAND_CTL_CLRCLE);
  481. /* Fall through into ready check */
  482.  
  483. /* This applies to read commands */
  484. default:
  485. /*
  486. * If we don't have access to the busy pin, we apply the
  487. given
  488. * command delay
  489. */
  490. if (!this->dev_ready) {
  491. udelay (this->chip_delay);
  492. return;
  493. }
  494. }
  495.  
  496. /* Apply this short delay always to ensure that we do wait tWB
  497. in
  498. * any case on any machine. */
  499. ndelay (1000);
  500. /* wait until command is processed */
  501. while (!this->dev_ready(mtd));
  502. }
  503. #endif
  504.  
  505. void board_nand_init(void)
  506. {
  507. // clear all NAF chip select bits
  508. clr_reg_bits32( CCU_IO , ( CCU_IO_NAF_CE_LINE_0 | CCU_IO_NAF_CE_LINE_1
  509. | CCU_IO_NAF_CE_LINE_2 | CCU_IO_NAF_CE_LINE_3
  510. ) );
  511. set_reg_bits32( CCU_IO , CCU_IO_NAF_CE_LINE_0 );
  512.  
  513. /* configure NAF */
  514. wreg8( NAF_MODE, NAF_POWER_ON ); /* turn power on */
  515. wreg8( NAF_MASK, 0xFF );
  516. wreg8( NAF_CLEAR, 0x7f ); /* clear any pending error indication */
  517.  
  518. /* configure fifo on but dma still off */
  519. wreg32( NAF_CONFIG, NAF_STROBE_CONFIG | NAF_FIFO_ENABLE);
  520.  
  521. /* 2. change into read mode */
  522. wreg8 ( NAF_MODE, NAF_MODE_DATA_READ_NO_ECC );
  523.  
  524. // nand->options = NAND_SAMSUNG_LP_OPTIONS;
  525. // nand->eccmode = NAND_ECC_SOFT;
  526. // nand->hwcontrol = as352x_nand_hwcontrol;
  527. // nand->dev_ready = as352x_nand_ready;
  528. // nand->chip_delay = 18;
  529. // nand->read_byte = as352x_nand_read_byte;
  530. // nand->write_byte = as352x_nand_write_byte;
  531. // nand->read_buf = as352x_nand_read_buf;
  532. // nand->write_buf = as352x_nand_write_buf;
  533. // nand->cmdfunc = as352x_nand_command_lp;
  534. }
  535.  
  536.  
  537.  
  538.  
  539. nand-as2535.h
  540. /*
  541. * (C) Copyright 2006
  542. * Copyright (C) 2006 Austriamicrosystems, by thomas.luo
  543. *
  544. * This program is free software; you can redistribute it and/or
  545. * modify it under the terms of the GNU General Public License as
  546. * published by the Free Software Foundation; either version 2 of
  547. * the License, or (at your option) any later version.
  548. *
  549. * This program is distributed in the hope that it will be useful,
  550. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  551. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  552. * GNU General Public License for more details.
  553. *
  554. * You should have received a copy of the GNU General Public License
  555. * along with this program; if not, write to the Free Software
  556. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  557. * MA 02111-1307 USA
  558. */
  559. #ifndef __NAND_AS352X_H__
  560. #define __NAND_AS352X_H__
  561.  
  562. /* AS352X only supports 512 Byte HW ECC */
  563. #define AS352X_ECCSIZE 512
  564. #define AS352X_ECCBYTES 3
  565.  
  566. #include <inttypes.h>
  567.  
  568. /* AS352X device base addresses */
  569.  
  570.  
  571. /*
  572. ------------------------------------------------------------------------
  573. * AS352X Registers
  574. *
  575. ------------------------------------------------------------------------
  576. *
  577. */
  578.  
  579. /* APB */
  580. #define AS352X_NAND_FLASH_BASE 0xC8000000
  581. #define AS352X_SD_MCI_BASE 0xC8020000
  582.  
  583. #define AS352X_CCU_BASE 0xC8100000
  584. //#define CCU_IO ( (AS352X_CCU_BASE) + 0x0C)
  585. /**
  586. * Reset Control Lines in CCU_SRC register
  587. **/
  588. #define CCU_SRC_NAF_EN ( 1 << 15 )
  589. #define CCU_SRC_SDMCI_EN ( 1 << 14 )
  590.  
  591. /**
  592. * Chip select lines for NAF. Use these constants to select/deselct the
  593. CE lines
  594. * for NAND flashes in Register CCU_IO.
  595. **/
  596. #define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 )
  597. #define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 )
  598. #define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 )
  599. #define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 )
  600.  
  601. /**
  602. * Chip select lines for NAF. Use these constants to select/deselct the
  603. CE lines
  604. * for NAND flashes in Register CCU_IO.
  605. **/
  606. #define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 )
  607. #define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 )
  608. #define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 )
  609. #define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 )
  610.  
  611.  
  612. /* --- are disabled after reset --- */
  613. #define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) /* mmc + sd */
  614. #define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) /* naf */
  615.  
  616.  
  617. /* ----------------------- defines
  618. ---------------------------------------- */
  619.  
  620. #define NAF_CONFIG ( (AS352X_NAND_FLASH_BASE) + 0x00 )
  621. #define NAF_CONTROL ( (AS352X_NAND_FLASH_BASE) + 0x04 )
  622. #define NAF_ECC ( (AS352X_NAND_FLASH_BASE) + 0x08 )
  623. #define NAF_DATA ( (AS352X_NAND_FLASH_BASE) + 0x0C )
  624. #define NAF_MODE ( (AS352X_NAND_FLASH_BASE) + 0x10 )
  625. #define NAF_STATUS ( (AS352X_NAND_FLASH_BASE) + 0x14 )
  626. #define NAF_MASK ( (AS352X_NAND_FLASH_BASE) + 0x18 )
  627. #define NAF_FIFODATA ( (AS352X_NAND_FLASH_BASE) + 0x1C )
  628. #define NAF_WORDS ( (AS352X_NAND_FLASH_BASE) + 0x20 )
  629. #define NAF_CLEAR ( (AS352X_NAND_FLASH_BASE) + 0x24 )
  630. #define NAF_TEST ( (AS352X_NAND_FLASH_BASE) + 0x28 )
  631.  
  632.  
  633.  
  634. #define set_reg_bits32( registerAddress, value ) \
  635. ( *( (volatile uint32_t *)(registerAddress) ) |= ( (uint32_t)(value) ) )
  636.  
  637.  
  638. #define clr_reg_bits32( registerAddress, value ) \
  639. ( *( (volatile uint32_t *)(registerAddress) ) &= ( ~( (uint32_t)(value) ) ) )
  640.  
  641. #define rreg32( registerAddress ) \
  642. ( *( ( const volatile uint32_t * )( registerAddress ) ) )
  643.  
  644. #define wreg32( registerAddress, value ) \
  645. ( *( (volatile uint32_t *)(registerAddress) ) = ( (uint32_t)(value) ) )
  646.  
  647.  
  648.  
  649. #define rreg16( registerAddress ) \
  650. ( *( ( const volatile uint16_t * )( registerAddress ) ) )
  651.  
  652. #define wreg16( registerAddress, value ) \
  653. ( *( (volatile uint16_t *)(registerAddress) ) = ( (uint16_t)(value) ) )
  654.  
  655. #define set_reg_bits16( registerAddress, value ) \
  656. ( *( (volatile uint16_t *)(registerAddress) ) |= ( (uint16_t)(value) ) )
  657.  
  658. #define clr_reg_bits16( registerAddress, value ) \
  659. ( *( (volatile uint16_t *)(registerAddress) ) &= ( ~( (uint16_t)(value) ) ) )
  660.  
  661.  
  662. #define rreg8( registerAddress ) \
  663. ( *( ( const volatile uint8_t * )( registerAddress ) ) )
  664.  
  665. #define wreg8( registerAddress, value ) \
  666. ( *( (volatile uint8_t *)(registerAddress) ) = ( (uint8_t)(value) ) )
  667.  
  668. #define set_reg_bits8( registerAddress, value ) \
  669. ( *( (volatile uint8_t *)(registerAddress) ) |= ( (uint8_t)(value) ) )
  670.  
  671. #define clr_reg_bits8( registerAddress, value ) \
  672. ( *( (volatile uint8_t *)(registerAddress) ) &= ( ~( (uint8_t)(value) ) ) )
  673. /* Wait until rINTPND is changed for the case that the ISR is very
  674. short. */
  675.  
  676.  
  677.  
  678. void board_nand_init(void);
  679. uint8_t as352x_nand_read_byte(void);
  680. void as352x_nand_read_buf(uint8_t *buf, int len);
  681. void cmd_read_test(void);
  682.  
  683. #endif /*__NAND_AS3525_H__*/
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