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- `timescale 1ns / 1ps
- module Mux_structural(
- input s0,
- input s1,
- input i0,
- input i1,
- input i2,
- input i3,
- output reg d
- );
- always @(s0, s1, i0, i1, i2, i3)
- begin
- d=1'b0;
- case ({s1,s0,i3,i2,i1,i0})
- 2'b00 : d = i0;
- 2'b01 : d = i1;
- 2'b10 : d = i2;
- 2'b11 : d = i3;
- default: begin
- d=1'b0;
- end
- endcase
- end
- endmodule
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