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Benny1994

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Sep 20th, 2023
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  1. `timescale 1ps/1ps
  2.  `default_nettype none
  3. module clockdevider_tb(output wire o_led);
  4.     reg clk,rst;
  5.     wire [7:0] counterout;
  6.  
  7.     clockdivider UUT (.rst(rst),
  8.                       .clk(clk),
  9.                       //.outputled(outputled),
  10.                       .counterout(counterout));
  11. initial begin
  12.         $dumpfile("clockdevider_tb.vcd");
  13.         $dumpvars(0,clockdevider_tb);
  14.         //repeat(100)
  15.         rst= 1;
  16.         rst=0;
  17.      
  18.          clk=0;
  19.         #20;
  20.         clk = 1;
  21.         #20;
  22.        
  23.  
  24. end
  25.     /*always @(posedge clk,posedge rst)
  26.     begin
  27.        
  28.         clk=0;
  29.         #20;
  30.         clk = 1;
  31.         #20;
  32.    
  33.     end
  34.     initial begin
  35.         $dumpfile("clockdevider_tb.vcd");
  36.         $dumpvars(0,clockdevider_tb);
  37.     end */
  38. endmodule
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