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  1. #include "nrf_drv_spi.h"
  2. #include "app_util_platform.h"
  3. #include "nrf_gpio.h"
  4. #include "nrf_delay.h"
  5. #include "boards.h"
  6. #include "app_error.h"
  7. #include <string.h>
  8. #include "nrf_log.h"
  9. #include "nrf_log_ctrl.h"
  10. #include "nrf_log_default_backends.h"
  11.  
  12. #define SPI_INSTANCE 0 /**< SPI instance index. */
  13. static const nrf_drv_spi_t spi = NRF_DRV_SPI_INSTANCE(SPI_INSTANCE); /**< SPI instance. */
  14. static volatile bool spi_xfer_done; /**< Flag used to indicate that SPI instance completed the transfer. */
  15.  
  16. uint8_t m_rx_buf[2]; // Receiving buffer; cleared and read upon each command
  17.  
  18.  
  19. /**
  20. * @brief SPI user event handler.
  21. * @param event
  22. */
  23. void spi_event_handler(nrf_drv_spi_evt_t const *p_event, void *p_context){
  24. spi_xfer_done = true;
  25. //NRF_LOG_INFO("Transfer completed."); //Our RX_BUF is not loaded until after __WFE();
  26. }
  27.  
  28. uint8_t intanRead(uint8_t addr )
  29. {
  30. //reads register addr
  31. //result is returned in 2 commands
  32. //use addr = 99 to send dummy command (i.e. tx_buf = {0, 0})
  33. memset(m_rx_buf, 0, 2); //Clear RX BUF
  34. spi_xfer_done = false; //Clear xfer flag
  35. uint8_t m_tx_buf[2]; //Building xfer command
  36.  
  37. m_tx_buf[0] =((0xc0) | addr)*(addr!=99); //Use addr == 99 for dummy command (i.e. tx_buf = {0, 0})
  38. m_tx_buf[1] = 0;
  39. APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi, m_tx_buf, 2, m_rx_buf, 2)); //Execute xfer command
  40.  
  41. while (!spi_xfer_done)
  42. {
  43. __WFE(); //Our RX_BUF is not loaded until after __WFE();
  44. }
  45.  
  46. //NRF_LOG_INFO("m_tx_buf:");
  47. //NRF_LOG_HEXDUMP_INFO(m_tx_buf,2); //debug tx buf
  48. //NRF_LOG_INFO("m_rx_buf:");
  49. //NRF_LOG_HEXDUMP_INFO(m_rx_buf,2); //debug rx buf
  50.  
  51. //NRF_LOG_FLUSH();
  52. //nrf_delay_ms(20);
  53.  
  54. return m_rx_buf[1]; //Load our receiving buffer to result
  55. }
  56.  
  57. uint8_t intanWrite(uint8_t addr, uint8_t data)
  58. {
  59. //writes data to register addr
  60. //result is echoed in 2 commands
  61. //returns lower byte, depends on command sent 2 CS pulses ago
  62. memset(m_rx_buf, 0, 2); //Clear RX BUF
  63. spi_xfer_done = false; //Clear xfer flag
  64. uint8_t m_tx_buf[2]; //Building xfer command
  65.  
  66. m_tx_buf[0] =((0x80) | addr);
  67. m_tx_buf[1] = data;
  68. APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi, m_tx_buf, 2, m_rx_buf, 2)); //Execute xfer command
  69.  
  70. while (!spi_xfer_done)
  71. {
  72. __WFE(); //Our RX_BUF is not loaded until after __WFE();
  73. }
  74.  
  75. //NRF_LOG_INFO("m_tx_buf:");
  76. //NRF_LOG_HEXDUMP_INFO(m_tx_buf,2); //debug tx buf
  77. //NRF_LOG_INFO("m_rx_buf:");
  78. //NRF_LOG_HEXDUMP_INFO(m_rx_buf,2); //debug rx buf
  79.  
  80. //NRF_LOG_FLUSH();
  81. //nrf_delay_ms(20);
  82.  
  83. return m_rx_buf[1]; //Load our receiving buffer to result
  84. }
  85.  
  86.  
  87. void intanSetupRegisters()
  88. {
  89. //uint8_t echoResult[21]; //18 registers, 1 duplicate, delay 2
  90. uint8_t i; //index/addr
  91. uint8_t maxAddr = 17; //Highest address to write to
  92.  
  93. uint8_t fastSettle = 0xFE; //D[5] must be set 1, then set again to 0
  94. uint8_t data[] = {
  95. //Register 0: ADC config and amplifier fast settle
  96. //D[5] must be set 1, then set again to 0
  97. //D[4] must wait 100 mu s after setting for valid ADC
  98. 0xDE,
  99. //Register 1: Supply sensor (off) and ADC buffer bias current ( = 32)
  100. 0x20,
  101. //Register 2: MUX Bias current (= 40)
  102. 0x28,
  103. //Register 3: MUX load, temp sensor, aux dig output (ALL zero)
  104. 0x00,
  105. //Register 4: ADC output format and DSP offset removal (ALL zero)
  106. 0x00,
  107. //Register 5: Impedance check control (zero)
  108. 0x00,
  109. //Register 6: Impedance check DAC (Zero)
  110. 0x00,
  111. //Register 7: Impedance check amp select (zero)
  112. 0x00,
  113. //Registers 8 - 13: amplifier bandidth select
  114. //00001000
  115. //00000000
  116. //00000100
  117. //00000000
  118. //00010000
  119. //01111100
  120. 0x08, 0x00, 0x04, 0x00, 0x10, 0x7C,
  121. //Register 14 - 17: Amplifier individual power
  122. //11111111
  123. //11111111
  124. //11111111
  125. //11111111
  126. 0xFF, 0xFF, 0xFF, 0xFF
  127. };
  128.  
  129. /**echoResult[0] = **/intanWrite(0, fastSettle);
  130. for(i=0; i<= maxAddr; i++){
  131. /*echoResult[i+1] =*/ intanWrite(i, data[i]);
  132. }
  133. // echoResult[19] = intanRead(99);
  134. // echoResult[20] = intanRead(99);
  135. //
  136. //NRF_LOG_HEXDUMP_INFO(echoResult,sizeof(echoResult));
  137. }
  138.  
  139.  
  140. void intanCalibrate()
  141. {
  142. //reads register addr
  143. //result is returned in 2 commands
  144. //use addr = 99 to send dummy command (i.e. tx_buf = {0, 0})
  145. memset(m_rx_buf, 0, 2); //Clear RX BUF
  146. spi_xfer_done = false; //Clear xfer flag
  147. uint8_t m_tx_buf[2]; //Building xfer command
  148.  
  149. m_tx_buf[0] = 0x55; //Calbrate command 0b01010101 0b00000000
  150. m_tx_buf[1] = 0;
  151.  
  152. APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi, m_tx_buf, 2, m_rx_buf, 2)); //Execute xfer command
  153.  
  154. while (!spi_xfer_done)
  155. {
  156. __WFE(); //Our RX_BUF is not loaded until after __WFE();
  157. }
  158.  
  159. //NRF_LOG_INFO("m_tx_buf:");
  160. //NRF_LOG_HEXDUMP_INFO(m_tx_buf,2); //debug tx buf
  161. //NRF_LOG_INFO("m_rx_buf:");
  162. //NRF_LOG_HEXDUMP_INFO(m_rx_buf,2); //debug rx buf
  163.  
  164. //NRF_LOG_FLUSH();
  165. //nrf_delay_ms(20);
  166.  
  167. uint8_t i;
  168. for (i=0;i<9;i++){
  169. intanRead(99); //send 9 dummy commands
  170. }
  171. }
  172.  
  173. void intanInit()
  174. {
  175. intanSetupRegisters();
  176. intanCalibrate();
  177. }
  178.  
  179.  
  180. uint16_t intanConvert(uint8_t chan)
  181. {
  182. //converts info at channel "chan" from ADC
  183. //result is returned in 2 commands
  184. //returns 16 bit unsigned integer (check 2s complement settings for format)
  185. //can use chan = 63 for successive channels
  186. memset(m_rx_buf, 0, 2); //Clear RX BUF
  187. spi_xfer_done = false; //Clear xfer flag
  188. uint8_t m_tx_buf[2]; //Building xfer command
  189.  
  190. m_tx_buf[0] =((0x00) | chan) * (chan != 99); //Use addr == 99 for dummy command (i.e. tx_buf = {0, 0})
  191. m_tx_buf[1] = 0;
  192. APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi, m_tx_buf, 2, m_rx_buf, 2)); //Execute xfer command
  193.  
  194. while (!spi_xfer_done)
  195. {
  196. __WFE(); //Our RX_BUF is not loaded until after __WFE();
  197. }
  198.  
  199. //NRF_LOG_INFO("m_tx_buf:");
  200. //NRF_LOG_HEXDUMP_INFO(m_tx_buf,2); //debug tx buf
  201. //NRF_LOG_INFO("m_rx_buf:");
  202. //NRF_LOG_HEXDUMP_INFO(m_rx_buf,2); //debug rx buf
  203.  
  204. //NRF_LOG_FLUSH();
  205. //nrf_delay_ms(20);
  206.  
  207. return (m_rx_buf[0] << 8) | m_rx_buf[1]; //Load our receiving buffer to result
  208. }
  209.  
  210.  
  211. int main(void){
  212. bsp_board_init(BSP_INIT_LEDS);
  213.  
  214. APP_ERROR_CHECK(NRF_LOG_INIT(NULL));
  215. NRF_LOG_DEFAULT_BACKENDS_INIT();
  216.  
  217. nrf_drv_spi_config_t spi_config = NRF_DRV_SPI_DEFAULT_CONFIG;
  218. spi_config.ss_pin = SPI_SS_PIN;
  219. spi_config.miso_pin = SPI_MISO_PIN;
  220. spi_config.mosi_pin = SPI_MOSI_PIN;
  221. spi_config.sck_pin = SPI_SCK_PIN;
  222. spi_config.frequency = NRF_DRV_SPI_FREQ_125K; //Low frequency for clean OSC signals
  223. APP_ERROR_CHECK(nrf_drv_spi_init(&spi, &spi_config, spi_event_handler, NULL));
  224.  
  225. NRF_LOG_INFO("SPI example started.");
  226.  
  227. intanInit();
  228.  
  229. // uint8_t ourResult[4]; //For reading INTAN, we need 7 commands (5 read + 2 dummy)
  230. uint16_t ourData[18]; //16 channels + 2 delay
  231. uint8_t initialChan = 8; //initial channel to sample
  232. int j; //index
  233. uint8_t chan; //channel to sample
  234. // uint16_t temp;
  235.  
  236. while (1)
  237. {
  238. // ourResult[0] = intanRead(40); //read registers 40-44, send 2 dummy commands, store in ourResult
  239. // ourResult[1] = intanRead(41);
  240. // ourResult[2] = intanRead(42);
  241. // ourResult[3] = intanRead(43);
  242. // ourResult[4] = intanRead(44);
  243. // ourResult[5] = intanRead(99);
  244. // ourResult[6] = intanRead(99);
  245.  
  246. // //write register 1: ADC buffer bias = 32
  247. // ourResult[0] = intanWrite(1, 32);
  248. // //write register 2: MUX bias = 40
  249. // ourResult[1] = intanWrite(2, 40);
  250. // //send dummy command 1
  251. // ourResult[2] = intanRead(99);
  252. // //send dummy command 2
  253. // ourResult[3] = intanRead(99);
  254.  
  255. memset(ourData, 0, sizeof(ourData)/2);
  256.  
  257. for (j=0; j<sizeof(ourData)/2;j++)
  258. {
  259. if (j==0){ //if we are on first sample we point to first channel
  260. chan = initialChan;
  261. } else {
  262. chan = 63;
  263. }
  264.  
  265. if ((j==sizeof(ourData)/2 - 1)|(j==sizeof(ourData)/2 - 2)) {
  266. //if we are on last 2 we will send dummy command
  267. //temp = intanRead(99);
  268. //ourData[j] = temp;
  269. ourData[j] = intanConvert(99);
  270. } else {
  271. ourData[j] = intanConvert(chan);
  272. }
  273.  
  274. }
  275.  
  276.  
  277. bsp_board_led_invert(BSP_BOARD_LED_0);
  278.  
  279. // NRF_LOG_INFO("ourResult:");
  280. // NRF_LOG_HEXDUMP_INFO(ourResult,sizeof(ourResult)); //Debug our array
  281. //NRF_LOG_INFO("ourData:");
  282. //NRF_LOG_HEXDUMP_INFO(ourData,sizeof(ourData)/2);
  283. //NRF_LOG_INFO("Decimal:");
  284. // for (j=0; j<sizeof(ourData)/2;j++)
  285. // {
  286. // NRF_LOG_INFO("%d: %d",j+initialChan, ourData[j]);
  287. // }
  288. NRF_LOG_INFO("%d: %d",10+initialChan, ourData[10])
  289. //NRF_LOG_INFO("//////////////////////////");
  290. NRF_LOG_FLUSH();
  291. }
  292. }
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