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-- Company:
-- Engineer:
--
-- Create Date: 04/16/2018 11:29:28 PM
-- Design Name:
-- Module Name: mpg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mpg is
    Port (clk:in std_logic;
        input:in std_logic;
        enable:out std_logic);
end mpg;

architecture Behavioral of mpg is

   signal cnt:std_logic_vector(31 downto 0):=x"00000000";
   signal Q1: std_logic;
   signal Q2: std_logic;
   signal Q3: std_logic;

begin
    enable <= Q2 and (not Q3);

    process(clk)
    begin
        if (rising_edge(clk)) then
            cnt<=cnt+1;
        end if;
    end process;

    process(clk)
        begin
            if (rising_edge(clk)) then
                if (cnt(15 downto 0)= "1111111111111111") then
                    Q1<=input;
                end if;
            end if;
        end process;

    process(clk)
        begin
             if (rising_edge(clk)) then
                  Q2<=Q1;
                  Q3<=Q2;
              end if;
    end process;


end Behavioral;