library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity klk_tb is
end entity;

architecture test_tb of klk_tb is

	signal	sLOAD : std_logic;
	signal	sD    : std_logic_vector(7 downto 0);
	signal	sCLK  : std_logic;
	signal	snRST : std_logic;
	signal	sONES : std_logic_vector(7 downto 0);
	signal	sEVEN : std_logic_vector(2 downto 0);
	signal	sODD  : std_logic_vector(2 downto 0);

component klk is
	port (
		iLOAD : in std_logic;
		iD    : in std_logic_vector(7 downto 0);
		iCLK  : in std_logic;
		inRST : in std_logic;
		oONES : out std_logic_vector(7 downto 0);
		oEVEN : out std_logic_vector(2 downto 0);
		oODD  : out std_logic_vector(2 downto 0)
	);
end component;

constant iCLK_period : time := 10 ns;

begin

	uut : klk port map (
		iLOAD => sLOAD,
		iD    => sD,
		iCLK  => sCLK,
		inRST => snRST,
		oONES => sONES,
		oEVEN => sEVEN,
		oODD  => sODD
	);

	iCLK_process : process
		begin
			sCLK <= '0';
			wait for iCLK_period/2;
			sCLK <= '1';
			wait for iCLK_period/2;
		end process;

	stimulus : process
		begin

			snRST <= '0';
			wait for 5.25*iCLK_period;

			snRST <='1';
			sLOAD <='1';

			sD <= "11100001";
			wait for iCLK_period;
			sLOAD <='0';
			wait for 9*iCLK_period;

			sLOAD <='1';
			sD <= "11100001";
			wait for iCLK_period;
			sLOAD <='0';
			wait for 9*iCLK_period;

			sLOAD <='1';
			sD <= "00110001";
			wait for iCLK_period;
			sLOAD <='0';
			wait for 9*iCLK_period;

			sLOAD <='1';
			sD <= "01100000";
			wait for iCLK_period;
			sLOAD <='0';
			wait for 9*iCLK_period;

			sLOAD <='1';
			sD <= "11000000";
			wait for iCLK_period;
			sLOAD <='0';
			wait for 9*iCLK_period;

		end process;
end architecture;