commit cdf7f815cb2ccf445f6f55b52fa339e271fae051
Author: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date:   Tue Jul 27 06:22:38 2021 +0000

    isatables: addg6s instruction

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 43e1d1a..ef37147 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -9,6 +9,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1011101010,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addmeo,XO,
 0b0011001010,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addze,XO,
 0b1011001010,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addzeo,XO,
+0b0001001010,ALU,OP_ADDG6S,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addg6s,XO,
 0b0000011100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,and,X,
 0b0000111100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,andc,X,
 0b0011111100,LOGICAL,OP_BPERM,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bpermd,X,

commit c95af3163525710182eacbe76237e702a461d5a1
Author: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date:   Mon Jul 26 14:48:38 2021 +0000

    power_enums: cbcdtd instruction

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 2f124e2..4f999f7 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -230,6 +230,7 @@ _insns = [
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",
+    "cbcdtd",
     "cdtbcd",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
@@ -401,6 +402,7 @@ class MicrOp(Enum):
     OP_SVSTEP = 82
     OP_ADDG6S = 83
     OP_CDTBCD = 84
+    OP_CBCDTD = 85


 @unique

commit e8ebd09f91b87609806d5910b2ca8587308bdbca
Author: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date:   Mon Jul 26 14:48:25 2021 +0000

    power_enums: cdtbcd instruction

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index e631f37..2f124e2 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -230,6 +230,7 @@ _insns = [
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",
+    "cdtbcd",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
     "crand", "crandc", "creqv",
@@ -399,6 +400,7 @@ class MicrOp(Enum):
     OP_SVSHAPE = 81
     OP_SVSTEP = 82
     OP_ADDG6S = 83
+    OP_CDTBCD = 84


 @unique

commit 693e96d7c9936708e288f62bebe8bae1c926b3aa
Author: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date:   Mon Jul 26 14:48:03 2021 +0000

    power_enums: addg6s instruction

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 9754938..e631f37 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -225,6 +225,7 @@ _insns = [
     "NONE", "add", "addc", "addco", "adde", "addeo",
     "addi", "addic", "addic.", "addis",
     "addme", "addmeo", "addo", "addze", "addzeo",
+    "addg6s",
     "and", "andc", "andi.", "andis.",
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
@@ -397,6 +398,7 @@ class MicrOp(Enum):
     OP_SVREMAP = 80
     OP_SVSHAPE = 81
     OP_SVSTEP = 82
+    OP_ADDG6S = 83


 @unique