Mealy VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.all;

ENTITY mealy IS
	PORT (
		I IN BIT;
		reset, clockIN BIT;
		O OUT BIT);
END mealy;

ARCHITECTURE mealy OF mealy IS
TYPE state IS (s0, s1, s2, s3, s4, s5, s6);
SIGNAL pr_state, nx_state state;
BEGIN
	PROCESS (reset, clock)
	BEGIN
		IF (reset='1') THEN
			pr_state = s0;
		ELSIF (clock'EVENT AND clock='1') THEN
			pr_state = nx_state;
		END IF;
	END PROCESS;
	PROCESS (I, pr_state)
	BEGIN
		CASE pr_state IS
			WHEN s0 =
				IF (i = '0') THEN
					O = '1';
					nx_state = s1;
				ELSE
					O = '0';
					nx_state = s2;
				END IF;
			WHEN s1 =
				IF (i = '0') THEN
					O = '1';
					nx_state = s3;
				ELSE
					O = '0';
					nx_state = s4;
				END IF;
			WHEN s2 =
				IF (i = '0') THEN
					O = '0';
					nx_state = s4;
				ELSE
					O = '1';
					nx_state = s4;
				END IF;
			WHEN s3 =
				IF (i = '0') THEN
					O = '0';
					nx_state = s5;
				ELSE
					O = '1';
					nx_state = s5;
				END IF;
			WHEN s4 =
				IF (i = '0') THEN
					O = '1';
					nx_state = s5;
				ELSE
					O = '0';
					nx_state = s6;
				END IF;
			WHEN s5 =
				IF (i = '0') THEN
					O = '0';
					nx_state = s0;
				ELSE
					O = '1';
					nx_state = s0;
				END IF;
			WHEN s6 =
				IF (i = '0') THEN
					O = '1';
					nx_state = s0;
				END IF;
		END CASE;
END PROCESS;
END mealy;

entity test_bench is
end test_bench;

architecture test_bench_arch of test_bench is
component mealy is
	port(
		I IN BIT;
		reset, clockIN BIT;
		O OUT BIT);
end component;
signal inp  bit;
signal rst, clk bit;
signal outp bit;
begin
	UUT mealy port map(inp, rst, clk, outp);
	process
	begin
		clk = '0';
		wait for 5ns;
		clk = '1';
		wait for 5ns;
	end process;

	process
	begin
		inp = '0';
		wait for 10ns;
		inp = '1';
		wait for 10ns;
		inp = '0';
		wait for 10ns;
		inp = '1';
		wait for 10ns;
		inp = '1';
		wait for 10ns;
		inp = '0';
		wait for 10ns;
	end process;


end test_bench_arch;