module proba (
    input clk,
    input rst,
    input en,
    output [7:0] r
    );

reg [7:0] shr = 8'b00000001;
reg dir;
wire first, last;

always @ (posedge clk)
if (rst)
    shr <= 8'b00000001;
else if (en)
    if (dir)
        shr <= { 1'b0, shr[7:1] }; //jobbra
    else
        shr <= { shr[6:0], 1'b0 }; //balra

assign first = (shr[0] == 1);
assign last = (shr[7] == 1);

always @ (posedge clk)

if (rst)
    dir <= 0;
else if (en)
    if (first|last) dir<=~dir;

assign r = shr;

endmodule