API tools faq
paste
Guest User

REDDIT

a guest
Nov 1st, 2025
50
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 219.71 KB | None | 0 0
raw download clone embed print report
  1. | Subsystem | Features |
  2. |---------------------------------|-------------------------------------------------------------------------------------------------------------------------------------------|
  3. | Cortex®<br>-A55 MPCore platform | Two Cortex®<br>-A55 processors operating up to 1.7 GHz |
  4. | | • 32 KB L1 Instruction Cache |
  5. | | • 32 KB L1 Data Cache |
  6. | | • 64 KB per-core L2 cache |
  7. | | • Media Processing Engine (MPE) with Arm®<br>Neon™<br>technology supporting the<br>Advanced Single Instruction Multiple Data architecture |
  8. | | • Floating Point Unit (FPU) with support of the Arm®<br>VFPv4-D16 architecture |
  9. | | Supports of 64-bit Arm® v8.2-A architecture |
  10. | | 256 KB cluster L3 cache |
  11. | | Parity/ECC protection on L1 cache, L2 cache, and TLB RAMs |
  12. | Cortex®-M33 core platform | • Stand by monitoring with Cortex®<br>-A55 and other high-power modules<br>power gated |
  13. | | Cortex®<br>-M33 CPU operating up to 250 MHz |
  14. | | • Supports FPU |
  15. | | • Supports MPU |
  16. | | • Supports NVIC |
  17. | | • Supports FPB |
  18. | | • Supports DWT and ITM |
  19. | | • Two-way set-associative 16 KB System Cache with parity support |
  20. | | • Two-way set-associative 16 KB Code Cache with parity support |
  21. | | • 256 KB tightly coupled memory (TCM) |
  22. | Neural Processing Unit (NPU) | Neural Network performance (256 MACs operating up to 1.0 GHz and 2 OPS/MAC) |
  23.  
  24. | Subsystem | Features |
  25. |------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
  26. | | • NPU targets 8-bit and 16-bit integer RNN |
  27. | | • Handles 8-bit weights |
  28. | Image Sensor Interface (ISI) | • Standard pixel formats commonly used in many camera input protocols |
  29. | | • Programmable resolutions up to 2K |
  30. | | • Image processing for: |
  31. | | — Supports one source of up to 2K horizontal resolution |
  32. | | — Supports pixel rate up to 200 Mpixel/s |
  33. | | • Image down scaling via decimation and bi-phase filtering |
  34. | | • Color space conversion |
  35. | | • Interlaced to progressive conversions |
  36. | On-chip memory | Boot ROM (256 KB) for Cortex®<br>-A55 |
  37. | | Boot ROM (256 KB) for Cortex®<br>-M33 |
  38. | | On-chip RAM (640 KB) |
  39. | External memory interface | 16-bit DRAM interface: |
  40. | | • LPDDR4X/LPDDR4 with inline ECC |
  41. | | • Supports up to 2 Gbyte DDR memory space |
  42. | | Three Ultra Secure Digital Host Controller (uSDHC) interfaces: |
  43. | | • One eMMC 5.1 (8-bit) compliance with HS400 DDR signaling to support up to 400<br>MB/sec |
  44. | | • One SDXC (4-bit, no eMMC5.1, with extended capacity) |
  45. | | • One SDIO (4-bit, SD/SDIO 3.01 compliance with 200 MHz SDR signaling and up<br>to 100 MB/sec) |
  46. | | FlexSPI Flash with support for XIP (for Cortex®<br>-A55 in low-power mode) and support<br>for either one Octal SPI or Quad SPI FLASH device. It also supports both Serial NOR<br>and Serial NAND flash using the FlexSPI. |
  47. | Pixel Pipeline (PXP) | • BitBlit |
  48. | | • Flexible image composition options—alpha, chroma key |
  49. | | • Porter-Duff operation |
  50. | | • Image rotation (90°, 180°, 270°) |
  51. | | • Image resize |
  52. | | • Color space conversion |
  53. | | • Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400) |
  54. | | Table continues on the next page |
  55.  
  56. | Subsystem | Features |
  57. |------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
  58. | | • Standard 2D-DMA operation |
  59. | LCDIF Display Controller | The LCDIF can drive any of three displays:<br>• MIPI DSI: up to 1920x1200p60<br>• LVDS Tx: up to 1366x768p60 or 1280x800p60<br>• Parallel display: up to 1366x768p60 or 1280x800p60 |
  60. | MIPI CSI-2 Interface | One 2-lane MIPI CSI-2 camera input:<br>• Complaint with MIPI CSI-2 specification v1.3 and MIPI D-PHY specification v1.2<br>• Supports up to 2 Rx data lanes (plus 1 Rx clock lane)<br>• Supports 80 Mbps – 1.5 Gbps per lane data rate in high speed operation<br>• Supports 10 Mbps data rate in low power operation |
  61. | MIPI DSI Interface | One 4-lane MIPI DSI display with data supplied by the LCDIF<br>• Compliant with MIPI DSI specification v1.2 and MIPI D-PHY specification v1.2<br>• Capable of resolutions achievable with a 200 MHz pixel clock and active pixel rate<br>of 140 Mpixel/s with 24-bit RGB.<br>• Supports 80 Mbps—1.5 Gbps data rate per lane in high speed operation<br>• Supports 10 Mbps data rate in low power operation |
  62. | Audio | • Three SAI interfaces:<br>— SAI1 supports 2-lane and SAI3 supports 1 lane<br>— SAI2 supports 4 lanes<br>— SAI2 and SAI3 support glue-less switching between PCM and stereo<br>DSD operation<br>• One SPDIF supports raw capture mode that can save all the incoming bits into<br>audio buffer<br>• 24-bit PDM supports up to 8-microphones (4 lanes) |
  63. | GPIO and input/output multiplexing | General-purpose input/output (GPIO) modules with interrupt capability<br>Input/output multiplexing controller (IOMUXC) to provide centralized pad control |
  64. | Power management | Temperature sensor with programmable trip points<br>Flexible power domain partitioning with internal power switches to support efficient<br>power management |
  65. | Connectivity | Two USB 2.0 controllers and PHYs interfaces<br>Two Controller Area Network (FlexCAN) modules, each optionally supporting flexible<br>data-rate (FD) |
  66.  
  67. | Subsystem | Features |
  68. |--------------|--------------------------------------------------------------------------------------------------------------------|
  69. | | Two Improved Inter Integrated Circuit (I3C) modules |
  70. | | Two 32-pin FlexIO modules |
  71. | | Three Ultra Secure Digital Host Controller (uSDHC) interfaces |
  72. | | Two Ethernet controllers (capable of simultaneous operation): |
  73. | | • One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),<br>Ethernet AVB, and IEEE 1588 |
  74. | | • One Gigabit Ethernet controller with support for TSN in addition to EEE, Ethernet<br>AVB, and IEEE 1588 |
  75. | | Eight Low Power SPI (LPSPI) modules |
  76. | | Eight Low Power I2C modules |
  77. | | Eight Low Power Universal Asynchronous Receiver/Transmitter (LPUART) modules: |
  78. | | • Programmable baud rates up to 5 Mbps |
  79. | | One Analog-to-Digital Converter (SAR ADC) module |
  80. | | • 12-bit 4-channel with 1 MS/s |
  81. | Security | Trusted Resource Domain Controller (TRDC) |
  82. | | • Supports 16 domains |
  83. | | Arm®<br>TrustZone®<br>(TZ) architecture, including both Trustzone-A and Trustzone-M |
  84. | | On-chip RAM (OCRAM) secure region protection using OCRAM controller |
  85. | | EdgeLock®<br>secure enclave |
  86. | | Battery Backed Security Module (BBSM) |
  87. | | • Secure real-time clock (RTC) |
  88. | System debug | Arm® CoreSight™<br>debug and trace technology |
  89. | | Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering |
  90. | | Unified trace capability for dual core Cortex®<br>-A55 and Cortex®<br>-M33 CPUs |
  91. | | Cross Triggering Interface (CTI) |
  92. | | Support for 4-pin (JTAG) debug interface and SWD |
  93.  
  94. | Part number | Part<br>differen<br>tiator | Number<br>of Cores<br>(A55) | Max<br>speed | NPU | GDET | Camera | Display | Connecti<br>vity | Audio | DDR | Packag<br>e |
  95. |---------------------|----------------------------|-----------------------------|--------------|-----|--------------|---------------------------------------------------------------|----------------------------------------------------------------------------------------|-----------------------------------------|---------------|-------------|---------------------------------------|
  96. | MIMX9352A<br>VTXMAC | 5 | 2 | 1.7<br>GHz | NPU | Disable<br>d | •<br>2-lane<br>1080p30<br>MIPI CSI<br>•<br>Parallel<br>camera | •<br>4-lane<br>1080p6<br>0 MIPI<br>DSI<br>•<br>4-lane<br>LVDS<br>• Parallel<br>display | •<br>2x<br>GbE<br>•<br>2x<br>USB<br>2.0 | 7x I2S<br>TDM | 3.7<br>GT/s | 14 x 14<br>mm,<br>0.65<br>mm<br>pitch |
  97. | MIMX9352A<br>VTXMBC | 5 | 2 | 1.7<br>GHz | NPU | Enable<br>d | •<br>2-lane<br>1080p30<br>MIPI CSI<br>•<br>Parallel<br>camera | •<br>4-lane<br>1080p6<br>0 MIPI<br>DSI<br>•<br>4-lane<br>LVDS<br>• Parallel<br>display | •<br>2x<br>GbE<br>•<br>2x<br>USB<br>2.0 | 7x I2S<br>TDM | 3.7<br>GT/s | 14 x 14<br>mm,<br>0.65<br>mm<br>pitch |
  98. | MIMX9351A<br>VTXMAC | 5 | 1 | 1.7<br>GHz | NPU | Disable<br>d | •<br>2-lane<br>1080p30<br>MIPI CSI<br>•<br>Parallel<br>camera | •<br>4-lane<br>1080p6<br>0 MIPI<br>DSI<br>•<br>4-lane<br>LVDS<br>• Parallel<br>display | •<br>2x<br>GbE<br>•<br>2x<br>USB<br>2.0 | 7x I2S<br>TDM | 3.7<br>GT/s | 14 x 14<br>mm,<br>0.65<br>mm<br>pitch |
  99. | MIMX9332A<br>VTXMAC | 3 | 2 | 1.7<br>GHz | — | Disable<br>d | •<br>2-lane<br>1080p30<br>MIPI CSI<br>•<br>Parallel<br>camera | •<br>4-lane<br>1080p6<br>0 MIPI<br>DSI<br>•<br>4-lane<br>LVDS<br>• Parallel<br>display | •<br>2x<br>GbE<br>•<br>2x<br>USB<br>2.0 | 7x I2S<br>TDM | 3.7<br>GT/s | 14 x 14<br>mm,<br>0.65<br>mm<br>pitch |
  100. | MIMX9331A<br>VTXMAC | 3 | 1 | 1.7<br>GHz | — | Disable<br>d | •<br>2-lane<br>1080p30<br>MIPI CSI<br>•<br>Parallel<br>camera | •<br>4-lane<br>1080p6<br>0 MIPI<br>DSI<br>•<br>4-lane<br>LVDS<br>• Parallel<br>display | •<br>2x<br>GbE<br>•<br>2x<br>USB<br>2.0 | 7x I2S<br>TDM | 3.7<br>GT/s | 14 x 14<br>mm,<br>0.65<br>mm<br>pitch |
  101.  
  102. | Qualification Level | | | | | | Silicon Revision | |
  103. |--------------------------------|---------------|---------------|-------------|----------------------------------------|--------|-----------------------------------------------------------------|----|
  104. | | Family | | | | | Special Fuse | |
  105. | Sub-family<br>#Cortex-A cores | | | | | | Cortex-A maximum CPU frequency<br>/ Reserved | |
  106. | Temperature Tj support | | | | | | Package type | |
  107. | Qualification<br>level | Q | Family | 93 | Temperature Tj support | + | Cortex-A maximum CPU<br>frequency | # |
  108. | Samples | P | i.MX9300 | 93 | Commercial: 0˚C to +95°C | D | 1.7 GHz | M |
  109. | Mass Production | M | | | Industrial:-40˚C to +105°C | C | 900 MHz | D |
  110. | Special | S | | | Extended Industrial:-40˚C to +125°C | X | | |
  111. | | | | | Automotive:-40˚C to +125˚C | A | Reserved | \$ |
  112. | Sub-family | 93<br>11 x 11 | 93<br>14 x 14 | 93<br>9 x 9 | | | Can be used to designate special<br>versions, e.g., reduced GPU | |
  113. | | mm | mm | mm | Package type | VV | performance | |
  114. | With NPU (Full -<br>featured) | 5 | 5 | 2 | 14 x 14 mm, 0.65 mm pitch,<br>FCBGA306 | VT | No additional information required | X |
  115. | Without NPU | 3 | 3 | 1 | 11 x 11 mm, 0.5 mm pitch,<br>FCBGA306 | VV | Reserved | Z |
  116. | Reduced<br>feature/performance | 0 | | | 9 x 9 mm, 0.5 mm pitch, FCBGA208 | VX | | |
  117. | | | | | | | Special Fuse | % |
  118. | | | | | Silicon Rev | | No special fuse | A |
  119. | #Cortex-A cores<br>Dual-core | | @<br>2 | | Rev 1.0 | &<br>A | Full featured with GDET enabled | B |
  120. | Single core | | 1 | | Rev. 2.0 | B | | |
  121. | | | | | Rev. 3.0 | C | | |
  122.  
  123. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  124. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  125. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  126.  
  127. | Signal Name | Remarks |
  128. |---------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
  129. | CLKIN1/CLKIN2 | CLKIN1 and CLKIN2 are input pins without internal pull-up and pull-down. An external 10K<br>pull-down resistor is recommended if they are not used. |
  130. | NC | These signals are No Connect (NC) and should be unconnected in the application. |
  131. | ONOFF | A brief connection to GND in the OFF mode causes the internal power management state machine<br>to change the state to ON. In the ON mode, a brief connection to GND generates an interrupt<br>(intended to be a software-controllable power-down). A connection to GND for a period of time<br>longer than the value configured in the BBNSM_CTRL[BTN_TIMEOUT] causes a forced OFF<br>(PMIC_ON_REQ output "L"), as long as there is no pending RTC alarm event or tamper event. |
  132. | POR_B | POR_B has no internal pull-up/down resistor, and requires external pull-up resistor<br>to NVCC_BBSM_1P8. |
  133. | | It is recommended that POR_B is properly handled during power up/down. Please see the EVK<br>design for details. |
  134. | RTC_XTALI/RTC_XTALO | To hit the exact oscillation frequency, the board capacitors must be reduced to account for the board<br>and chip parasitics. The integrated oscillation amplifier is self-biasing, but relatively weak. Care<br>must be taken to limit the parasitic leakage from RTC_XTALI and RTC_XTALO to either the power<br>or the ground (> 100 MΩ). This de-biases the amplifier and reduces the start-up margin. |
  135. | | If you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must<br>remain unconnected or driven by a complementary signal. The logic level of this forcing clock<br>must not exceed the NVCC_BBSM_1P8 level and the frequency shall be < 50 kHz under the<br>typical conditions. |
  136. | XTALI_24M/XTALO_24M | The system requires 24 MHz on XTALI/XTALO. The crystal cannot be eliminated by an external 24<br>MHz oscillator. |
  137. | | If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter<br>requirements. See Clock sources and relevant interface specifications chapters for details. |
  138.  
  139. | | | | | Table 4. Unused function strapping recommendations |
  140. |--|--|--|--|----------------------------------------------------|
  141. |--|--|--|--|----------------------------------------------------|
  142.  
  143. | Function | Ball name | Recommendations<br>if unused |
  144. |----------|-------------------------------------------------------------|------------------------------------------|
  145. | ADC | ADC_IN0, ADC_IN1, ADC_IN2, ADC_IN3 | Tie to ground |
  146. | TAMPER | TAMPER0, TAMPER1 | Tie to ground |
  147. | LVDS | VDD_LVDS_1P8, LVDS_CLK_P, LVDS_CLK_N, LVDS_Dx_P, LVDS_Dx_N, | Tie to ground through 10<br>KΩ resistors |
  148.  
  149. | Function | Ball name | Recommendations<br>if unused |
  150. |-------------------------|--------------------------------------------|------------------------------------------------------------------------|
  151. | Digital I/O<br>supplies | NVCC_GPIO, NVCC_WAKEUP, NVCC_AON, NVCC_SD2 | Tie to ground through 10<br>KΩ resistors if entire bank is<br>not used |
  152.  
  153. | Function | Ball name | Recommendations |
  154. |-------------------------------------|------------------------------------------------------------------|-----------------|
  155. | Only<br>MIPI_CSI<br>used | VDD_MIPI_0P8, VDD_MIPI_1P8 | Supply |
  156. | | MIPI_DSI1_CLK_P, MIPI_DSI1_CLK_N, MIPI_DSI1_Dx_P, MIPI_DSI1_Dx_N | Not connected |
  157. | Only | VDD_MIPI_0P8, VDD_MIPI_1P8 | Supply |
  158. | MIPI_DSI<br>used | MIPI_CSI1_CLK_P, MIPI_CSI1_CLK_N, MIPI_CSI1_Dx_P, MIPI_CSI1_Dx_N | Not connected |
  159. | Neither | VDD_MIPI_0P8, VDD_MIPI_1P8 | Tie to ground |
  160. | MIPI_CSI<br>nor<br>MIPI_DSI<br>used | MIPI_CSI1_CLK_P, MIPI_CSI1_CLK_N, MIPI_CSI1_Dx_P, MIPI_CSI1_Dx_N | Not connected |
  161. | | MIPI_DSI1_CLK_P, MIPI_DSI1_CLK_N, MIPI_DSI1_Dx_P, MIPI_DSI1_Dx_N | Not connected |
  162. | | MIPI_REXT | Tie to ground |
  163.  
  164. | Function | Ball name | Recommendations |
  165. |-------------------------------------------------------------|------------------------------------------------------|-----------------|
  166. | Only<br>USB1<br>used | VDD_USB_3P3, VDD_USB_1P8, VDD_USB_0P8 | Supply |
  167. | | USB2_VBUS, USB2_D_P, USB2_D_N, USB2_ID, USB2_TXRTUNE | Not connected |
  168. | Only<br>USB2<br>used<br>Neither<br>USB1 nor<br>USB2<br>used | VDD_USB_3P3, VDD_USB_1P8, VDD_USB_0P8 | Supply |
  169. | | USB1_VBUS, USB1_D_P, USB1_D_N, USB1_ID, USB1_TXRTUNE | Not connected |
  170. | | VDD_USB_3P3, VDD_USB_1P8, VDD_USB_0P8 | Tie to ground |
  171. | | USB1_VBUS, USB1_D_P, USB1_D_N, USB1_ID, USB1_TXRTUNE | Not connected |
  172. | | USB2_VBUS, USB2_D_P, USB2_D_N, USB2_ID, USB2_TXRTUNE | Not connected |
  173.  
  174. | For these characteristics, … | Topic appears … |
  175. |----------------------------------------------|-------------------------------------------------|
  176. | Absolute maximum ratings | Absolute maximum ratings |
  177. | Thermal resistance | Thermal resistance |
  178. | Operating ranges | Operating ranges |
  179. | Clock sources | Clock sources |
  180. | Maximum supply currents | Maximum supply currents |
  181. | Power modes | Power modes |
  182. | Power supplies requirements and restrictions | Power supplies requirements and<br>restrictions |
  183.  
  184. | Parameter description | Symbol | Min | Max | Unit | Notes |
  185. |-------------------------------------------------------|----------------------------------------|------|-------|------|-------|
  186. | Core supplies input voltages | VDD_SOC | -0.3 | 1.15 | V | — |
  187. | GPIO supply voltage | NVCC_GPIO,<br>NVCC_WAKEUP,<br>NVCC_AON | -0.3 | 3.8 | V | — |
  188. | I/O supply for SD2 | NVCC_SD2 | -0.3 | 3.8 | V | — |
  189. | DDR PHY supply voltage | VDD2_DDR | -0.3 | 1.575 | V | — |
  190. | DDR I/O supply voltage | VDDQ_DDR | -0.3 | 1.575 | V | — |
  191. | I/O supply and I/O Pre-driver<br>supply for BBSM bank | NVCC_BBSM_1P8 | -0.3 | 2.15 | V | — |
  192. | USB VBUS input detected | USB1_VBUS,<br>USB2_VBUS | -0.3 | 3.95 | V | — |
  193. | Power for USB OTG PHY | VDD_USB_0P8 | -0.3 | 1.15 | V | — |
  194.  
  195. | | | Table 8. Absolute maximum ratings continued | | |
  196. |--|--|---------------------------------------------|--|--|
  197. |--|--|---------------------------------------------|--|--|
  198.  
  199. | Parameter description | Symbol | Min | Max | Unit | Notes |
  200. |----------------------------|--------------|------|----------------|------|-------|
  201. | | VDD_USB_1P8 | -0.3 | 2.15 | V | — |
  202. | | VDD_USB_3P3 | -0.3 | 3.95 | V | — |
  203. | MIPI PHY supply voltage | VDD_MIPI_0P8 | -0.3 | 1.15 | V | — |
  204. | | VDD_MIPI_1P8 | -0.3 | 2.15 | V | — |
  205. | LVDS PHY supply voltage | VDD_LVDS_1P8 | -0.3 | 2.15 | V | — |
  206. | Analog core supply voltage | VDD_ANA_0P8 | -0.3 | 1.15 | V | — |
  207. | | VDD_ANAx_1P8 | -0.3 | 2.15 | V | 1 |
  208. | Input/output voltage range | Vin/Vout | -0.3 | OVDD2<br>+ 0.3 | V | — |
  209. | Storage temperature range | TSTORAGE | -40 | 150 | oC | — |
  210.  
  211. | | Parameter description | Rating | Reference | Comment |
  212. |-----------------------------------------------|-----------------------------------------------------------------------------------------------------------|---------|-----------|---------|
  213. | Electrostatic | Human Body Model (HBM) | ±1000 V | JS-001 | — |
  214. | Discharge (ESD)<br>Charged Device Model (CDM) | ±250 V | JS-002 | — | |
  215. | Latch-up (LU) | Immunity level:<br>• Class I @ 25 °C<br>ambient temperature<br>• Class II @ 125 °C<br>ambient temperature | A<br>A | JESD78 | — |
  216.  
  217. | Rating | Board Type1 | Symbol | Values | Unit |
  218. |-------------------------------------------------------------------|----------------|--------|--------|------|
  219. | Junction to Ambient Thermal Resistance2 | JESD51-9, 2s2p | RθJA | 21.7 | °C/W |
  220. | Junction-to-Top of Package<br>Thermal Characterization parameter3 | JESD51-9, 2s2p | ΨJT | 0.1 | °C/W |
  221.  
  222. | Table 10. 14 x 14 mm FCPBGA thermal resistance datacontinued | | |
  223. |--------------------------------------------------------------|--|--|
  224. |--------------------------------------------------------------|--|--|
  225.  
  226. | Rating | Board Type1 | Symbol | Values | Unit |
  227. |--------------------------------------|--------------|--------|--------|------|
  228. | Junction to Case Thermal Resistance3 | JESD51-9, 1s | RθJC | 5.4 | °C/W |
  229.  
  230. | Power supplies | Modules |
  231. |----------------|-----------------------------------------------|
  232. | VDD_SOC | SoC synthesized DRAM controller digital logic |
  233. | VDD_ANA_0P8 | DRAM PLL and PHY digital logic |
  234. | VDD_ANAx_1P8 | DRAM PLL and PHY analog circuitry |
  235. | VDD2_DDR | 1.1 V DRAM PHY I/O supply |
  236. | VDDQ_DDR | 0.6 V DRAM PHY I/O supply for LPDDR4X |
  237.  
  238. | Parameter Description | Symbol | Min | Typ | Max1 | Unit | Comment | |
  239. |------------------------------------------------------------------|----------------------|-------|------|------|------|-----------------------------------------|--|
  240. | Power supply for SoC<br>logic and Arm core | VDD_SOC | 0.85 | 0.90 | 0.95 | V | Power supply for SoC,<br>overdrive mode | |
  241. | | | 0.80 | 0.85 | 0.90 | V | Power supply for SoC,<br>nominal mode | |
  242. | | | 0.76 | 0.80 | 0.84 | V | Power supply for SoC, low<br>drive mode | |
  243. | | | 0.61 | 0.65 | 0.70 | V | Power supply for SoC,<br>suspend mode | |
  244. | Digital supply for PLLs, | VDD_ANA_0P8 | 0.76 | 0.80 | 0.84 | V | — | |
  245. | temperature sensor,<br>LVCMOS I/O, MIPI, | VDD_MIPI_0P8 | | | | | | |
  246. | and USB PHYs | VDD_USB_0P8 | | | | | | |
  247. | 1.8 V supply | VDD_ANAx_1P8 | 1.71 | 1.80 | 1.89 | V | 2 | |
  248. | for PLLs, eFuse,<br>Temperature sensor, | VDD_LVDS_1P8 | | | | | | |
  249. | LVCMOS voltage<br>detect reference, ADC, | VDD_MIPI_1P8 | | | | | | |
  250. | 24 MHz XTAL, LVDS,<br>MIPI, and USB PHYs | VDD_USB_1P8 | | | | | | |
  251. | 3.3 V supply for<br>USB PHY | VDD_USB_3P3 | 3.069 | 3.30 | 3.45 | V | — | |
  252. | Voltage supply for<br>DRAM PHY | VDD2_DDR | 1.06 | 1.10 | 1.14 | V | — | |
  253. | Voltage supply for | VDDQ_DDR | 1.06 | 1.10 | 1.14 | V | LPDDR4 | |
  254. | DRAM PHY I/O | | 0.57 | 0.60 | 0.67 | V | LPDDR4X | |
  255. | I/O supply and I/O pre<br>driver supply for GPIO<br>in BBSM bank | NVCC_BBSM_1P8 | 1.62 | 1.80 | 1.98 | V | — | |
  256. | Power supply for GPIO<br>when it is in 1.8 V mode | NVCC_AON<br>NVCC_SD2 | 1.62 | 1.80 | 1.98 | V | — | |
  257.  
  258. | Parameter Description | Symbol | Min | Typ | Max1 | Unit | Comment | | |
  259. |---------------------------------------------------|--------------------------|------|------|-------|------|--------------------------------------------------------------------------------------------------------------|--|--|
  260. | Power supply for GPIO<br>when it is in 3.3 V mode | NVCC_GPIO<br>NVCC_WAKEUP | 3.00 | 3.30 | 3.465 | V | — | | |
  261. | | Temperature Ranges | | | | | | | |
  262. | Junction temperature<br>— Automotive | Tj3 | -40 | — | +125 | °C | See the application note, i.MX 93<br>Product Lifetime Usage Estimates<br>for information on product lifetime | | |
  263. | Ambient temperature<br>— Automotive | Ta | -40 | — | +85 | | (power-on hours) for this processor. | | |
  264.  
  265. | Main modules | Frequency<br>(Low Drive mode) | Frequency<br>(Nominal mode) | Frequency<br>(Overdrive mode) |
  266. |-----------------------------|-------------------------------|-----------------------------|-------------------------------|
  267. | EdgeLock®<br>Secure Enclave | 133 MHz | 200 MHz | 250 MHz |
  268. | Cortex®<br>-M33 core | 133 MHz | 200 MHz | 250 MHz |
  269. | Cortex®<br>-A55 cores | 0.9 GHz | 1.4 GHz | 1.7 GHz |
  270. | DRAM | 933 MHz | 1400 MHz | 1866 MHz |
  271. | NPU | 500 MHz | 800 MHz | 1000 MHz |
  272.  
  273. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  274. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  275. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  276.  
  277. | Parameter Description | Symbol | Min | тур | Max | Unit |
  278. |-----------------------------------|--------|-----|---------|-----|------|
  279. | RTC_XTALI Oscillator <sup>1</sup> | ckil | $-$ | 32.7682 | $-$ | kHz |
  280.  
  281. | Parameter Description | Symbol | Low drive<br>mode | Nominal mode | Overdrive<br>mode | Unit |
  282. |---------------------------|----------|-------------------|--------------|-------------------|------|
  283. | EXT_CLK maximum frequency | Text clk | 133 | 200 | 200 | MHz |
  284.  
  285. | | Symbol | Min | Typ | Max | Unit |
  286. |-----------|------------|---------------------|--------|---------------------|------|
  287. | Frequency | | | 32.768 | | kHz |
  288. | RTC_XTALI | $V_{IH}$ | 0.9 x NVCC_BBSM_1P8 | | NVCC_BBSIM_1P8 | |
  289. | | $V_{IL}$ | 0 | | 0.1 x NVCC_BBSM_1P8 | |
  290. | | Duty cycle | 45 | | 55 | % |
  291.  
  292. | Symbol | <b>Parameter Description</b> | Min | Тур | Max | Unit |
  293. |--------|------------------------------|-----|-----|-----|------|
  294. | fXTAL | Frequency | | 24 | | MHz |
  295. | CLOAD | Cload | | 12 | | pF |
  296. | DL | Drive level | | | 100 | μW |
  297. | ESR | ESR | | | 120 | Ω |
  298.  
  299. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | <sup>o</sup> 2025 NXP B.V. All rights reserved |
  300. |--------------------------|----------------------------------------------------------------------------|------------------------------------------------|
  301. | Product<br>Shee<br>I)ata | $\cup \triangle \cup$<br>liilv | teedhack |
  302.  
  303. | Symbol | Parameter Description | Min | Typ | Max | Unit |
  304. |--------|----------------------------|-----|--------|-----|------|
  305. | fXTAL | Frequency (crystal mode) 1 | — | 32.768 | — | kHz |
  306. | CLOAD | Cload | — | 12.5 | — | pF |
  307. | ESR | ESR | — | — | 90 | KΩ |
  308.  
  309. | Power rail | Max current | |
  310. |---------------------------------------------|--------------------------------------------------------------------------------|----|
  311. | VDD_SOC | 2700 | mA |
  312. | VDD_ANA_0P8 | 50 | mA |
  313. | VDD_ANAx_1P8 1 | 250 | mA |
  314. | NVCC_BBSM_1P8 | 2 | mA |
  315. | NVCC_GPIO, NVCC_WAKEUP, NVCC_AON | Imax = N x C x V x (0.5 x F) | |
  316. | | Where: | |
  317. | | N—Number of IO pins supplied by the power line | |
  318. | | C—Equivalent external capacitive load | |
  319. | | V—IO voltage | |
  320. | | (0.5 x F)—Data change rate. Up to 0.5 of the clock<br>rate (F). | |
  321. | | In this equation, Imax is in Amps, C in Farads, V in<br>Volts, and F in Hertz. | |
  322. | VDDQ_DDR | 160 | mA |
  323. | VDD2_DDR | 525<br>mA | |
  324. | VDD_MIPI_0P8 (for MIPI CSI-2 2-lane Rx PHY) | 18<br>mA | |
  325. | VDD_MIPI_0P8 (for MIPI-DSI 4-lane Tx PHY) | 33<br>mA | |
  326. | VDD_MIPI_1P8 (for MIPI CSI-2 2-lane Rx PHY) | 2.5<br>mA | |
  327.  
  328. | Product Data Shee | |
  329. |-------------------|--|
  330.  
  331. | Power rail | Max current | Unit |
  332. |-------------------------------------------|------------------------|------|
  333. | VDD_MIPI_1P8 (for MIPI-DSI 4-lane Tx PHY) | 9.5 | mA |
  334. | VDD_USB_3P3 (for USB PHY) | 25.2 | mA |
  335. | VDD_USB_1P8 (for USB PHY) | 36.2 | mA |
  336. | VDD_USB_0P8 (for USB PHY) | 22.2 | mA |
  337. | VDD_LVDS_1P8 | Max dynamic current 45 | mA |
  338.  
  339. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  340. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  341. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  342.  
  343. | Table 20. The power supply states | | | | |
  344. |-----------------------------------|--|--|--|--|
  345. |-----------------------------------|--|--|--|--|
  346.  
  347. | Power rail | OFF | BBSM | SUSPEND<br>(Analog on) | IDLE | RUN/LP RUN |
  348. |----------------------------------------------------------------------------|-----|------|------------------------|------|------------|
  349. | NVCC_BBSM_1P8 | OFF | ON | ON | ON | ON |
  350. | VDD_SOC | OFF | OFF | ON | ON | ON |
  351. | VDD2_DDR<br>VDDQ_DDR | OFF | OFF | ON | ON | ON |
  352. | NVCC_ <xxx></xxx> | OFF | OFF | ON | ON | ON |
  353. | VDD_ANA_0P8<br>VDD_MIPI_0P8<br>VDD_USB_0P8 | OFF | OFF | ON | ON | ON |
  354. | VDD_ANAx_1P8<br>VDD_LVDS_1P8<br>VDD_MIPI_1P8<br>VDD_USB_1P8<br>VDD_USB_3P3 | OFF | OFF | ON | ON | ON |
  355.  
  356. | | IDLE | SUSPEND | BBSM |
  357. |-------------------------|------|---------|------|
  358. | CCM LPM mode | WAIT | STOP | N/A |
  359. | Arm Cortex®-A55 CPU0 | OFF | OFF | OFF |
  360. | Arm Cortex®-A55 CPU1 | OFF | OFF | OFF |
  361. | Shared L3 cache | ON | OFF | OFF |
  362. | Display | OFF | OFF | OFF |
  363. | DRAM controller and PHY | ON | OFF | OFF |
  364. | ARM_PLL | OFF | OFF | OFF |
  365. | DRAM_PLL | OFF | OFF | OFF |
  366. | SYSTEM_PLL 1/2/3 | ON | OFF | OFF |
  367. | XTAL | ON | OFF | OFF |
  368.  
  369. | | IDLE | SUSPEND | BBSM |
  370. |--------------------------|--------------------|--------------|------|
  371. | RTC | ON | ON | ON |
  372. | External DRAM device | Self-Refresh | Self-Refresh | OFF |
  373. | USB PHY | In Low Power State | OFF | OFF |
  374. | DRAM clock | 266 MHz | OFF | OFF |
  375. | NOC clock | 133 MHz | OFF | OFF |
  376. | AXI clock | 133 MHz | OFF | OFF |
  377. | Module clocks | ON as needed | OFF | OFF |
  378. | EdgeLock® Secure Enclave | ON | ON | ON |
  379. | GPIO Wakeup | Yes | Yes | OFF |
  380. | RTC Wakeup | Yes | Yes | Yes |
  381. | USB remote wakeup | Yes | No1 | No |
  382. | Other wakeup source | Yes | No2 | No |
  383. | WAKEUPMIX | ON | OFF3 | OFF |
  384. | MLMIX | ON | OFF | OFF |
  385. | NICMIX | ON as needed | OFF | OFF |
  386.  
  387. | Mode | Supply | Voltage (V) | Power (mW)1 |
  388. |------|---------------|-------------|-------------|
  389. | BBSM | NVCC_BBSM_1P8 | 1.8 | 0.14 |
  390.  
  391. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  392. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  393. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  394.  
  395. | | Table 22. Chip power in different LP modes continued | | | | |
  396. |--|------------------------------------------------------|--|--|--|--|
  397. |--|------------------------------------------------------|--|--|--|--|
  398.  
  399. | Mode | Supply | Voltage (V) | Power (mW)1 |
  400. |---------|---------------------|-------------|-------------|
  401. | SUSPEND | NVCC_GPIO, NVCC_SD2 | 3.3 | 2.65 |
  402. | | NVCC_WAKEUP2 | 1.8 | 1.20 |
  403. | | VDDQ_DDR | 0.6 | < 0.01 |
  404. | | VDD2_DDR | 1.1 | 0.25 |
  405. | | VDD_ANA*_1P8 | 1.8 | 1.85 |
  406. | | VDD_ANA_0P8 | 0.8 | 0.40 |
  407. | | VDD_MIPI_0P8 | 0.8 | 0.65 |
  408. | | VDD_USB_0P8 | 0.8 | 0.45 |
  409. | | VDD_USB_3P3 | 3.3 | 0.25 |
  410. | | VDD_SOC | 0.65 | 7.40 |
  411. | | Total3 | — | 15.1 |
  412.  
  413. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  414. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  415. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  416.  
  417. | PLL type | Parameter | Value | |
  418. |------------|--------------------|-------------------------------|--|
  419. | AUDIO_PLL1 | Clock output range | Up to 650 MHz | |
  420. | | Reference clock | 24 MHz | |
  421. | | Lock time | 50 µs | |
  422. | | Jitter | ±1% of output period, ≥ 50 ps | |
  423. | VIDEO_PLL1 | Clock output range | Up to 594 MHz | |
  424. | | Reference clock | 24 MHz | |
  425. | | Lock time | 50 µs | |
  426. | SYS_PLL1 | Clock output range | 312.5 MHz — 1 GHz | |
  427. | | Reference clock | 24 MHz | |
  428. | | Lock time | 70 µs | |
  429. | ARM_PLL | Clock output range | 800 MHz — 1700 MHz | |
  430. | | Reference clock | 24 MHz | |
  431. | | Lock time | 70 µs | |
  432. | DRAM_PLL1 | Clock output range | 400 MHz — 1000 MHz | |
  433. | | Reference clock | 24 MHz | |
  434. | | Lock time | 50 µs | |
  435.  
  436. | Parameter | Symbol | Test Conditions | Min | Typ | Max | Unit |
  437. |---------------------------|-------------|---------------------------------------------------|-------------------|-----|----------|------|
  438. | High-level output voltage | VOH (1.8 V) | DS =1, IOH = 1.1 mA | 0.8 x | — | NVCC_xxx | V |
  439. | | | DS=6, IOH = 6.6 mA | NVCC_xxx | | | |
  440. | | VOH (3.3 V) | DS =1, IOH = 2 mA | 0.8 x | — | NVCC_xxx | V |
  441. | | | DS=6, IOH = 12 mA | NVCC_xxx | | | |
  442. | Low-level output voltage | VOL (1.8 V) | DS =1, IOL = 1.1 mA | 0 | — | 0.2 x | V |
  443. | | | DS=6, IOL = 6.6 mA | | | NVCC_xxx | |
  444. | | VOL (3.3 V) | DS =1, IOL = 2 mA | 0 | — | 0.2 x | V |
  445. | | | DS=6, IOL = 12 mA | | | NVCC_xxx | |
  446. | Low-level input voltage | VIL | NVCC_xxx = 1.65 - 3.465 V; Temp | 0 | — | 0.3 x | V |
  447. | | | = -40 to 125°C | | | NVCC_xxx | |
  448. | High-level input voltage | VIH | NVCC_xxx = 1.65 - 3.465 V;<br>Temp = -40 to 125°C | 0.7 x<br>NVCC_xxx | — | NVCC_xxx | V |
  449. | Pull-down resistor | Rpd3.3v | NVCC_xxx = 3.0 - 3.465 V; Temp = | 24 | 43 | 87 | KΩ |
  450. | Pull-up resistor | Rpu3.3v | -40 to 125°C | 18 | 37 | 72 | KΩ |
  451. | Pull-down resistor | Rpd1.8v | NVCC_xxx = 1.65 - 1.95 V; Temp<br>= -40 to 125°C | 13 | 23 | 48 | KΩ |
  452. | Pull-up resistor | Rpu1.8v | | 12 | 22 | 49 | KΩ |
  453.  
  454. | Parameter | Symbol | Condition | Min | Max | Unit |
  455. |--------------|--------|------------------------------------------------------------------------|-----|-----|------|
  456. | Leakage high | IIH | Non-PHY I/O, 1.65 V - 3.465 V, Temp =<br>-40°C to 125°C pad = VDDIO1 | -5 | 5 | µA |
  457. | Leakage low | IIL | Non-PHY I/O, 1.65 V - 3.465 V, Temp =<br>-40°C to 125°C pad = VSS1 | -5 | 5 | |
  458.  
  459. | Parameter | Symbol | Test Conditions | Min | Typ | Max | Unit |
  460. |----------------------------------|----------|------------------------------------------|-------|-----|-------|------|
  461. | Output<br>Differential Voltage | VOD | Rload = 100 Ω between Pad P and<br>Pad N | 250 | 350 | 450 | mV |
  462. | Output High Voltage | VOH | Rload = 100 Ω between Pad P and<br>Pad N | 1.25 | — | 1.6 | V |
  463. | Output Low Voltage | VOL | Rload = 100 Ω between Pad P and<br>Pad N | 0.9 | — | 1.25 | V |
  464. | Offset common<br>mode Voltage | VCM | — | 1.125 | 1.2 | 1.375 | V |
  465. | Tri-state I/O<br>supply current | Icc-ovdd | VIN=OVDD or 0 | 0.016 | | 1700 | |
  466. | Tri-state core<br>supply current | Icc-vddi | VIN=VDDI or 0 | — | | 1500 | nA |
  467. | | | VIN=OVDD or 0 | | | | |
  468. | Power Supply current | Icc | Rload=100 Ω | — | | 5 | mA |
  469.  
  470. | Symbol | Description | Min | Typ | Max | Unit | Condition |
  471. |--------|--------------|------|-----|------|------|-------------------------------------------------------------------------------------------|
  472. | tR | TX rise time | 3950 | — | 5950 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x1 |
  473. | tF | TX fall time | 4140 | — | 5600 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x1 |
  474. | tR | TX rise time | 1890 | — | 2820 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x2 |
  475. | tF | TX fall time | 1790 | — | 2560 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x2 |
  476. | tR | TX rise time | 675 | — | 1950 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x3 |
  477. | tF | TX fall time | 584 | — | 1730 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x3 |
  478. | tR | TX rise time | 521 | — | 1320 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x4 |
  479. | tF | TX fall time | 442 | — | 748 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x4 |
  480. | tR | TX rise time | 454 | — | 742 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x5 |
  481.  
  482. | | | | | | | Table 27. General purpose I/O (GPIO) AC parameterscontinued |
  483. |--|--|--|--|--|--|-------------------------------------------------------------|
  484. |--|--|--|--|--|--|-------------------------------------------------------------|
  485.  
  486. | Symbol | Description | Min | Typ | Max | Unit | Condition |
  487. |--------|--------------|------|-----|------|------|-------------------------------------------------------------------------------------------|
  488. | tF | TX fall time | 380 | — | 554 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x5 |
  489. | tR | TX rise time | 419 | — | 639 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x6 |
  490. | tF | TX fall time | 349 | — | 506 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x6 |
  491. | tR | TX rise time | 4030 | — | 5790 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x1 |
  492. | tF | TX fall time | 4410 | — | 6290 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x1 |
  493. | tR | TX rise time | 1870 | — | 2950 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(1.62 V, 1.8 V, 1.98 V),<br>Drive strength x2 |
  494. | tF | TX fall time | 1900 | — | 3310 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x2 |
  495. | tR | TX rise time | 774 | — | 1930 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x3 |
  496. | tF | TX fall time | 719 | — | 2070 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x3 |
  497. | tR | TX rise time | 598 | — | 1360 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x4 |
  498. | tF | TX fall time | 490 | — | 1590 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x4 |
  499.  
  500. | Symbol | Description | Min | Typ | Max | Unit | Condition |
  501. |--------|--------------|-----|-----|------|------|-----------------------------------------------------------------------------------------|
  502. | tR | TX rise time | 543 | — | 1040 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x5 |
  503. | tF | TX fall time | 401 | — | 1160 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x5 |
  504. | tR | TX rise time | 505 | — | 887 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x6 |
  505. | tF | TX fall time | 356 | — | 747 | ps | Slew rate FSEL1 =<br>11b, Fast Slew Rate<br>(3 V, 3.3 V, 3.465 V),<br>Drive strength x6 |
  506.  
  507. | Parameter | Symbol | Test Conditions | Min | Тур | Max | Unit | |
  508. |------------------------------------------|-------------------|---------------------------------------|-------|----------|------|------------------|--|
  509. | Lane skew $^{1}$ | $t_{\text{SKew}}$ | $\text{Rload} = 100 \ \Omega$ | | $0.25^2$ | | ns | |
  510. | Transition Low to High time <sup>3</sup> | $t_{\text{TLH}}$ | $\text{Cload} = 2 \text{ pF}$ | | | 0.3 | Unit<br>Interval | |
  511. | Transition High to Low time | $t_{\text{THL}}$ | | | | 0.3 | $(UI)^4$ | |
  512. | Operating data rate $5$ | f | | | | 560 | Mbps | |
  513. | Offset peak to peak voltage imbalance | $V_{\text{ospp}}$ | | | | 150 | mV | |
  514. | Tri-state I/O supply current | Icc-ovdd | VIN=OVDD or 0 | 0.016 | | 1700 | nА | |
  515. | Tri-state core supply current | Icc-vddi | $\text{VIN=VDDI}$ or 0 | | | 1500 | | |
  516. | Power Supply current | Icc | $VIN=OVDD$ or 0<br>Rload=100 $\Omega$ | | | 5 | mA | |
  517.  
  518. | ID | Parameter | Min | Max | Unit |
  519. |-----|-----------------------------------------------------|-----|-----|-----------------|
  520. | CC1 | Duration of POR_B to be qualified as valid. | 1 | — | RTC_XTALI cycle |
  521. | | Note: POR_B rise/fall times must be 400 µs or less. | | | |
  522.  
  523. | ID | Parameter | Min | Max | Unit |
  524. |-----|-------------------------------|-----|-----|-----------------|
  525. | CC3 | Duration of WDOG1_B Assertion | 1 | — | RTC_XTALI cycle |
  526.  
  527. | | Parameter | All Frequencies | | |
  528. |------|------------------------------------------------|-----------------|-----|------|
  529. | ID | | Min | Max | Unit |
  530. | SJ0 | JTAG_TCK frequency of operation3,4 | — | 50 | MHz |
  531. | SJ1 | JTAG_TCK cycle time in crystal mode | 20 | — | ns |
  532. | SJ2 | 5<br>JTAG_TCK clock pulse width measured at VM | 10 | — | ns |
  533. | SJ3 | JTAG_TCK rise and fall times | — | 3 | ns |
  534. | SJ4 | Boundary scan input data set-up time | 15 | — | ns |
  535. | SJ5 | Boundary scan input data hold time | 15 | — | ns |
  536. | SJ6 | JTAG_TCK low to output data valid | — | 600 | ns |
  537. | SJ7 | JTAG_TCK low to output high impedance | — | 600 | ns |
  538. | SJ8 | JTAG_TMS, JTAG_TDI data set-up time | 5 | — | ns |
  539. | SJ9 | JTAG_TMS, JTAG_TDI data hold time | 5 | — | ns |
  540. | SJ10 | JTAG_TCK low to JTAG_TDO data valid | — | 14 | ns |
  541. | SJ11 | JTAG_TCK low to JTAG_TDO high impedance | — | 14 | ns |
  542. | SJ14 | JTAG_TCK low to JTAG_TDO data invalid | 1 | — | ns |
  543.  
  544. | Symbol | Description | Min | Max | Unit |
  545. |--------|----------------------------|-----|-----|------|
  546. | S0 | SWD_CLK frequency | — | 50 | MHz |
  547. | S1 | SWD_CLK cycle time | 20 | — | ns |
  548. | S2 | SWD_CLK pulse width | 10 | — | ns |
  549. | S3 | Input data setup time | 5 | — | ns |
  550. | S4 | Input data hold time | 5 | — | ns |
  551. | S5 | Output data valid time | — | 14 | ns |
  552. | S6 | Output high impedance time | — | 14 | ns |
  553. | S7 | Output data invalid time | 0 | — | ns |
  554.  
  555. | Product Data Sheet |
  556. |--------------------|
  557.  
  558. | Parameter | LPDDR4/LPDDR4X |
  559. |-----------------------------|----------------|
  560. | Number of Controllers | 1 |
  561. | Number of Channels | 1 |
  562. | Number of Chip Selects | 2 |
  563. | Bus Width | 16-bit |
  564. | Maximum supported data rate | |
  565. | • Low drive mode | 1866 MT/s |
  566. | • Nominal drive mode | 2880 MT/s |
  567. | • Overdrive mode | 3733 MT/s1 |
  568.  
  569. | Symbol | Parameter | Min | Typ | Max | Unit |
  570. |------------------|----------------------------------------------------------------|-----|-----|------|------|
  571. | VCMTX1 | High Speed Transmit Static Common Mode Voltage | 150 | 200 | 250 | mV |
  572. | ΔVCMTX <br>(1,0) | VCMTX mismatch when Output is Differential-1 or Differential-0 | — | — | 5 | mV |
  573. | 1<br> VOD | High Speed Transmit Differential Voltage | 140 | 200 | 270 | mV |
  574. | ΔVOD | VOD mismatch when Output is Differential-1 or Differential-0 | — | — | 14 | mV |
  575. | VOHHS1 | High Speed Output High Voltage | — | — | 360 | mV |
  576. | ZOS | Single Ended Output Impedance | 40 | 50 | 62.5 | Ω |
  577. | ΔZOS | Single Ended Output Impedance Mismatch | — | — | 10 | % |
  578.  
  579. | Symbol | Parameter | Min | Typ | Max | Unit |
  580. |----------------|-------------------------------------------|-----|-----|-----------|--------|
  581. | ΔVCMTX(HF) | Common-level variations above 450 MHz | — | — | 15 | mVRMS |
  582. | ΔVCMTX(LF) | Common-level variation between 50-450 MHz | — | — | 25 | mVPEAK |
  583. | 1<br>tR and tF | Rise Time and Fall Time (20% to 80%) | 100 | — | 0.35 x UI | ps |
  584.  
  585. | Symbol | Parameter | Min | Typ | Max | Unit |
  586. |---------|-------------------------------------------|-----|-----|-----|------|
  587. | VIDTH | Differential input high voltage threshold | — | — | 70 | mV |
  588. | VIDTL | Differential input low voltage threshold | -70 | — | — | mV |
  589. | VIHHS | Single ended input high voltage | — | — | 460 | mV |
  590. | VILHS | Single ended input low voltage | -40 | — | — | mV |
  591. | VCMRXDC | Input common mode voltage | 70 | — | 330 | mV |
  592. | ZID | Differential input impedance | 80 | 100 | 125 | Ω |
  593.  
  594. | Symbol | Parameter | Min | Typ | Max | Unit |
  595. |-------------|-------------------------------------------------|-----|-----|-----|------|
  596. | ΔVCMRX(HF)1 | Common mode interference beyond 450 MHz | — | — | 50 | mV |
  597. | ΔVCMRX(LF) | Common mode interference between 50 and 450 MHz | -25 | — | 25 | mV |
  598. | CCM | Common mode termination | — | — | 60 | pF |
  599.  
  600. | Symbol | Parameter | Min | Typ | Max | Unit |
  601. |--------|-------------------------------------------|-----|-----|-----|------|
  602. | VOH1 | Thevenin Output High Level | 1.1 | 1.2 | 1.3 | V |
  603. | VOL | Thevenin Output Low Level | –50 | — | 50 | mV |
  604. | ZOLP2 | Output Impedance of Low Power Transmitter | 110 | — | — | Ω |
  605.  
  606. | Symbol | Parameter | Min | Typ | Max | Unit |
  607. |------------------|---------------------------------------------------------------------------------------------------------------------------------|-----|-----|-----|-------|
  608. | TRLP/TFLP1 | 15% to 85% Rise Time and Fall Time | — | — | 25 | ns |
  609. | TREOT1,2,3 | 30% to 85% Rise Time and Fall Time | — | — | 35 | ns |
  610. | TLP-PULSE<br>TX4 | Pulse width of the LP exclusive-OR clock: First LP exclusive-OR clock<br>pulse after Stop state or last pulse before Stop state | 40 | — | — | ns |
  611. | | Pulse width of the LP exclusive-OR clock: All other pulses | 20 | — | — | ns |
  612. | TLP-PER-TX | Period of the LP exclusive-OR clock | 90 | — | — | ns |
  613. | δV/δtSR1,5,6,7 | Slew Rate @ CLOAD= 0 pF | 25 | — | 500 | mV/ns |
  614. | | Slew Rate @ CLOAD= 5 pF | 25 | — | 300 | mV/ns |
  615. | | Slew Rate @ CLOAD= 20 pF | 25 | — | 250 | mV/ns |
  616. | | Slew Rate @ CLOAD= 70 pF | 25 | — | 150 | mV/ns |
  617. | CLOAD | Load Capacitance | 0 | — | 70 | pF |
  618.  
  619. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  620. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  621. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  622.  
  623. | Symbol | Parameter | Min | Typ | Max | Unit |
  624. |----------|-----------------------------------------|-----|-----|-----|------|
  625. | VIH | Logic 1 input voltage | 740 | — | — | mV |
  626. | VIL | Logic 0 input voltage, not in ULP state | — | — | 550 | mV |
  627. | VIL-ULPS | Logic 0 input voltage, ULP state | — | — | 300 | mV |
  628. | VHYST | Input hysteresis | 25 | — | — | mV |
  629.  
  630. | Symbol | Parameter | Min | Typ | Max | Unit |
  631. |-----------|------------------------------|-----|-----|-----|------|
  632. | eSPIKE1,2 | Input pulse rejection | — | — | 300 | V.ps |
  633. | TMIN-RX3 | Minimum pulse width response | 20 | — | — | ns |
  634. | VINT | Peak Interference amplitude | — | — | 200 | mV |
  635. | fINT | Interference frequency | 450 | — | — | MHz |
  636.  
  637. | Symbol | Parameter | Min | Typ | Max | Unit |
  638. |--------|------------------------------|-----|-----|-----|------|
  639. | VIHCD | Logic 1 contention threshold | 450 | — | — | mV |
  640. | VILCD | Logic 0 contention threshold | — | — | 200 | mV |
  641.  
  642. | ID | Parameter | Symbol | Min | Max | Unit |
  643. |----|---------------------------------------------------------------------|----------------|------|-----|------|
  644. | L1 | LCD pixel clock frequency3 | tCLK(LCD) | — | 80 | MHz |
  645. | L2 | LCD pixel clock high (falling edge capture) | tCLKH(LCD) | 5 | — | ns |
  646. | L3 | LCD pixel clock low (rising edge capture) | tCLKL(LCD) | 5 | — | ns |
  647. | L4 | LCD pixel clock high to data valid (falling edge capture) | td(CLKH-DV) | -1.5 | 1.5 | ns |
  648. | L5 | LCD pixel clock low to data valid (rising edge capture) | td(CLKL-DV) | -1.5 | 1.5 | ns |
  649. | L6 | LCD pixel clock high to control signal valid (falling edge capture) | td(CLKH-CTRLV) | -1.5 | 1.5 | ns |
  650. | L7 | LCD pixel clock low to control signal valid (rising edge capture) | td(CLKL-CTRLV) | -1.5 | 1.5 | ns |
  651.  
  652. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  653. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  654. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  655.  
  656. | Num | Characteristic | Min | Max | Unit |
  657. |-----|--------------------------------------------|-----|-----|-------------|
  658. | S1 | SAI_MCLK cycle time | 20 | — | ns |
  659. | S2 | SAI_MCLK pulse width high/low | 40% | 60% | MCLK period |
  660. | S3 | SAI_BCLK cycle time | 20 | — | ns |
  661. | S4 | SAI_BCLK pulse width high/low | 40% | 60% | BCLK period |
  662. | S5 | SAI_BCLK to SAI_FS output valid | — | 3 | ns |
  663. | S6 | SAI_BCLK to SAI_FS output invalid | -2 | — | ns |
  664. | S7 | SAI_BCLK to SAI_TXD valid | — | 3 | ns |
  665. | S8 | SAI_BCLK to SAI_TXD invalid | -2 | — | ns |
  666. | S9 | SAI_RXD/SAI_FS input setup before SAI_BCLK | 3 | — | ns |
  667. | S10 | SAI_RXD/SAI_FS input hold after SAI_BCLK | 2 | — | ns |
  668.  
  669. | Num | Characteristic | Min | Max | Unit |
  670. |-----|--------------------------------------------|-----|-----|-------------|
  671. | S1 | SAI_MCLK cycle time | 40 | — | ns |
  672. | S2 | SAI_MCLK pulse width high/low | 40% | 60% | MCLK period |
  673. | S3 | SAI_BCLK cycle time | 40 | — | ns |
  674. | S4 | SAI_BCLK pulse width high/low | 40% | 60% | BCLK period |
  675. | S5 | SAI_BCLK to SAI_FS output valid | — | 3 | ns |
  676. | S6 | SAI_BCLK to SAI_FS output invalid | -2 | — | ns |
  677. | S7 | SAI_BCLK to SAI_TXD valid | — | 3 | ns |
  678. | S8 | SAI_BCLK to SAI_TXD invalid | -2 | — | ns |
  679. | S9 | SAI_RXD/SAI_FS input setup before SAI_BCLK | 8 | — | ns |
  680. | S10 | SAI_RXD/SAI_FS input hold after SAI_BCLK | 0 | — | ns |
  681.  
  682. | Num | Characteristic | Min | Max | Unit |
  683. |-----|-------------------------------------------------|-----|-----|-------------|
  684. | S11 | SAI_BCLK cycle time (input) | 40 | — | ns |
  685. | S12 | SAI_BCLK pulse width high/low (input) | 40% | 60% | BCLK period |
  686. | S13 | SAI_FS input setup before SAI_BCLK | 3 | — | ns |
  687. | S14 | SAI_FS input hold after SAI_BCLK | 2 | — | ns |
  688. | S15 | SAI_BCLK to SAI_TXD/SAI_FS output valid | — | 9 | ns |
  689. | S16 | SAI_BCLK to SAI_TXD/SAI_FS output invalid | 0 | — | ns |
  690. | S17 | SAI_RXD setup before SAI_BCLK | 3 | — | ns |
  691. | S18 | SAI_RXD hold after SAI_BCLK | 2 | — | ns |
  692. | S19 | SAI_FS input assertion to SAI_TXD output valid3 | — | 25 | ns |
  693.  
  694. | Parameter | | Timing Parameter Range | | |
  695. |----------------------------------------------------|--------|------------------------|------|------|
  696. | | | Min | Max | Unit |
  697. | SPDIF_IN Skew: asynchronous inputs, no specs apply | — | — | 0.7 | ns |
  698. | SPDIF_OUT output (Load = 50 pf) | — | — | 1.5 | ns |
  699. | • Skew | — | — | 24.2 | |
  700. | • Transition rising | — | — | 31.3 | |
  701. | • Transition falling | | | | |
  702. | SPDIF_OUT output (Load = 30 pf) | — | — | 1.5 | ns |
  703. | • Skew | — | — | 13.6 | |
  704. | • Transition rising | — | — | 18.0 | |
  705. | • Transition falling | | | | |
  706. | Modulating Rx clock (SPDIF_SR_CLK) period | srckp | 40.0 | — | ns |
  707. | SPDIF_SR_CLK high period | srckph | 16.0 | — | ns |
  708.  
  709. | Parameter | | Timing Parameter Range | | |
  710. |-------------------------------------------|---------|------------------------|-----|------|
  711. | | | Min | Max | Unit |
  712. | SPDIF_SR_CLK low period | srckpl | 16.0 | — | ns |
  713. | Modulating Tx clock (SPDIF_ST_CLK) period | stclkp | 40.0 | — | ns |
  714. | SPDIF_ST_CLK high period | stclkph | 16.0 | — | ns |
  715. | SPDIF_ST_CLK low period | stclkpl | 16.0 | — | ns |
  716.  
  717. | Parameter | Value |
  718. |-----------|--------------------------------------------------------------------|
  719. | trs, tfs | floor (kxCLKDIV) - 1<br><=<br>@ (moduleNickname)_CLK_ROOTrate<br>1 |
  720. | trh, tfh | ≥ 0 |
  721.  
  722. | Quality factor | K factor |
  723. |------------------------------------|----------|
  724. | High Quality | 1/2 |
  725. | Medium Quality, Very Low Quality 0 | |
  726. | Low Quality, Very Low Quality 1 | 2 |
  727. | Very Low Quality 2 | 4 |
  728.  
  729. | Symbol | Description | Min | Тур | Max | Unit |
  730. |----------|---------------------------------------------------------|-----|--------|------|------|
  731. | fmclk '' | Bit clock is used to generate<br><sup>1</sup> the mclk. | | 24.576 | 66.5 | MHz |
  732.  
  733. | MX93AEC | All information provided in this document is subject to legal disclaimers. | 2025 NXP B.V. All rights reserved. |
  734. |--------------------|----------------------------------------------------------------------------|------------------------------------|
  735. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  736. | | | . |
  737.  
  738. | Symbol | Description | Min | Typ | Max | Unit | Notes |
  739. |-------------|-----------------------------------------------------------------------------|----------------------------------|-----|------|-------|---------|
  740. | VADIN | Input voltage | VGND | — | VDDA | V | 1 |
  741. | fAD_CK | ADC clock frequency | 20 | — | 80 | MHz | — |
  742. | Csample | Sample cycles | 5.5 | — | — | Cycle | — |
  743. | Ccompare | Fixed compare cycles | — | 58 | — | Cycle | — |
  744. | Cconversion | Conversion cycles | Cconversion = Csample + Ccompare | | | Cycle | — |
  745. | CAD_INPUT | ADC input capacitance | — | — | 7 | pF | 2 |
  746. | RAD_INPUT | ADC input series resistance | — | — | 1.25 | KΩ | — |
  747. | DNL | ADC differential nonlinearity | — | ±2 | — | LSB | 3 |
  748. | INL | ADC integral nonlinearity | — | ±6 | — | LSB | 3 |
  749. | RAS | Analog source resistance | — | — | 5 | KΩ | — |
  750. | Bandgap | Output voltage ready time<br>for bandgap | — | 1 | — | µs | 4 |
  751. | ENOB | Effective number of bits:<br>Single-ended mode (11 x 11<br>mm package, PWM) | — | 9.8 | — | bit | 5,6,7,8 |
  752. | | Effective number of bits:<br>Single-ended mode (11 x 11<br>mm package, PFM) | — | 9.4 | — | | |
  753. | | Effective number of bits:<br>Single-ended mode (9 x 9 mm<br>package, PWM) | — | 9.2 | — | | |
  754. | | Effective number of bits:<br>Single-ended mode (9 x 9 mm<br>package, PFM) | — | 8.5 | — | | |
  755.  
  756. | Symbol | Description | Min | Typ | Max | Unit | Notes |
  757. |--------|-----------------------------------------------------------------------------|-----|------|-----|------|-------|
  758. | | Effective number of bits:<br>Single-ended mode (14 x 14<br>mm package, PWM) | — | 10.5 | — | | |
  759. | | Effective number of bits:<br>Single-ended mode (14 x 14<br>mm package, PFM) | — | 10.1 | — | | |
  760.  
  761. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  762. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  763. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  764.  
  765. | Table 52. SD3.0/eMMC5.1 (SDR) interface timing specification1,2 | | | |
  766. |-----------------------------------------------------------------|--|--|--|
  767. | | | | |
  768.  
  769. | ID | Parameter | Symbols | Min | Max | Unit | |
  770. |-----|---------------------------------------------------------------|---------|------|-------|------|--|
  771. | | Card Input Clock | | | | | |
  772. | SD1 | Clock Frequency (Low Speed) | fPP3 | 0 | 400 | kHz | |
  773. | | Clock Frequency (SD/SDIO Full Speed/High Speed) | fPP4 | 0 | 25/50 | MHz | |
  774. | | Clock Frequency (MMC Full Speed/High Speed) | fPP5 | 0 | 20/52 | MHz | |
  775. | | Clock Frequency (Identification Mode) | fOD | 100 | 400 | kHz | |
  776. | SD2 | Clock Low Time | tWL | 7 | — | ns | |
  777. | SD3 | Clock High Time | tWH | 7 | — | ns | |
  778. | SD4 | Clock Rise Time | tTLH | — | 3 | ns | |
  779. | SD5 | Clock Fall Time<br>tTHL<br>—<br>3 | | | | | |
  780. | | uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK) | | | | | |
  781. | SD6 | uSDHC Output Delay | tOD | -6.6 | 3.6 | ns | |
  782. | | uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK) | | | | | |
  783. | SD7 | uSDHC Input Setup Time | tISU | 2.5 | — | ns | |
  784. | SD8 | uSDHC Input Hold Time6 | tIH | 1.5 | — | ns | |
  785.  
  786. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  787. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  788. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  789.  
  790. | Table 53. SD3.0/eMMC5.1 (DDR) interface timing specification1,2 | | | | | | | |
  791. |-----------------------------------------------------------------|--|--|--|--|--|--|--|
  792. |-----------------------------------------------------------------|--|--|--|--|--|--|--|
  793.  
  794. | ID | Parameter | Symbols | Min | Max | Unit | | | | |
  795. |-----------------------------------------------------------------|-------------------------------|---------|-----|-----|------|--|--|--|--|
  796. | | Card Input Clock | | | | | | | | |
  797. | SD1 | Clock Frequency (eMMC5.1 DDR) | fPP | 0 | 52 | MHz | | | | |
  798. | SD1 | Clock Frequency (SD3.0 DDR) | fPP | 0 | 50 | MHz | | | | |
  799. | uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK) | | | | | | | | | |
  800. | SD2 | uSDHC Output Delay | 6.8 | ns | | | | | | |
  801. | uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK) | | | | | | | | | |
  802. | SD3 | uSDHC Input Setup Time | tISU | 2.4 | — | ns | | | | |
  803. | SD4 | uSDHC Input Hold Time | tIH | 1.5 | — | ns | | | | |
  804.  
  805. | | | | | Table 54. HS400 interface timing specification (Nominal and Overdrive mode)1,2 | | | | | |
  806. |--|--|--|--|--------------------------------------------------------------------------------|--|--|--|--|--|
  807. |--|--|--|--|--------------------------------------------------------------------------------|--|--|--|--|--|
  808.  
  809. | ID | Parameter | Symbols | Min | Max | Unit | | | |
  810. |----------------------------------------------------|--------------------------------------|------------------|------|------|------|--|--|--|
  811. | | | Card Input Clock | | | | | | |
  812. | SD1 | Clock frequency | fPP | 0 | 200 | MHz | | | |
  813. | SD2 | Clock low time | tCL | 2.2 | — | ns | | | |
  814. | SD3 | Clock high time | tCH | 2.2 | — | ns | | | |
  815. | uSDHC Output/Card Inputs DAT (Reference to SCK) | | | | | | | | |
  816. | SD4 | Output skew from Data of edge of SCK | tOSkew1 | 0.45 | — | ns | | | |
  817. | SD5 | Output skew from SCK to Data of edge | tOSkew2 | 0.45 | — | ns | | | |
  818. | uSDHC Input/Card Outputs DAT (Reference to Strobe) | | | | | | | | |
  819. | SD6 | uSDHC input skew | tRQ | — | 0.45 | ns | | | |
  820. | SD7 | uSDHC hold skew | tRQH | — | 0.45 | ns | | | |
  821.  
  822. | Table 55. HS400 interface timing specification (Low drive mode)1,2 | |
  823. |--------------------------------------------------------------------|--|
  824. |--------------------------------------------------------------------|--|
  825.  
  826. | ID | Parameter | Symbols | Min | Max | Unit | | | |
  827. |-----|------------------|---------|-----|-----|------|--|--|--|
  828. | | Card Input Clock | | | | | | | |
  829. | SD1 | Clock frequency | fPP | 0 | 133 | MHz | | | |
  830.  
  831. | | Table 55. HS400 interface timing specification (Low drive mode)1,2 | | | | continued |
  832. |--|--------------------------------------------------------------------|--|--|--|-----------|
  833. |--|--------------------------------------------------------------------|--|--|--|-----------|
  834.  
  835. | ID | Parameter | Symbols | Min | Max | Unit | | | | |
  836. |----------------------------------------------------|--------------------------------------------|---------|------|------|------|--|--|--|--|
  837. | SD2 | Clock low time | tCL | 3.3 | — | ns | | | | |
  838. | SD3 | Clock high time | tCH | 3.3 | — | ns | | | | |
  839. | uSDHC Output/Card Inputs DAT (Reference to SCK) | | | | | | | | | |
  840. | SD4 | Output skew from data of edge of SCK | tOSkew1 | 0.45 | — | ns | | | | |
  841. | SD5 | Output skew from edge of SCk to data | tOSkew2 | 0.45 | — | ns | | | | |
  842. | uSDHC Input/Card Outputs DAT (Reference to Strobe) | | | | | | | | | |
  843. | SD6 | uSDHC input skew<br>tRQ<br>—<br>0.45<br>ns | | | | | | | | |
  844. | SD7 | uSDHC hold skew | tRQH | — | 0.45 | ns | | | | |
  845.  
  846. | | | Table 56. HS200 interface timing specification (Nominal and Overdrive mode)1,2 | | |
  847. |--|--|--------------------------------------------------------------------------------|--|--|
  848. | | | | | |
  849.  
  850. | ID | Parameter | Symbols | Min | Max | Unit |
  851. |-----|------------------------|---------|-----|-----|------|
  852. | | Card Input Clock | | | | |
  853. | SD1 | Clock Frequency Period | tCLK | 5.0 | — | ns |
  854. | SD2 | Clock Low Time | tCL | 2.2 | — | ns |
  855. | SD3 | Clock High Time | tCH | 2.2 | — | ns |
  856.  
  857. | ID | Parameter | Symbols | Min | Max | Unit | | | | |
  858. |-------------------------------------------------------------------------|-------------------------|---------|-----------------|-----|------|--|--|--|--|
  859. | uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK) | | | | | | | | | |
  860. | SD5 | uSDHC Output Delay | tOD | -1.6 | 1 | ns | | | | |
  861. | uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)3 | | | | | | | | | |
  862. | SD8 | uSDHC Input Data Window | tODW | 0.475 x<br>tCLK | — | ns | | | | |
  863.  
  864. | ID | Parameter | Symbols | Min | Max | Unit | | | | | |
  865. |-------------------------------------------------------------------------|------------------------------------------------------------------------|---------|-----------------|-----|------|--|--|--|--|--|
  866. | | Card Input Clock | | | | | | | | | |
  867. | SD1 | Clock Frequency Period | tCLK | 7.5 | — | ns | | | | | |
  868. | SD2 | Clock Low Time | tCL | 3.3 | — | ns | | | | | |
  869. | SD3 | Clock High Time | tCH | 3.3 | — | ns | | | | | |
  870. | | uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK) | | | | | | | | | |
  871. | SD5 | uSDHC Output Delay | tOD | -1.6 | 1 | ns | | | | | |
  872. | uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)3 | | | | | | | | | | |
  873. | SD8 | uSDHC Input Data Window | tODW | 0.475 x<br>tCLK | — | ns | | | | | |
  874.  
  875. | ID | Parameter | Symbols | Min | Max | Unit | | | | | |
  876. |-----|--------------------------------------------------------------------------|---------|------------|-----|------|--|--|--|--|--|
  877. | | Card Input Clock | | | | | | | | | |
  878. | SD1 | Clock Frequency Period | tCLK | 5 | — | ns | | | | | |
  879. | SD2 | Clock Low Time | tCL | 2.2 | — | ns | | | | | |
  880. | SD3 | Clock High Time | tCH | 2.2 | — | ns | | | | | |
  881. | | uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK) | | | | | | | | | |
  882. | SD4 | uSDHC Output Delay | tOD | -3 | 1 | ns | | | | | |
  883. | | uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK) | | | | | | | | | |
  884. | SD5 | uSDHC Output Delay | tOD | -1.6 | 1 | ns | | | | | |
  885. | | uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK) | | | | | | | | | |
  886. | SD6 | uSDHC Input Setup Time | tISU | 2.4 | — | ns | | | | | |
  887. | SD7 | uSDHC Input Hold Time | tIH | 1.5 | — | ns | | | | | |
  888. | | uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)3 | | | | | | | | | |
  889. | SD8 | uSDHC Input Data Window | tODW | 0.5 x tCLK | — | ns | | | | | |
  890.  
  891. | ID | Parameter | Min | Max | Unit | | | | | | |
  892. |------------------------------------------------------------------------|--------------------------------------------------------------------------|------|------------|------|----|--|--|--|--|--|
  893. | | Card Input Clock | | | | | | | | | |
  894. | SD1 | Clock Frequency Period | tCLK | 7.5 | — | ns | | | | | |
  895. | SD2 | Clock Low Time | tCL | 3.3 | — | ns | | | | | |
  896. | SD3 | Clock High Time | tCH | 3.3 | — | ns | | | | | |
  897. | uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK) | | | | | | | | | | |
  898. | SD4 | uSDHC Output Delay | tOD | -3 | 1 | ns | | | | | |
  899. | | uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK) | | | | | | | | | |
  900. | SD5 | uSDHC Output Delay | tOD | -1.6 | 1 | ns | | | | | |
  901. | | uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK) | | | | | | | | | |
  902. | SD6 | uSDHC Input Setup Time | tISU | 2.4 | — | ns | | | | | |
  903. | SD7 | uSDHC Input Hold Time | tIH | 1.5 | — | ns | | | | | |
  904. | | uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)3 | | | | | | | | | |
  905. | SD8 | uSDHC Input Data Window | tODW | 0.5 x tCLK | — | ns | | | | | |
  906.  
  907. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  908. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  909. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  910.  
  911. | Pad name | RGMII | Alt mode | RMII | Alt mode | Direction |
  912. |--------------|--------------|----------|---------------|----------|-----------|
  913. | ENET2_MDC | RGMII_MDC | Alt 0 | RMII_MDC | Alt 0 | O |
  914. | ENET2_MDIO | RGMII_MDIO | Alt 0 | RMII_MDIO | Alt 0 | I/O |
  915. | ENET2_TXC | RGMII_TXC | Alt 0 | RMII_TX_ER | Alt 1 | O |
  916. | ENET2_TX_CTL | RGMII_TX_CTL | Alt 0 | RMII_TX_EN | Alt 0 | O |
  917. | ENET2_TD0 | RGMII_TD0 | Alt 0 | RMII_TD0 | Alt 0 | O |
  918. | ENET2_TD1 | RGMII_TD1 | Alt 0 | RMII_TD1 | Alt 0 | O |
  919. | ENET2_TD2 | RGMII_TD2 | Alt 0 | RMII_REF_CLK2 | Alt 1 | I/O |
  920. | ENET2_TD3 | RGMII_TD3 | Alt 0 | — | Alt 0 | O |
  921. | ENET2_RXC | RGMII_RXC | Alt 0 | RMII_RX_ER | Alt 1 | I |
  922. | ENET2_RX_CTL | RGMII_RX_CTL | Alt 0 | RMII_CRS_DV | Alt 0 | I |
  923. | ENET2_RD0 | RGMII_RD0 | Alt 0 | RMII_RD0 | Alt 0 | I |
  924.  
  925. | Pad name | RGMII | Alt mode | RMII | Alt mode | Direction |
  926. |-----------|-----------|----------|----------|----------|-----------|
  927. | ENET2_RD1 | RGMII_RD1 | Alt 0 | RMII_RD1 | Alt 0 | I |
  928. | ENET2_RD2 | RGMII_RD2 | Alt 0 | — | Alt 0 | I |
  929. | ENET2_RD3 | RGMII_RD3 | Alt 0 | — | Alt 0 | I |
  930.  
  931. | ID | Characteristic | Min. | Max. | Unit |
  932. |-----|---------------------------------------------------------------------|------|------|------------------------|
  933. | M16 | ENET_CLK pulse width high | 35% | 65% | RMII_REF_CLK<br>period |
  934. | M17 | RMII_REF_CLK pulse width low | 35% | 65% | RMII_REF_CLK<br>period |
  935. | M18 | RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN invalid | 2 | — | ns |
  936. | M19 | RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN valid | — | 14 | ns |
  937. | M20 | ENET_RX_DATA[1:0], ENET_CRS_DV, ENET_RX_ER to<br>RMII_REF_CLK setup | 4 | — | ns |
  938. | M21 | RMII_REF_CLK to ENET_RX_DATA[1:0], ENET_CRS_DV,<br>ENET_RX_ER hold | 2 | — | ns |
  939.  
  940. | ID | Characteristic | Min. | Max. | Unit |
  941. |-----|-------------------------------------------------------------------------------|------|------|-----------------|
  942. | M10 | ENET_MDC falling edge to ENET_MDIO output invalid (min.<br>propagation delay) | -1.5 | — | ns |
  943. | M11 | ENET_MDC falling edge to ENET_MDIO output valid (max.<br>propagation delay) | — | 13 | ns |
  944. | M12 | ENET_MDIO (input) to ENET_MDC rising edge setup | 13 | — | ns |
  945. | M13 | ENET_MDIO (input) to ENET_MDC rising edge hold | 0 | — | ns |
  946. | M14 | ENET_MDC pulse width high | 40% | 60% | ENET_MDC period |
  947. | M15 | ENET_MDC pulse width low | 40% | 60% | ENET_MDC period |
  948.  
  949. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  950. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  951. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  952.  
  953. | Symbol | Description | Min. | Max. | Unit |
  954. |--------|------------------------------------------|------|------|------|
  955. | Tcyc | Clock cycle duration | 7.2 | 8.8 | ns |
  956. | TskewT | Data to clock output skew at transmitter | -500 | 500 | ps |
  957. | TskewR | Data to clock input skew at receiver | 1 | 2.6 | ns |
  958. | Duty_G | Duty cycle for Gigabit | 45 | 55 | % |
  959. | Duty_T | Duty cycle for 10/100T | 40 | 60 | % |
  960.  
  961. | Pad name | RGMII | Alt mode | RMII | Alt mode | Direction |
  962. |--------------|--------------|----------|---------------|----------|-----------|
  963. | ENET1_MDC | RGMII_MDC | Alt 0 | RMII_MDC | Alt 0 | O |
  964. | ENET1_MDIO | RGMII_MDIO | Alt 0 | RMII_MDIO | Alt 0 | I/O |
  965. | ENET1_TXC | RGMII_TXC | Alt 0 | RMII_TX_ER | Alt 1 | O |
  966. | ENET1_TX_CTL | RGMII_TX_CTL | Alt 0 | RMII_TX_EN | Alt 0 | O |
  967. | ENET1_TD0 | RGMII_TD0 | Alt 0 | RMII_TD0 | Alt 0 | O |
  968. | ENET1_TD1 | RGMII_TD1 | Alt 0 | RMII_TD1 | Alt 0 | O |
  969. | ENET1_TD2 | RGMII_TD2 | Alt 0 | RMII_REF_CLK2 | Alt 1 | I/O |
  970. | ENET1_TD3 | RGMII_TD3 | Alt 0 | — | Alt 0 | O |
  971. | ENET1_RXC | RGMII_RXC | Alt 0 | RMII_RX_ER | Alt 1 | I |
  972. | ENET1_RX_CTL | RGMII_RX_CTL | Alt 0 | RMII_CRS_DV | Alt 0 | I |
  973. | ENET1_RD0 | RGMII_RD0 | Alt 0 | RMII_RD0 | Alt 0 | I |
  974. | ENET1_RD1 | RGMII_RD1 | Alt 0 | RMII_RD1 | Alt 0 | I |
  975. | ENET1_RD2 | RGMII_RD2 | Alt 0 | — | Alt 0 | I |
  976. | ENET1_RD3 | RGMII_RD3 | Alt 0 | — | Alt 0 | I |
  977.  
  978. | ID | Characteristic | Min. | Max. | Unit |
  979. |-----|---------------------------------------------------------------------|------|------|------------------------|
  980. | M16 | ENET_CLK pulse width high | 35% | 65% | RMII_REF_CLK<br>period |
  981. | M17 | RMII_REF_CLK pulse width low | 35% | 65% | RMII_REF_CLK<br>period |
  982. | M18 | RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN invalid | 2 | — | ns |
  983. | M19 | RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN valid | — | 14 | ns |
  984. | M20 | ENET_RX_DATA[1:0], ENET_CRS_DV, ENET_RX_ER to<br>RMII_REF_CLK setup | 4 | — | ns |
  985. | M21 | RMII_REF_CLK to ENET_RX_DATA[1:0], ENET_CRS_DV,<br>ENET_RX_ER hold | 2 | — | ns |
  986.  
  987. | ID | Characteristic | Min. | Max. | Unit |
  988. |-----|-------------------------------------------------------------------------------|------|------|-----------------|
  989. | M10 | ENET_MDC falling edge to ENET_MDIO output invalid (min.<br>propagation delay) | -1.5 | — | ns |
  990. | M11 | ENET_MDC falling edge to ENET_MDIO output valid (max.<br>propagation delay) | — | 13 | ns |
  991. | M12 | ENET_MDIO (input) to ENET_MDC rising edge setup | 13 | — | ns |
  992. | M13 | ENET_MDIO (input) to ENET_MDC rising edge hold | 0 | — | ns |
  993. | M14 | ENET_MDC pulse width high | 40% | 60% | ENET_MDC period |
  994. | M15 | ENET_MDC pulse width low | 40% | 60% | ENET_MDC period |
  995.  
  996. | | | | | Table 67. RGMII signal switching specifications1,2,3,4 |
  997. |--|--|--|--|--------------------------------------------------------|
  998. |--|--|--|--|--------------------------------------------------------|
  999.  
  1000. | Symbol | Description | Min. | Max. | Unit |
  1001. |--------|------------------------------------------|------|------|------|
  1002. | Tcyc | Clock cycle duration | 7.2 | 8.8 | ns |
  1003. | TskewT | Data to clock output skew at transmitter | -500 | 500 | ps |
  1004. | TskewR | Data to clock input skew at receiver | 1 | 2.6 | ns |
  1005.  
  1006. | Symbol | Description | Min. | Max. | Unit |
  1007. |--------|------------------------|------|------|------|
  1008. | Duty_G | Duty cycle for Gigabit | 45 | 55 | % |
  1009. | Duty_T | Duty cycle for 10/100T | 40 | 60 | % |
  1010.  
  1011. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  1012. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  1013. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  1014.  
  1015. | Number | Symbol | Description | Min. | Max. | Units | Note |
  1016. |--------|--------|------------------------------|--------------|--------------|---------|------|
  1017. | 1 | fSCK | Frequency of LPSPI clock3 | — | 30 | MHz | 4 |
  1018. | | | | — | 60 | MHz | 5 |
  1019. | 2 | tSCK | SCK period | 2 x tperiph | — | ns | 6 |
  1020. | 3 | tLead | Enable lead time | 1 | — | tperiph | — |
  1021. | 4 | tLag | Enable lag time | 1 | — | tperiph | — |
  1022. | 5 | tWSCK | Clock (SCK) high or low time | tSCK / 2 - 3 | tSCK / 2 + 3 | ns | — |
  1023. | 6 | tSU | Data setup time (inputs) | 8 | — | ns | 7,8 |
  1024. | 7 | tHI | Data hold time (inputs) | 0 | — | ns | 7 |
  1025. | 8 | tV | Data valid (after SCK edge) | — | 2.5 | ns | — |
  1026. | 9 | tHO | Data hold time (outputs) | -2.5 | — | ns | — |
  1027.  
  1028. | Number | Symbol | Description | Min. | Max. | Units | Note |
  1029. |--------|-------------------|--------------------------|------------------------------|------|---------------------|------|
  1030. | | $f_{\text{SCK}}$ | Frequency of LPSPI clock | 0 | 30 | MHz | |
  1031. | 2 | $t_{\text{SCK}}$ | SCK period | $2 \times t_{\text{periph}}$ | | ns | |
  1032. | 3 | $t_{\text{Lead}}$ | Enable lead time | | | <sup>L</sup> periph | |
  1033.  
  1034. | Number | Symbol | Description | Min. | Max. | Units | Note |
  1035. |--------|--------|------------------------------|--------------|--------------|---------|------|
  1036. | 4 | tLag | Enable lag time | 1 | — | tperiph | — |
  1037. | 5 | tWSCK | Clock (SCK) high or low time | tSCK / 2 - 5 | tSCK / 2 + 5 | ns | — |
  1038. | 6 | tSU | Data setup time (inputs) | 3 | — | ns | — |
  1039. | 7 | tHI | Data hold time (inputs) | 3 | — | ns | — |
  1040. | 8 | ta | Peripheral access time | — | 20 | ns | 4 |
  1041. | 9 | tdis | Peripheral MISO disable time | — | 20 | ns | 5 |
  1042. | 10 | tV | Data valid (after SCK edge) | — | 8 | ns | 6 |
  1043. | 11 | tHO | Data hold time (outputs) | 0 | — | ns | — |
  1044.  
  1045. | able / U. LPIZC module timing parameters | | | | | | | | | |
  1046. |------------------------------------------|---------------------|---------------------------|-----|------|------|--|--|--|--|
  1047. | Symbol | Description | | Min | Max | Unit | | | | |
  1048. | $f_{SCL}$ | SCL clock frequency | Standard mode (Sm) | 0 | 100 | kHz | | | | |
  1049. | | | Fast mode (Fm) | 0 | 400 | | | | | |
  1050. | | | Fast mode Plus (Fm+) | 0 | 1000 | | | | | |
  1051. | | | High speed mode (Hs-mode) | 0 | 3400 | | | | | |
  1052.  
  1053. | Symbol | Description | Min | Typ | Max | Unit | Condition |
  1054. |--------|----------------------------------------------------|------|------|-------------------------------------------|------|-------------------------------------------------------|
  1055. | fSCL | SCL Clock Frequency | 0.01 | 12.5 | 12.9 | MHz | FSCL = 1 / (tDIG_L +<br>tDIG_H) |
  1056. | tDIG_L | SCL Clock Low Period 1,2 | 32 | — | — | ns | — |
  1057. | tDIG_H | SCL Clock High Period 1 | 32 | — | — | ns | — |
  1058. | tSCO | Clock in to Data Out for<br>Slave 3,4 | — | — | 12 | ns | — |
  1059. | tCR | SCL Clock Rise Time 5 | — | — | 150e06 *<br>1 / fSCL<br>(capped<br>at 60) | ns | — |
  1060. | tCF | SCL Clock Fall Time 5 | — | — | 150e06 *<br>1 / fSCL<br>(capped<br>at 60) | ns | — |
  1061. | tHD_PP | SDA Signal Data Hold in Push<br>Pull Mode, Slave 6 | 1 | — | — | — | Applicable for slave<br>and master loopback<br>modes |
  1062. | tSU_PP | SDA Signal Data Setup in Push<br>Pull Mode | 3 | — | N/A | ns | Applicable for slave<br>and master loopback<br>modes. |
  1063.  
  1064. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  1065. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  1066. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  1067.  
  1068. | Parameters | FlexCAN (Classical and FD) | Unit |
  1069. |----------------------------|----------------------------|------|
  1070. | Maximum Baud Rate | 8/8 | Mbps |
  1071. | TXD Rise time wcs | 4/4 | ns |
  1072. | TXD Fall time wcs | 4/4 | ns |
  1073. | RXD Rise time wcs | 4/4 | ns |
  1074. | RXD Fall time wcs | 4/4 | ns |
  1075. | TXD | 3.3/3.3 | V |
  1076. | RXD | 3.3/3.3 | V |
  1077. | Internal delay wcs | 100/50 | ns |
  1078. | TX PAD delay wcs | 25/25 | ns |
  1079. | RX PAD delay wcs | 10/10 | ns |
  1080. | TX routing delay wcs | 5/5 | ns |
  1081. | RX routing delay wcs | 5/5 | ns |
  1082. | Transceiver loop delay wcs | 250/250 | ns |
  1083. | Total loop delay | 395/345 | ns |
  1084.  
  1085. | ID | Parameter | Min | Max | Unit |
  1086. |----|-----------------------------|-----|------|------|
  1087. | | PWM Module Clock Frequency | 0 | 83.3 | MHz |
  1088. | P1 | PWM output pulse width high | 12 | — | ns |
  1089. | P2 | PWM output pulse width low | 12 | — | ns |
  1090.  
  1091. | Symbol | Parameter | Min | Max | Unit |
  1092. |--------|------------------------------|-----|-----|------|
  1093. | — | Frequency of operation1 | — | 66 | MHz |
  1094. | F1 | Setup time for incoming data | 6 | — | ns |
  1095. | F2 | Hold time for incoming data | 0 | — | ns |
  1096.  
  1097. | Symbol | Parameter | Min | Max | Unit |
  1098. |--------|------------------------------|-----|-----|------|
  1099. | — | Frequency of operation | — | 50 | MHz |
  1100. | F1 | Setup time for incoming data | 7 | — | ns |
  1101. | F2 | Hold time for incoming data | 0 | — | ns |
  1102.  
  1103. | Symbol | Parameter | Min | Max | Unit |
  1104. |--------|------------------------------|-----|-----|------|
  1105. | — | Frequency of operation1 | — | 166 | MHz |
  1106. | F1 | Setup time for incoming data | 1 | — | ns |
  1107. | F2 | Hold time for incoming data | 1 | — | ns |
  1108.  
  1109. | Symbol | Parameter | Min | Max | Unit |
  1110. |--------|------------------------------|-----|-----|------|
  1111. | — | Frequency of operation1 | — | 100 | MHz |
  1112. | F1 | Setup time for incoming data | 2 | — | ns |
  1113. | F2 | Hold time for incoming data | 1 | — | ns |
  1114.  
  1115. | Symbol | Parameter | Min | Max | Unit |
  1116. |--------|------------------------|-----|-----|------|
  1117. | — | Frequency of operation | — | 200 | MHz |
  1118.  
  1119. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  1120. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  1121. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  1122.  
  1123. | Symbol | Parameter | Min | Max | Unit |
  1124. |-----------------|--------------------------------------|------|-----|------|
  1125. | TSCKD | Time from SCK to data valid | — | — | ns |
  1126. | TSCKDQS | Time from SCK to DQS | — | — | ns |
  1127. | TSCKD - TSCKDQS | Time delta between TSCKD and TSCKDQS | -0.6 | 0.6 | ns |
  1128.  
  1129. | Symbol | Parameter | Min | Max | Unit |
  1130. |-----------------|--------------------------------------|-----|-----|------|
  1131. | — | Frequency of operation | — | 133 | MHz |
  1132. | TSCKD | Time from SCK to data valid | — | — | ns |
  1133. | TSCKDQS | Time from SCK to DQS | — | — | ns |
  1134. | TSCKD - TSCKDQS | Time delta between TSCKD and TSCKDQS | -2 | 2 | ns |
  1135.  
  1136. | Symbol | Parameter | Value | | |
  1137. |-----------------|--------------------------------------|-------|-----|------|
  1138. | | | Min | Max | Unit |
  1139. | — | Frequency of operation | — | 200 | MHz |
  1140. | TSCKD | Time from SCK to data valid | — | — | ns |
  1141. | TSCKDQS | Time from SCK to DQS | — | — | ns |
  1142. | TSCKD - TSCKDQS | Time delta between TSCKD and TSCKDQS | -0.6 | 0.6 | ns |
  1143.  
  1144. | | Parameter | Value | | |
  1145. |-----------------|--------------------------------------|-------|-----|------|
  1146. | Symbol | | Min | Max | Unit |
  1147. | — | Frequency of operation | — | 133 | MHz |
  1148. | TSCKD | Time from SCK to data valid | — | — | ns |
  1149. | TSCKDQS | Time from SCK to DQS | — | — | ns |
  1150. | TSCKD - TSCKDQS | Time delta between TSCKD and TSCKDQS | -2 | 2 | ns |
  1151.  
  1152. | FLEXSPI_SCLK | TSCKD | | | | |
  1153. |-------------------------------------------------------------------------------------------|-------------------------------------------------|--|--|--|--|
  1154. | FLEXSPI_DATA[7:0] | TSCKD<br>TSCKD<br>TSCKDQS<br>TSCKDQS<br>TSCKDQS | | | | |
  1155. | FLEXSPI_DQS | | | | | |
  1156. | Internal Sample Clock | | | | | |
  1157. | Figure 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2) | | | | | |
  1158.  
  1159. | Symbol | Parameter | Min | Max | Unit |
  1160. |--------|------------------------------|-----|-----|------|
  1161. | — | Frequency of operation | — | 33 | MHz |
  1162. | F1 | Setup time for incoming data | 6 | — | ns |
  1163. | F2 | Hold time for incoming data | 0 | — | ns |
  1164.  
  1165. | | Table 83. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 (Nominal and Overdrive mode) | | |
  1166. |--|-------------------------------------------------------------------------------------------------------------|--|--|
  1167. | | | | |
  1168.  
  1169. | Symbol | Parameter | Min | Max | Unit |
  1170. |--------|------------------------------|-----|-----|------|
  1171. | — | Frequency of operation1 | — | 83 | MHz |
  1172. | F1 | Setup time for incoming data | 1 | — | ns |
  1173. | F2 | Hold time for incoming data | 1 | — | ns |
  1174.  
  1175. | Symbol | Parameter | Min | Max | Unit |
  1176. |--------|------------------------------|-----|-----|------|
  1177. | — | Frequency of operation1 | — | 66 | MHz |
  1178. | F1 | Setup time for incoming data | 1.5 | — | ns |
  1179. | F2 | Hold time for incoming data | 1 | — | ns |
  1180.  
  1181. | Symbol | Parameter | Min | Max | Unit |
  1182. |-----------------|--------------------------------------|------|-----|------|
  1183. | — | Frequency of operation | — | 200 | MHz |
  1184. | TSCKD | Time from SCK to data valid | — | — | ns |
  1185. | TSCKDQS | Time from SCK to DQS | — | — | ns |
  1186. | TSCKD - TSCKDQS | Time delta between TSCKD and TSCKDQS | -0.6 | 0.6 | ns |
  1187.  
  1188. | Symbol | Parameter | Min | Max | Unit |
  1189. |-----------------|--------------------------------------|------|-----|------|
  1190. | — | Frequency of operation | — | 133 | MHz |
  1191. | TSCKD | Time from SCK to data valid | — | — | ns |
  1192. | TSCKDQS | Time from SCK to DQS | — | — | ns |
  1193. | TSCKD - TSCKDQS | Time delta between TSCKD and TSCKDQS | -0.9 | 0.9 | ns |
  1194.  
  1195. | Symbol | Parameter | Min | Max | Unit |
  1196. |--------|--------------------------------|-----------------------------|-----|------|
  1197. | — | Frequency of operation2 | — | 200 | MHz |
  1198. | Tck | SCK clock period | 5 | — | ns |
  1199. | TDVO | Output data valid time | — | 0.6 | ns |
  1200. | TDHO | Output data hold time | -0.6 | — | ns |
  1201. | TCSS | Chip select output setup time3 | (TCSS + 0.5) x<br>Tck - 0.6 | — | ns |
  1202. | TCSH | Chip select output hold time3 | (TCSH x Tck) -<br>0.6 | — | ns |
  1203.  
  1204. | Table 87. FlexSPI output timing in SDR mode (Nominal and Overdrive mode)1 | |
  1205. |---------------------------------------------------------------------------|--|
  1206. |---------------------------------------------------------------------------|--|
  1207.  
  1208. | Symbol | Parameter | Min | | Unit |
  1209. |--------|-------------------------|-----|------|------|
  1210. | — | Frequency of operation1 | — | 1332 | MHz |
  1211. | Tck | SCK clock period | 7.5 | — | ns |
  1212. | TDVO | Output data valid time | — | 2 | ns |
  1213. | TDHO | Output data hold time | -2 | — | ns |
  1214.  
  1215. | Symbol | Parameter | Min | Max | Unit |
  1216. |--------|-------------------------------|---------------------------|-----|------|
  1217. | TCSS | Chip select output setup time | (TCSS + 0.5) x<br>Tck - 2 | — | ns |
  1218. | TCSH | Chip select output hold time3 | (TCSH x Tck) - 2 | — | ns |
  1219.  
  1220. | Symbol | Parameter | Min | Max | Unit |
  1221. |--------|-------------------------------|-----------------------------|-------|------|
  1222. | — | Frequency of operation2 | — | 200 | MHz |
  1223. | Tck | SCK clock period | 5 | — | ns |
  1224. | TDVO | Output data valid time | — | 1.815 | ns |
  1225. | TDHO | Output data hold time | 0.615 | — | ns |
  1226. | TCSS | Chip select output setup time | (TCSS + 0.5) x<br>Tck - 0.6 | — | ns |
  1227. | TCSH | Chip select output hold time3 | (TCSH + 0.5) x<br>Tck - 0.6 | — | ns |
  1228.  
  1229. | Symbol | Parameter | Min | Max | Unit |
  1230. |--------|--------------------------------|-----------------------------|------|------|
  1231. | — | Frequency of operation1 | — | 1332 | MHz |
  1232. | Tck | SCK clock period | 7.5 | — | ns |
  1233. | TDVO | Output data valid time | — | 2.75 | ns |
  1234. | TDHO | Output data hold time | 0.9 | — | ns |
  1235. | TCSS | Chip select output setup time3 | (TCSS + 0.5) x<br>Tck - 0.9 | — | ns |
  1236. | TCSH | Chip select output hold time3 | (TCSH + 0.5) x<br>Tck - 0.9 | — | ns |
  1237.  
  1238. | Symbol | Descriptions | Min | Typ | Max | Unit | Notes |
  1239. |--------|-----------------------------------------------------------------------------------------------------------------------|-----|-----|-----|------|-------|
  1240. | tODS | Output delay skew between any two<br>FlexIO_Dx pins configured as outputs that<br>toggle on same internal clock cycle | 0 | — | 12 | ns | 3 |
  1241.  
  1242. | IMX93AEC | |
  1243. |--------------------|--|
  1244. | Product Data Sheet | |
  1245.  
  1246. | | | Table 91. FlexIO timing specifications1,2<br>continued |
  1247. |--|--|--------------------------------------------------------|
  1248. |--|--|--------------------------------------------------------|
  1249.  
  1250. | tIDS | Input delay skew between any two | 0 | — | 12 | ns | 3 |
  1251. |------|----------------------------------------------|---|---|----|----|---|
  1252. | | FlexIO_Dx pins configured as inputs that are | | | | | |
  1253. | | sampled on the same internal clock cycle | | | | | |
  1254.  
  1255. | | | | Table 92. Fuses and associated pins used for boot | | | | |
  1256. |--|--|--|---------------------------------------------------|--|--|--|--|
  1257. |--|--|--|---------------------------------------------------|--|--|--|--|
  1258.  
  1259. | BOOT_MODE[3:0] | Function |
  1260. |----------------|----------------------------------|
  1261. | x000 | Boot from Internal Fuses |
  1262. | 0001 | Serial Download (USB1) |
  1263. | 0010 | uSDHC1 8-bit eMMC 5.1 |
  1264. | 0011 | uSDHC2 4-bit SD 3.0 |
  1265. | 0100 | FlexSPI Serial NOR |
  1266. | 0101 | FlexSPI Serial NAND 2K |
  1267. | 0110 | Reserved |
  1268. | 0111 | Reserved |
  1269. | 1000 | LPB: Boot from Internal Fuses |
  1270. | 1001 | LPB: Serial Downloader (USB1) |
  1271. | 1010 | LPB: uSDHC1 8-bit 1.8 V eMMC 5.1 |
  1272. | 1011 | LPB: uSDHC2 4-bit SD 3.0 |
  1273. | 1100 | LPB: FlexSPI Serial NOR |
  1274. | 1101 | LPB: FlexSPI Serial NAND 2K |
  1275. | 1110 | Reserved |
  1276. | 1111 | Reserved |
  1277.  
  1278. | IMX93AEC | All information provided in this document is subject to legal disclaimers. | © 2025 NXP B.V. All rights reserved. |
  1279. |--------------------|----------------------------------------------------------------------------|--------------------------------------|
  1280. | Product Data Sheet | Rev. 6.1 — 7 July 2025 | Document feedback |
  1281.  
  1282. | | | Table 93. Boot through FlexSPI |
  1283. |--|--|--------------------------------|
  1284. | | | |
  1285.  
  1286. | Signal name | PAD name | ALT |
  1287. |----------------|------------|------|
  1288. | FlexSPIA_DATA0 | SD3_DATA0 | ALT1 |
  1289. | FlexSPIA_DATA1 | SD3_DATA1 | ALT1 |
  1290. | FlexSPIA_DATA2 | SD3_DATA2 | ALT1 |
  1291. | FlexSPIA_DATA3 | SD3_DATA3 | ALT1 |
  1292. | FlexSPIA_DQS | SD1_STROBE | ALT1 |
  1293. | FlexSPIA_SS0_B | SD3_CMD | ALT1 |
  1294. | FlexSPIA_SCLK | SD3_CLK | ALT1 |
  1295. | FlexSPIA_DATA4 | SD1_DATA4 | ALT1 |
  1296. | FlexSPIA_DATA5 | SD1_DATA5 | ALT1 |
  1297. | FlexSPIA_DATA6 | SD1_DATA6 | ALT1 |
  1298. | FlexSPIA_DATA7 | SD1_DATA7 | ALT1 |
  1299.  
  1300. | Signal name | PAD name | ALT |
  1301. |--------------|-----------|------|
  1302. | USDHC1_CMD | SD1_CMD | ALT0 |
  1303. | USDHC1_CLK | SD1_CLK | ALT0 |
  1304. | USDHC1_DATA0 | SD1_DATA0 | ALT0 |
  1305.  
  1306. | USDHC1_DATA1 | SD1_DATA1 | ALT0 |
  1307. |--------------|-----------|------|
  1308. | USDHC1_DATA2 | SD1_DATA2 | ALT0 |
  1309. | USDHC1_DATA3 | SD1_DATA3 | ALT0 |
  1310. | USDHC1_DATA4 | SD1_DATA4 | ALT0 |
  1311. | USDHC1_DATA5 | SD1_DATA5 | ALT0 |
  1312. | USDHC1_DATA6 | SD1_DATA6 | ALT0 |
  1313. | USDHC1_DATA7 | SD1_DATA7 | ALT0 |
  1314. | USDHC1_RESET | SD1_DATA5 | ALT2 |
  1315.  
  1316. | Signal name | PAD name | ALT |
  1317. |----------------|-------------|------|
  1318. | USDHC2_CMD | SD2_CMD | ALT0 |
  1319. | USDHC2_CLK | SD2_CLK | ALT0 |
  1320. | USDHC2_DATA0 | SD2_DATA0 | ALT0 |
  1321. | USDHC2_DATA1 | SD2_DATA1 | ALT0 |
  1322. | USDHC2_DATA2 | SD2_DATA2 | ALT0 |
  1323. | USDHC2_DATA3 | SD2_DATA3 | ALT0 |
  1324. | USDHC2_RESET | SD2_RESET_B | ALT0 |
  1325. | USDHC2_VSELECT | SD2_VSELECT | ALT0 |
  1326.  
  1327. | Signal name | PAD name | ALT |
  1328. |-------------|-----------------|------|
  1329. | SPI1_PCS1 | PDM_BIT_STREAM0 | ALT2 |
  1330. | SPI1_SIN | SAI1_TXC | ALT2 |
  1331. | SPI1_SOUT | SAI1_RXD0 | ALT2 |
  1332. | SPI1_SCK | SAI1_TXD0 | ALT2 |
  1333. | SPI1_PCS0 | SAI1_TXFS | ALT2 |
  1334.  
  1335. | Signal name | PAD name | ALT |
  1336. |-------------|-----------------|------|
  1337. | SPI2_PCS1 | PDM_BIT_STREAM1 | ALT2 |
  1338. | SPI2_SIN | UART1_RXD | ALT2 |
  1339. | SPI2_SOUT | UART2_RXD | ALT2 |
  1340. | SPI2_SCK | UART2_TXD | ALT2 |
  1341. | SPI2_PCS0 | UART1_TXD | ALT2 |
  1342.  
  1343. | Signal name | PAD name | ALT |
  1344. |-------------|-----------|------|
  1345. | SPI3_PCS1 | GPIO_IO07 | ALT1 |
  1346. | SPI3_SIN | GPIO_IO09 | ALT1 |
  1347. | SPI3_SOUT | GPIO_IO10 | ALT1 |
  1348. | SPI3_SCK | GPIO_IO11 | ALT1 |
  1349. | SPI3_PCS0 | GPIO_IO08 | ALT1 |
  1350.  
  1351. | Signal name | PAD name | ALT |
  1352. |-------------|-----------|------|
  1353. | SPI4_PCS1 | GPIO_IO17 | ALT5 |
  1354. | SPI4_PCS2 | GPIO_IO16 | ALT5 |
  1355. | SPI4_SIN | GPIO_IO19 | ALT5 |
  1356. | SPI4_SOUT | GPIO_IO20 | ALT5 |
  1357. | SPI4_SCK | GPIO_IO21 | ALT5 |
  1358. | SPI4_PCS0 | GPIO_IO18 | ALT5 |
  1359.  
  1360. | | | | | | Table 100. 14 x 14 mm supplies contact assignment |
  1361. |--|--|--|--|--|---------------------------------------------------|
  1362. |--|--|--|--|--|---------------------------------------------------|
  1363.  
  1364. | Supply Rail Name | Ball(s) Position(s) | Remark |
  1365. |------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--------|
  1366. | NVCC_AON | L16 | — |
  1367. | NVCC_BBSM_1P8 | G12 | — |
  1368. | NVCC_GPIO | N15, N16 | — |
  1369. | NVCC_SD2 | R16 | — |
  1370. | NVCC_WAKEUP | R10, R12, W8 | — |
  1371. | VDD_ANA_0P8 | J15, J16, R14 | — |
  1372. | VDD_ANA0_1P8 | F16, G16 | — |
  1373. | VDD_ANA1_1P8 | R8 | — |
  1374. | VDD_ANAVDET_1P8 | L15 | — |
  1375. | VDD_BBSM_0P8_CAP | G14 | — |
  1376. | VDD_LVDS_1P8 | F6 | — |
  1377. | VDD_MIPI_0P8 | G8 | — |
  1378. | VDD_MIPI_1P8 | F8 | — |
  1379. | VDD_SOC | J9, J10, J11, J12, J13, K9, K10, K12, K13, M9, M10, M12, M13, N9, N10,<br>N11, N12, N13 | — |
  1380. | VDD_USB_0P8 | F10 | — |
  1381. | VDD_USB_1P8 | E8 | — |
  1382. | VDD_USB_3P3 | G10 | — |
  1383. | VDD2_DDR | L7, N6, N7, R6, T6 | — |
  1384. | VDDQ_DDR | G6, J6, J7, L6 | — |
  1385. | VSS | A1, A21, C2, C4, C6, C8, C10, C12, C14, C16, C18, E3, E19, G3, G19,<br>H8, H10, H12, H14, J3, J5, J8, J14, J19, K11, L1, L3, L5, L8, L14, L19,<br>M11, N3, N5, N8, N14, N19, P8, P10, P12, P14, R3, R19, T1, U3, U19,<br>W4, W6, W10, W12, W14, W16, W18, AA1, AA21 | — |
  1386.  
  1387. | | | | Table 101. 14 x 14 mm functional contact assignment |
  1388. |--|--|--|-----------------------------------------------------|
  1389. |--|--|--|-----------------------------------------------------|
  1390.  
  1391. | | | | Default setting | | | |
  1392. |----------------------|-----------------|-------------|-----------------|------------------|--------------------|--------------------------------------|
  1393. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1394. | ADC_IN0 | B19 | VDD_ANA_1P8 | ANALOG | — | — | Input without<br>PU1<br>/ PD2 |
  1395. | ADC_IN1 | A20 | VDD_ANA_1P8 | ANALOG | — | — | Input without<br>PU / PD |
  1396. | ADC_IN2 | B20 | VDD_ANA_1P8 | ANALOG | — | — | Input without<br>PU / PD |
  1397. | ADC_IN3 | B21 | VDD_ANA_1P8 | ANALOG | — | — | Input without<br>PU / PD |
  1398. | CCM_CLKO1 | AA2 | NVCC_WAKEUP | GPIO | Alt0 | CCMSRCGPCMIX.CLK01 | Output low |
  1399. | CCM_CLKO2 | Y3 | NVCC_WAKEUP | GPIO | Alt0 | CCMSRCGPCMIX.CLK02 | Output low |
  1400. | CCM_CLKO3 | U4 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[28] | Input with PD |
  1401. | CCM_CLKO4 | V4 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[29] | Input with PD |
  1402. | CLKIN1 | B17 | VDD_ANA_1P8 | ANALOG | — | — | Input without<br>PU / PD |
  1403. | CLKIN2 | A18 | VDD_ANA_1P8 | ANALOG | — | — | Input without<br>PU / PD |
  1404. | DAP_TCLK_SWCLK | Y1 | NVCC_WAKEUP | GPIO | Alt0 | DAP.TCLK_SWCLK | Input with PD |
  1405. | DAP_TDI | W1 | NVCC_WAKEUP | GPIO | Alt0 | DAP.TDI | Input with PU |
  1406. | DAP_TDO_TRACESW<br>O | Y2 | NVCC_WAKEUP | GPIO | Alt0 | DAP.TDO_TRACESWO | Input without<br>PU/PD |
  1407. | DAP_TMS_SWDIO | W2 | NVCC_WAKEUP | GPIO | Alt0 | DAP.TMS_SWDIO | Input with PU |
  1408. | DRAM_CA0_A | H2 | VDD2_DDR | DDR | — | — | — |
  1409. | DRAM_CA1_A | G1 | VDD2_DDR | DDR | — | — | — |
  1410. | DRAM_CA2_A | F2 | VDD2_DDR | DDR | — | — | — |
  1411. | DRAM_CA3_A | E1 | VDD2_DDR | DDR | — | — | — |
  1412. | DRAM_CA4_A | E2 | VDD2_DDR | DDR | — | — | — |
  1413. | DRAM_CA5_A | D1 | VDD2_DDR | DDR | — | — | — |
  1414.  
  1415. | | | | Table 101. 14 x 14 mm functional contact assignment continued | | | |
  1416. |--|--|--|---------------------------------------------------------------|--|--|--|
  1417. |--|--|--|---------------------------------------------------------------|--|--|--|
  1418.  
  1419. | | | | | | Default setting | |
  1420. |-------------|-----------------|-------------|------------|------------------|------------------|--------------------------------------|
  1421. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1422. | DRAM_CK_C_A | G5 | VDD2_DDR | DDR | — | — | — |
  1423. | DRAM_CK_T_A | G4 | VDD2_DDR | DDR | — | — | — |
  1424. | DRAM_CKE0_A | H1 | VDD2_DDR | DDR | — | — | — |
  1425. | DRAM_CKE1_A | J4 | VDD2_DDR | DDR | — | — | — |
  1426. | DRAM_CS0_A | F1 | VDD2_DDR | DDR | — | — | — |
  1427. | DRAM_CS1_A | G2 | VDD2_DDR | DDR | — | — | — |
  1428. | DRAM_DMI0_A | L2 | VDDQ_DDR | DDR | — | — | — |
  1429. | DRAM_DMI1_A | T2 | VDDQ_DDR | DDR | — | — | — |
  1430. | DRAM_DQ00_A | N1 | VDDQ_DDR | DDR | — | — | — |
  1431. | DRAM_DQ01_A | N2 | VDDQ_DDR | DDR | — | — | — |
  1432. | DRAM_DQ02_A | M1 | VDDQ_DDR | DDR | — | — | — |
  1433. | DRAM_DQ03_A | M2 | VDDQ_DDR | DDR | — | — | — |
  1434. | DRAM_DQ04_A | K1 | VDDQ_DDR | DDR | — | — | — |
  1435. | DRAM_DQ05_A | K2 | VDDQ_DDR | DDR | — | — | — |
  1436. | DRAM_DQ06_A | J1 | VDDQ_DDR | DDR | — | — | — |
  1437. | DRAM_DQ07_A | J2 | VDDQ_DDR | DDR | — | — | — |
  1438. | DRAM_DQ08_A | V1 | VDDQ_DDR | DDR | — | — | — |
  1439. | DRAM_DQ09_A | V2 | VDDQ_DDR | DDR | — | — | — |
  1440. | DRAM_DQ10_A | U2 | VDDQ_DDR | DDR | — | — | — |
  1441. | DRAM_DQ11_A | U1 | VDDQ_DDR | DDR | — | — | — |
  1442. | DRAM_DQ12_A | R1 | VDDQ_DDR | DDR | — | — | — |
  1443. | DRAM_DQ13_A | R2 | VDDQ_DDR | DDR | — | — | — |
  1444. | DRAM_DQ14_A | P2 | VDDQ_DDR | DDR | — | — | — |
  1445.  
  1446. | | | | Table 101. 14 x 14 mm functional contact assignment continued | | | |
  1447. |--|--|--|---------------------------------------------------------------|--|--|--|
  1448. |--|--|--|---------------------------------------------------------------|--|--|--|
  1449.  
  1450. | | | | | Default setting | | |
  1451. |---------------|-----------------|-------------|------------|------------------|------------------|--------------------------------------|
  1452. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1453. | DRAM_DQ15_A | P1 | VDDQ_DDR | DDR | — | — | — |
  1454. | DRAM_DQS0_C_A | L4 | VDDQ_DDR | — | — | — | — |
  1455. | DRAM_DQS0_T_A | N4 | VDDQ_DDR | DDRCLK | — | — | — |
  1456. | DRAM_DQS1_C_A | R5 | VDDQ_DDR | — | — | — | — |
  1457. | DRAM_DQS1_T_A | R4 | VDDQ_DDR | DDRCLK | — | — | — |
  1458. | DRAM_MTEST1 | D4 | VDD2_DDR | DDR | — | — | — |
  1459. | DRAM_RESET_N | D2 | VDD2_DDR | DDR | — | — | — |
  1460. | DRAM_ZQ | E4 | VDDQ_DDR | DDR | — | — | — |
  1461. | ENET1_MDC | AA11 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[0] | Input with PD |
  1462. | ENET1_MDIO | AA10 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[1] | Input with PD |
  1463. | ENET1_RD0 | AA8 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[10] | Input with PD |
  1464. | ENET1_RD1 | Y9 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[11] | Input with PD |
  1465. | ENET1_RD2 | AA9 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[12] | Input with PD |
  1466. | ENET1_RD3 | Y10 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[13] | Input with PD |
  1467. | ENET1_RX_CTL | Y8 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[8] | Input with PD |
  1468. | ENET1_RXC | AA7 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[9] | Input with PD |
  1469. | ENET1_TD0 | W11 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[5] | Input with PD |
  1470. | ENET1_TD1 | T12 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[4] | Input with PD |
  1471. | ENET1_TD2 | U12 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[3] | Input with PD |
  1472. | ENET1_TD3 | V12 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[2] | Input with PD |
  1473. | ENET1_TX_CTL | V10 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[6] | Input with PD |
  1474. | ENET1_TXC | U10 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[7] | Input with PD |
  1475. | ENET2_MDC | Y7 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[14] | Input with PD |
  1476.  
  1477. | | | | Table 101. 14 x 14 mm functional contact assignment continued | |
  1478. |--|--|--|---------------------------------------------------------------|--|
  1479. |--|--|--|---------------------------------------------------------------|--|
  1480.  
  1481. | | | | | | Default setting | |
  1482. |--------------|-----------------|-------------|------------|------------------|------------------|--------------------------------------|
  1483. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1484. | ENET2_MDIO | AA6 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[15] | Input with PD |
  1485. | ENET2_RD0 | AA4 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[24] | Input with PD |
  1486. | ENET2_RD1 | Y5 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[25] | Input with PD |
  1487. | ENET2_RD2 | AA5 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[26] | Input with PD |
  1488. | ENET2_RD3 | Y6 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[27] | Input with PD |
  1489. | ENET2_RX_CTL | Y4 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[22] | Input with PD |
  1490. | ENET2_RXC | AA3 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[23] | Input with PD |
  1491. | ENET2_TD0 | T8 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[19] | Input with PD |
  1492. | ENET2_TD1 | U8 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[18] | Input with PD |
  1493. | ENET2_TD2 | V8 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[17] | Input with PD |
  1494. | ENET2_TD3 | T10 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[16] | Input with PD |
  1495. | ENET2_TX_CTL | V6 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[20] | Input with PD |
  1496. | ENET2_TXC | U6 | NVCC_WAKEUP | GPIO | Alt5 | GPIO4.IO[21] | Input with PD |
  1497. | GPIO_IO00 | J21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[0] | Input with PD |
  1498. | GPIO_IO01 | J20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[1] | Input with PD |
  1499. | GPIO_IO02 | K20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[2] | Input with PD |
  1500. | GPIO_IO03 | K21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[3] | Input with PD |
  1501. | GPIO_IO04 | L17 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[4] | Input with PD |
  1502. | GPIO_IO05 | L18 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[5] | Input with PD |
  1503. | GPIO_IO06 | L20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[6] | Input with PD |
  1504. | GPIO_IO07 | L21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[7] | Input with PD |
  1505. | GPIO_IO08 | M20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[8] | Input with PD |
  1506. | GPIO_IO09 | M21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[9] | Input with PD |
  1507.  
  1508. | | Table 101. 14 x 14 mm functional contact assignment continued | | | | |
  1509. |--|---------------------------------------------------------------|--|--|--|--|
  1510. |--|---------------------------------------------------------------|--|--|--|--|
  1511.  
  1512. | | | | | Default setting | | | |
  1513. |-----------|-----------------|-------------|------------|------------------|------------------|--------------------------------------|--|
  1514. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted | |
  1515. | GPIO_IO10 | N17 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[10] | Input with PD | |
  1516. | GPIO_IO11 | N18 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[11] | Input with PD | |
  1517. | GPIO_IO12 | N20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[12] | Input with PD | |
  1518. | GPIO_IO13 | N21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[13] | Input with PD | |
  1519. | GPIO_IO14 | P20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[14] | Input with PD | |
  1520. | GPIO_IO15 | P21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[15] | Input with PD | |
  1521. | GPIO_IO16 | R21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[16] | Input with PD | |
  1522. | GPIO_IO17 | R20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[17] | Input with PD | |
  1523. | GPIO_IO18 | R18 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[18] | Input with PD | |
  1524. | GPIO_IO19 | R17 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[19] | Input with PD | |
  1525. | GPIO_IO20 | T20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[20] | Input with PD | |
  1526. | GPIO_IO21 | T21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[21] | Input with PD | |
  1527. | GPIO_IO22 | U18 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[22] | Input with PD | |
  1528. | GPIO_IO23 | U20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[23] | Input with PD | |
  1529. | GPIO_IO24 | U21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[24] | Input with PD | |
  1530. | GPIO_IO25 | V21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[25] | Input with PD | |
  1531. | GPIO_IO26 | V20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[26] | Input with PD | |
  1532. | GPIO_IO27 | W21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[27] | Input with PD | |
  1533. | GPIO_IO28 | W20 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[28] | Input with PD | |
  1534. | GPIO_IO29 | Y21 | NVCC_GPIO | GPIO | Alt0 | GPIO2.IO[29] | Input with PD | |
  1535. | I2C1_SCL | C20 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[0] | Input with PD | |
  1536. | I2C1_SDA | C21 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[1] | Input with PD | |
  1537. | I2C2_SCL | D20 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[2] | Input with PD | |
  1538.  
  1539. | | | | | | | Table 101. 14 x 14 mm functional contact assignment continued | |
  1540. |--|--|--|--|--|--|---------------------------------------------------------------|--|
  1541. |--|--|--|--|--|--|---------------------------------------------------------------|--|
  1542.  
  1543. | | | Default setting | | | | |
  1544. |-----------------|-----------------|-----------------|------------|------------------|------------------|--------------------------------------|
  1545. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1546. | I2C2_SDA | D21 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[3] | Input with PD |
  1547. | LVDS_D0_P | B5 | VDD_LVDS_1P8 | PHY | — | — | — |
  1548. | LVDS_D0_N | A5 | VDD_LVDS_1P8 | PHY | — | — | — |
  1549. | LVDS_D1_P | B4 | VDD_LVDS_1P8 | PHY | — | — | — |
  1550. | LVDS_D1_N | A4 | VDD_LVDS_1P8 | PHY | — | — | — |
  1551. | LVDS_D2_P | B2 | VDD_LVDS_1P8 | PHY | — | — | — |
  1552. | LVDS_D2_N | A2 | VDD_LVDS_1P8 | PHY | — | — | — |
  1553. | LVDS_D3_P | C1 | VDD_LVDS_1P8 | PHY | — | — | — |
  1554. | LVDS_D3_N | B1 | VDD_LVDS_1P8 | PHY | — | — | — |
  1555. | LVDS_CLK_P | B3 | VDD_LVDS_1P8 | PHY | — | — | — |
  1556. | LVDS_CLK_N | A3 | VDD_LVDS_1P8 | PHY | — | — | — |
  1557. | MIPI_CSI1_CLK_N | D10 | MIPI_CSI1_VPH | PHY | — | — | — |
  1558. | MIPI_CSI1_CLK_P | E10 | MIPI_CSI1_VPH | PHY | — | — | — |
  1559. | MIPI_CSI1_D0_N | A11 | MIPI_CSI1_VPH | PHY | — | — | — |
  1560. | MIPI_CSI1_D0_P | B11 | MIPI_CSI1_VPH | PHY | — | — | — |
  1561. | MIPI_CSI1_D1_N | A10 | MIPI_CSI1_VPH | PHY | — | — | — |
  1562. | MIPI_CSI1_D1_P | B10 | MIPI_CSI1_VPH | PHY | — | — | — |
  1563. | MIPI_DSI1_CLK_N | D6 | MIPI_DSI1_VPH | PHY | — | — | — |
  1564. | MIPI_DSI1_CLK_P | E6 | MIPI_DSI1_VPH | PHY | — | — | — |
  1565. | MIPI_DSI1_D0_N | A6 | MIPI_DSI1_VPH | PHY | — | — | — |
  1566. | MIPI_DSI1_D0_P | B6 | MIPI_DSI1_VPH | PHY | — | — | — |
  1567. | MIPI_DSI1_D1_N | A7 | MIPI_DSI1_VPH | PHY | — | — | — |
  1568. | MIPI_DSI1_D1_P | B7 | MIPI_DSI1_VPH | PHY | — | — | — |
  1569.  
  1570. | | | | | Table 101. 14 x 14 mm functional contact assignment continued | |
  1571. |--|--|--|--|---------------------------------------------------------------|--|
  1572. |--|--|--|--|---------------------------------------------------------------|--|
  1573.  
  1574. | | | | | Default setting | | |
  1575. |-----------------|-----------------|---------------|------------|------------------|-----------------------------------------------|--------------------------------------|
  1576. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1577. | MIPI_DSI1_D2_N | A8 | MIPI_DSI1_VPH | PHY | — | — | — |
  1578. | MIPI_DSI1_D2_P | B8 | MIPI_DSI1_VPH | PHY | — | — | — |
  1579. | MIPI_DSI1_D3_N | A9 | MIPI_DSI1_VPH | PHY | — | — | — |
  1580. | MIPI_DSI1_D3_P | B9 | MIPI_DSI1_VPH | PHY | — | — | — |
  1581. | MIPI_REXT | D8 | MIPI_DSI1_VPH | PHY | — | — | — |
  1582. | ONOFF | A19 | NVCC_BBSM_1P8 | GPIO | Alt0 | BBSMMIX.ONOFF | Input without<br>PU / PD |
  1583. | PDM_BIT_STREAM0 | J17 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[9] | Input with PD |
  1584. | PDM_BIT_STREAM1 | G18 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[10] | Input with PD |
  1585. | PDM_CLK | G17 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[8] | Input with PD |
  1586. | PMIC_ON_REQ | A17 | NVCC_BBSM_1P8 | GPIO | Alt0 | BBSMMIX.PMIC_ON_REQ | Output high<br>without PU /<br>PD |
  1587. | PMIC_STBY_REQ | B18 | NVCC_BBSM_1P8 | GPIO | Alt0 | BBSMMIX.PMIC_STBY_<br>REQ | Output low<br>without PU /<br>PD |
  1588. | POR_B | A16 | NVCC_BBSM_1P8 | GPIO | Alt0 | BBSMMIX.POR_B | Input without<br>PU / PD |
  1589. | RTC_XTALI | E16 | NVCC_BBSM_1P8 | ANALOG | Alt0 | BBSMMIX.RTC | — |
  1590. | RTC_XTALO | D16 | NVCC_BBSM_1P8 | ANALOG | — | — | — |
  1591. | SAI1_RXD0 | H20 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[14] | Input with PD |
  1592. | SAI1_TXC | G20 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[12] | Input with PD |
  1593. | SAI1_TXD0 | H21 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[13]<br>CCMSRCGPCMIX.BOOT_<br>MODE[3] | Input with PD |
  1594. | SAI1_TXFS | G21 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[11]<br>CCMSRCGPCMIX.BOOT_<br>MODE[2] | Input with PD |
  1595.  
  1596. | | Table 101. 14 x 14 mm functional contact assignment continued | | | | |
  1597. |--|---------------------------------------------------------------|--|--|--|--|
  1598. |--|---------------------------------------------------------------|--|--|--|--|
  1599.  
  1600. | | | | | Default setting | | | |
  1601. |-------------|-----------------|-------------|------------|------------------|------------------|--------------------------------------|--|
  1602. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted | |
  1603. | SD1_CLK | Y11 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[8] | Input with PD | |
  1604. | SD1_CMD | AA12 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[9] | Input with PD | |
  1605. | SD1_DATA0 | AA14 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[10] | Input with PD | |
  1606. | SD1_DATA1 | AA15 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[11] | Input with PD | |
  1607. | SD1_DATA2 | AA16 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[12] | Input with PD | |
  1608. | SD1_DATA3 | AA13 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[13] | Input with PD | |
  1609. | SD1_DATA4 | Y13 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[14] | Input with PD | |
  1610. | SD1_DATA5 | Y14 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[15] | Input with PD | |
  1611. | SD1_DATA6 | Y15 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[16] | Input with PD | |
  1612. | SD1_DATA7 | Y16 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[17] | Input with PD | |
  1613. | SD1_STROBE | Y12 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[18] | Input without<br>PU / PD | |
  1614. | SD2_CD_B | Y17 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[0] | Input with PD | |
  1615. | SD2_CLK | AA19 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[1] | Input with PD | |
  1616. | SD2_CMD | Y19 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[2] | Input with PD | |
  1617. | SD2_DATA0 | Y18 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[3] | Input with PD | |
  1618. | SD2_DATA1 | AA18 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[4] | Input with PD | |
  1619. | SD2_DATA2 | Y20 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[5] | Input with PD | |
  1620. | SD2_DATA3 | AA20 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[6] | Input with PD | |
  1621. | SD2_RESET_B | AA17 | NVCC_SD2 | GPIO | Alt5 | GPIO3.IO[7] | Input with PD | |
  1622. | SD2_VSELECT | V18 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[19] | Input with PD | |
  1623. | SD3_CLK | V16 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[20] | Input with PD | |
  1624. | SD3_CMD | U16 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[21] | Input with PD | |
  1625. | SD3_DATA0 | T16 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[22] | Input with PD | |
  1626.  
  1627. | | | | | | | Table 101. 14 x 14 mm functional contact assignment continued | |
  1628. |--|--|--|--|--|--|---------------------------------------------------------------|--|
  1629. |--|--|--|--|--|--|---------------------------------------------------------------|--|
  1630.  
  1631. | | | | | | Default setting | |
  1632. |--------------|-----------------|---------------|------------|------------------|----------------------------------------------|--------------------------------------|
  1633. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1634. | SD3_DATA1 | V14 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[23] | Input with PD |
  1635. | SD3_DATA2 | U14 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[24] | Input with PD |
  1636. | SD3_DATA3 | T14 | NVCC_WAKEUP | GPIO | Alt5 | GPIO3.IO[25] | Input with PD |
  1637. | TAMPER0 | B16 | NVCC_BBSM_1P8 | GPIO | Alt0 | BBSMMIX.TAMPER0 | Input with PD |
  1638. | TAMPER1 | F14 | NVCC_BBSM_1P8 | GPIO | Alt0 | BBSMMIX.TAMPER1 | Input with PD |
  1639. | UART1_RXD | E20 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[4] | Input with PD |
  1640. | UART1_TXD | E21 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[5]<br>CCMSRCGPCMIX.BOOT_<br>MODE[0] | Input with PD |
  1641. | UART2_RXD | F20 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[6] | Input with PD |
  1642. | UART2_TXD | F21 | NVCC_AON | GPIO | Alt5 | GPIO1.IO[7]<br>CCMSRCGPCMIX.BOOT_<br>MODE[1] | Input with PD |
  1643. | USB1_D_N | A14 | VDD_USB_3P3 | PHY | — | — | — |
  1644. | USB1_D_P | B14 | VDD_USB_3P3 | PHY | — | — | — |
  1645. | USB1_ID | C11 | VDD_USB_1P8 | PHY | — | — | — |
  1646. | USB1_TXRTUNE | D12 | VDD_USB_1P8 | PHY | — | — | — |
  1647. | USB1_VBUS | F12 | VDD_USB_3P3 | PHY | — | — | — |
  1648. | USB2_D_N | A15 | VDD_USB_3P3 | PHY | — | — | — |
  1649. | USB2_D_P | B15 | VDD_USB_3P3 | PHY | — | — | — |
  1650. | USB2_ID | E12 | VDD_USB_1P8 | PHY | — | — | — |
  1651. | USB2_TXRTUNE | D14 | VDD_USB_1P8 | PHY | — | — | — |
  1652. | USB2_VBUS | E14 | VDD_USB_3P3 | PHY | — | — | — |
  1653. | WDOG_ANY | J18 | NVCC_AON | GPIO | Alt0 | WDOG1.WDOG_ANY | Input with PU |
  1654. | XTALI_24M | D18 | VDD_ANA_1P8 | ANALOG | — | — | — |
  1655.  
  1656. | | | | | | | Table 101. 14 x 14 mm functional contact assignment continued | |
  1657. |--|--|--|--|--|--|---------------------------------------------------------------|--|
  1658. |--|--|--|--|--|--|---------------------------------------------------------------|--|
  1659.  
  1660. | | | | | | Default setting | |
  1661. |-----------|-----------------|-------------|------------|------------------|------------------|--------------------------------------|
  1662. | Ball name | 14 x 14<br>ball | Power group | Ball Types | Default<br>modes | Default function | Status while<br>reset is<br>asserted |
  1663. | XTALO_24M | E18 | VDD_ANA_1P8 | ANALOG | — | — | — |
  1664.  
  1665. | | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | |
  1666. |---|--------------------|--------------------------|--------------------|-------------------------|-------------------------|-----------------------------|----------------------------|----------------------------|----------------------------|-----------------------------|----------------------------|---------------------------|------------|----------------------------------|------------------|--------------------------|---------------------|---------------------------------|-------------|-------------------|-------------------|---|
  1667. | A | VSS | LVD<br>S_D2<br>_N | LVD<br>S_CL<br>K_N | LVD<br>S_D1<br>_N | LVD<br>S_D0<br>_N | MIPI<br>_DSI<br>1_D0<br>_N | MIPI<br>_DSI<br>1_D1<br>_N | MIPI<br>_DSI<br>1_D2<br>_N | MIPI<br>_DSI<br>1_D3<br>_N | MIPI<br>_CSI<br>1_D1<br>_N | MIPI<br>_CSI<br>1_D0<br>_N | NC_<br>A12 | NC_<br>A13 | USB<br>1_D_<br>N | USB<br>2_D_<br>N | POR<br>_B | PMIC<br>_ON_<br>REQ | CLKI<br>N2 | ONO<br>FF | ADC<br>_IN1 | VSS | A |
  1668. | B | LVD<br>S_D3<br>_N | LVD<br>S_D2<br>_P | LVD<br>S_CL<br>K_P | LVD<br>S_D1<br>_P | LVD<br>S_D0<br>_P | MIPI<br>_DSI<br>1_D0<br>_P | MIPI<br>_DSI<br>1_D1<br>_P | MIPI<br>_DSI<br>1_D2<br>_P | MIPI<br>_DSI<br>1_D3<br>_P | MIPI<br>_CSI<br>1_D1<br>_P | MIPI<br>_CSI<br>1_D0<br>_P | NC_<br>B12 | NC_<br>B13 | USB<br>1_D_<br>P | USB<br>2_D_<br>P | TAM<br>PER<br>0 | CLKI<br>N1 | PMIC<br>_STB<br>Y_R<br>EQ | ADC<br>_IN0 | ADC<br>_IN2 | ADC<br>_IN3 | B |
  1669. | C | LVD<br>S_D3<br>_P | VSS | | VSS | | VSS | | VSS | | VSS | USB<br>1_ID | VSS | | VSS | | VSS | | VSS | | I2C1<br>_SCL | I2C1<br>_SD<br>A | C |
  1670. | D | DRA<br>M_C<br>A5_A | DRA<br>M_R<br>ESE<br>T_N | | DRA<br>M_M<br>TES<br>T1 | | MIPI<br>_DSI<br>1_CL<br>K_N | | MIPI<br>_RE<br>XT | | MIPI<br>_CSI<br>1_CL<br>K_N | | USB<br>1_TX<br>RTU<br>NE | | USB<br>2_TX<br>RTU<br>NE | | RXC<br>_XTA<br>LO | | XTAL<br>I_24<br>M | | I2C2<br>_SCL | I2C2<br>_SD<br>A | D |
  1671. | E | DRA<br>M_C<br>A3_A | DRA<br>M_C<br>A4_A | VSS | DRA<br>M_Z<br>Q | | MIPI<br>_DSI<br>1_CL<br>K_P | | VDD<br>_US<br>B_1P<br>8 | | MIPI<br>_CSI<br>1_CL<br>K_P | | USB<br>2_ID | | USB<br>2_VB<br>US | | RTC<br>_XTA<br>LI | | XTAL<br>O_24<br>M | VSS | UAR<br>T1_R<br>XD | UAR<br>T1_T<br>XD | E |
  1672. | F | DRA<br>M_C<br>S0_A | DRA<br>M_C<br>A2_A | | | | VDD<br>_LVD<br>S_1P<br>8 | | VDD<br>_MIP<br>I_1P<br>8 | | VDD<br>_US<br>B_0P<br>8 | | USB<br>1_VB<br>US | | TAM<br>PER<br>1 | | VDD<br>_AN<br>A0_1<br>P8 | | | | UAR<br>T2_R<br>XD | UAR<br>T2_T<br>XD | F |
  1673. | G | DRA<br>M_C<br>A1_A | DRA<br>M_C<br>S1_A | VSS | DRA<br>M_C<br>K_T_<br>A | DRA<br>M_C<br>K_C_<br>A | VDD<br>Q_D<br>DR | | VDD<br>_MIP<br>I_0P<br>8 | | VDD<br>_US<br>B_3P<br>3 | | NVC<br>C_B<br>BSM<br>_1P8 | | VDD<br>_BBS<br>M_0<br>P8_C<br>AP | | VDD<br>_AN<br>A0_1<br>P8 | PDM<br>_CLK | PDM<br>_BIT<br>_STR<br>EAM<br>1 | VSS | SAI1<br>_TXC | SAI1<br>_TXF | G |
  1674.  
  1675. | | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | |
  1676. |---|-------------------------|-------------------------|-----|---------------------------|-----|------------------|------------------|-----|-----------------|-----------------|-----------------|-----------------|-----------------|-----|---------------------------------|-------------------------|---------------------------------|-------------------|-----|-------------------|-------------------|---|
  1677. | H | DRA<br>M_C<br>KE0_<br>A | DRA<br>M_C<br>A0_A | | | | | | VSS | | VSS | | VSS | | VSS | | | | | | SAI1<br>_RX<br>D0 | SAI1<br>_TXD<br>0 | H |
  1678. | J | DRA<br>M_D<br>Q06_<br>A | DRA<br>M_D<br>Q07_<br>A | VSS | DRA<br>M_C<br>KE1_<br>A | VSS | VDD<br>Q_D<br>DR | VDD<br>Q_D<br>DR | VSS | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VSS | VDD<br>_AN<br>A_0P<br>8 | VDD<br>_AN<br>A_0P<br>8 | PDM<br>_BIT<br>_STR<br>EAM<br>0 | WDO<br>G_A<br>NY | VSS | GPIO<br>_IO0<br>1 | GPIO<br>_IO0<br>0 | J |
  1679. | K | DRA<br>M_D<br>Q04_<br>A | DRA<br>M_D<br>Q05_<br>A | | | | | | | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VSS | VDD<br>_SO<br>C | VDD<br>_SO<br>C | | | | | | | GPIO<br>_IO0<br>2 | GPIO<br>_IO0<br>3 | K |
  1680. | L | VSS | DRA<br>M_D<br>MI0_<br>A | VSS | DRA<br>M_D<br>QS0_<br>C_A | VSS | VDD<br>Q_D<br>DR | VDD<br>2_DD<br>R | VSS | | | | | | VSS | VDD<br>_AN<br>AVD<br>ET_1<br>P8 | NVC<br>C_A<br>ON | GPIO<br>_IO0<br>4 | GPIO<br>_IO0<br>5 | VSS | GPIO<br>_IO0<br>6 | GPIO<br>_IO0<br>7 | L |
  1681. | M | DRA<br>M_D<br>Q02_<br>A | DRA<br>M_D<br>Q03_<br>A | | | | | | | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VSS | VDD<br>_SO<br>C | VDD<br>_SO<br>C | | | | | | | GPIO<br>_IO0<br>8 | GPIO<br>_IO0<br>9 | M |
  1682. | N | DRA<br>M_D<br>Q00_<br>A | DRA<br>M_D<br>Q01_<br>A | VSS | DRA<br>M_D<br>QS0_<br>T_A | VSS | VDD<br>2_DD<br>R | VDD<br>2_DD<br>R | VSS | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VDD<br>_SO<br>C | VSS | NVC<br>C_G<br>PIO | NVC<br>C_G<br>PIO | GPIO<br>_IO1<br>0 | GPIO<br>_IO1<br>1 | VSS | GPIO<br>_IO1<br>2 | GPIO<br>_IO1<br>3 | N |
  1683.  
  1684. | | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | |
  1685. |---|-------------------------|-------------------------------|-------------------|---------------------------|---------------------------|--------------------------|-------------------|--------------------------|-------------------|--------------------------|-------------------|-------------------------|-------------------|-------------------------|-------------------|-------------------|-------------------|-------------------------|-------------|-------------------|-------------------|---|
  1686. | P | DRA<br>M_D<br>Q15_<br>A | DRA<br>M_D<br>Q14_<br>A | | | | | | VSS | | VSS | | VSS | | VSS | | | | | | GPIO<br>_IO1<br>4 | GPIO<br>_IO1<br>5 | P |
  1687. | R | DRA<br>M_D<br>Q12_<br>A | DRA<br>M_D<br>Q13_<br>A | VSS | DRA<br>M_D<br>QS1_<br>T_A | DRA<br>M_D<br>QS1_<br>C_A | VDD<br>2_DD<br>R | | VDD<br>_AN<br>A1_1<br>P8 | | NVC<br>C_W<br>AKE<br>UP | | NVC<br>C_W<br>AKE<br>UP | | VDD<br>_AN<br>A_0P<br>8 | | NVC<br>C_S<br>D2 | GPIO<br>_IO1<br>9 | GPIO<br>_IO1<br>8 | VSS | GPIO<br>_IO1<br>7 | GPIO<br>_IO1<br>6 | R |
  1688. | T | VSS | DRA<br>M_D<br>MI1_<br>A | | | | VDD<br>2_DD<br>R | | ENE<br>T2_T<br>D0 | | ENE<br>T2_T<br>D3 | | ENE<br>T1_T<br>D1 | | SD3_<br>DAT<br>A3 | | SD3_<br>DAT<br>A0 | | | | GPIO<br>_IO2<br>0 | GPIO<br>_IO2<br>1 | T |
  1689. | U | DRA<br>M_D<br>Q11_<br>A | DRA<br>M_D<br>Q10_<br>A | VSS | CCM<br>_CLK<br>O3 | | ENE<br>T2_T<br>XC | | ENE<br>T2_T<br>D1 | | ENE<br>T1_T<br>XC | | ENE<br>T1_T<br>D2 | | SD3_<br>DAT<br>A2 | | SD3_<br>CMD | | GPIO<br>_IO2<br>2 | VSS | GPIO<br>_IO2<br>3 | GPIO<br>_IO2<br>4 | U |
  1690. | V | DRA<br>M_D<br>Q08_<br>A | DRA<br>M_D<br>Q09_<br>A | | CCM<br>_CLK<br>O4 | | ENE<br>T2_T<br>X_CT<br>L | | ENE<br>T2_T<br>D2 | | ENE<br>T1_T<br>X_CT<br>L | | ENE<br>T1_T<br>D3 | | SD3_<br>DAT<br>A1 | | SD3_<br>CLK | | SD2_<br>VSE<br>LEC<br>T | | GPIO<br>_IO2<br>6 | GPIO<br>_IO2<br>5 | V |
  1691. | W | DAP<br>_TDI | DAP<br>_TM<br>S_S<br>WDI<br>O | | VSS | | VSS | | NVC<br>C_W<br>AKE<br>UP | | VSS | ENE<br>T1_T<br>D0 | VSS | | VSS | | VSS | | VSS | | GPIO<br>_IO2<br>8 | GPIO<br>_IO2<br>7 | W |
  1692. | Y | DAP<br>_TCL<br>K_S | DAP<br>_TD<br>O_T | CCM<br>_CLK<br>O2 | ENE<br>T2_R | ENE<br>T2_R<br>D1 | ENE<br>T2_R<br>D3 | ENE<br>T2_M<br>DC | ENE<br>T1_R | ENE<br>T1_R<br>D1 | ENE<br>T1_R<br>D3 | SD1_<br>CLK | SD1_<br>STR<br>OBE | SD1_<br>DAT<br>A4 | SD1_<br>DAT<br>A5 | SD1_<br>DAT<br>A6 | SD1_<br>DAT<br>A7 | SD2_<br>CD_<br>B | SD2_<br>DAT<br>A0 | SD2_<br>CMD | SD2_<br>DAT<br>A2 | GPIO<br>_IO2<br>9 | Y |
  1693.  
  1694. | Table 102. | | | 14 x 14 mm, 0.65 mm pitch, ball map | continued |
  1695. |------------|--|--|-------------------------------------|-----------|
  1696. |------------|--|--|-------------------------------------|-----------|
  1697.  
  1698. | | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | |
  1699. |----|----------|-------------------|-------------------|-------------------|-------------------|--------------------|-------------------|-------------------|-------------------|--------------------|-------------------|-------------|-------------------|-------------------|-------------------|-------------------|---------------------|-------------------|-------------|-------------------|-----|----|
  1700. | | WCL<br>K | RAC<br>ESW<br>O | | X_CT<br>L | | | | X_CT<br>L | | | | | | | | | | | | | | |
  1701. | AA | VSS | CCM<br>_CLK<br>O1 | ENE<br>T2_R<br>XC | ENE<br>T2_R<br>D0 | ENE<br>T2_R<br>D2 | ENE<br>T2_M<br>DIO | ENE<br>T1_R<br>XC | ENE<br>T1_R<br>D0 | ENE<br>T1_R<br>D2 | ENE<br>T1_M<br>DIO | ENE<br>T1_M<br>DC | SD1_<br>CMD | SD1_<br>DAT<br>A3 | SD1_<br>DAT<br>A0 | SD1_<br>DAT<br>A1 | SD1_<br>DAT<br>A2 | SD2_<br>RES<br>ET_B | SD2_<br>DAT<br>A1 | SD2_<br>CLK | SD2_<br>DAT<br>A3 | VSS | AA |
  1702. | | 1 | 2 | | 3 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | |
  1703.  
  1704. | Ball name | LPDDR4/LPDDR4x |
  1705. |---------------|----------------|
  1706. | DRAM_DQS0_T_A | DQSA_T[0] |
  1707. | DRAM_DQS0_C_A | DQSA_C[0] |
  1708. | DRAM_DMI0_A | DM/DBIA[0] |
  1709. | DRAM_DQ00_A | DQA[0] |
  1710. | DRAM_DQ01_A | DQA[1] |
  1711. | DRAM_DQ02_A | DQA[2] |
  1712. | DRAM_DQ03_A | DQA[3] |
  1713. | DRAM_DQ04_A | DQA[4] |
  1714. | DRAM_DQ05_A | DQA[5] |
  1715. | DRAM_DQ06_A | DQA[6] |
  1716. | DRAM_DQ07_A | DQA[7] |
  1717. | DRAM_DQS1_T_A | DQSA_T[1] |
  1718. | DRAM_DQS1_C_A | DQSA_C[1] |
  1719. | DRAM_DMI1_A | DM/DBIA[1] |
  1720. | DRAM_DQ08_A | DQA[8] |
  1721. | DRAM_DQ09_A | DQA[9] |
  1722. | DRAM_DQ10_A | DQA[10] |
  1723. | DRAM_DQ11_A | DQA[11] |
  1724. | DRAM_DQ12_A | DQA[12] |
  1725. | DRAM_DQ13_A | DQA[13] |
  1726. | DRAM_DQ14_A | DQA[14] |
  1727. | DRAM_DQ15_A | DQA[15] |
  1728. | DRAM_RESET_N | RESET_N |
  1729.  
  1730. | | | | | | | Table 103. DDR pin function list continued |
  1731. |--|--|--|--|--|--|--------------------------------------------|
  1732. |--|--|--|--|--|--|--------------------------------------------|
  1733.  
  1734. | DRAM_MTRST1 | — |
  1735. |-------------|---------|
  1736. | DRAM_CKE0_A | CKEA[0] |
  1737. | DRAM_CKE1_A | CKEA[1] |
  1738. | DRAM_CS0_A | CSA[0] |
  1739. | DRAM_CS1_A | CSA[1] |
  1740. | DRAM_CK_T_A | CLKA_T |
  1741. | DRAM_CK_C_A | CLKA_C |
  1742. | DRAM_CA0_C | CAA[0] |
  1743. | DRAM_CA1_C | CAA[1] |
  1744. | DRAM_CA2_C | CAA[2] |
  1745. | DRAM_CA3_C | CAA[3] |
  1746. | DRAM_CA4_C | CAA[4] |
  1747. | DRAM_CA5_C | CAA[5] |
  1748. | DRAM_ZQ1 | — |
  1749.  
  1750. | Table 104. i.MX 93 Data Sheet document revision history | | |
  1751. |---------------------------------------------------------|--|--|
  1752. |---------------------------------------------------------|--|--|
  1753.  
  1754. | Rev.<br>Number | Date | Substantive Change(s) |
  1755. |----------------|-----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
  1756. | IMX93AEC v.6.1 | 07 July<br>2025 | • Removed the I/O pin information from Ordering information<br>• Updated the Package type in Figure 1<br>• Removed Section 9 x 9 mm package information |
  1757. | IMX93AEC v.6.0 | 04 June<br>2025 | • Updated Ordering information<br>• Updated Figure 1<br>• Updated the descriptions about DRAM and LPUART, and ADC in Table 1; Removed<br>FlexIO from Table 1<br>• Added LPDDR4 in Figure 2; updated ADC and LPUART in Figure 2 |
  1758.  
  1759. | Rev.<br>Number | Date | Substantive Change(s) |
  1760. |----------------|---------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
  1761. | | | • Updated the description about ONOFF and XTALI_24/XTALO_24M in Table 3 |
  1762. | | | • Added Table 11 |
  1763. | | | • Updated Table 15 |
  1764. | | | • Updated Table 27 |
  1765. | | | • Updated the description of DDR SDRAM–specific parameters (LPDDR4/LPDDR4X) and<br>Clock/data/command/address pin allocations |
  1766. | | | • Added a footnote in Table 43 |
  1767. | | | • Added a footnote in Table 50 |
  1768. | | | • Updated the unit of Csample, Ccompare, and Cconversion to cycle in Table 51; removed the<br>maximum value of Ccompare and second ADC clock in Table 51; added ENOB lavues in<br>Table 51 |
  1769. | | | • Removed Table. ADC electrical specifications (VREFH = VDD_ANAx_1p8 and<br>VADINmax ≤ VREFH) |
  1770. | | | • Added a footnote in Table 68 |
  1771. | | | • Updated Table 71 |
  1772. | | | • Removed BCAN, BCANXL, and minimum operating frequency from Table 72 |
  1773. | | | • Added the maximum frequency footnotes in FlexSPI timing parameters |
  1774. | | | • Updated LPB descriptions in Boot mode configuration |
  1775. | Rev. 5 | 01/2025 | • Added new part number in Table 2 |
  1776. | | | • Updated the definition of special fuse in Figure 1 |
  1777. | | | • Removed Module list |
  1778. | | | • Updated the descriptions of External clock sources |
  1779. | | | • Updated the NVCC_BBSM_1P8 in Figure 4 |
  1780. | | | • Updated the footnote of Table 29 |
  1781. | | | • Updated the values of VIDTH, VIDTL, VIHHS, and VIHHS in Table 36 |
  1782. | | | • Updated Figure 50 |
  1783. | | | • Updated the default function of SAI1_RXD0 in Table 101 |
  1784. | Rev. 4 | 08/2024 | • Updated Table 2 |
  1785. | | | • Updated Figure 1 |
  1786. | | | • Updated Clock sources |
  1787. | | | • Added a footnote in Figure 4 |
  1788. | | | • Updated Table 24 and Table 25 |
  1789. | | | • Updated Table 26 and Table 28 |
  1790.  
  1791. | Rev.<br>Number | Date | Substantive Change(s) |
  1792. |----------------|---------|----------------------------------------------------------------------------------------------------------------------|
  1793. | | | • Updated JTAG timing parameters |
  1794. | | | • Updated descriptions and a table footnote in SWD timing parameters |
  1795. | | | • Updated descriptions and a footnote in LCD Controller (LCDIF) timing parameters |
  1796. | | | • Updated descriptions and footnotes in SAI switching specifications |
  1797. | | | • Updated descriptions of SPDIF timing parameters |
  1798. | | | • Updated footnotes, descriptions, and Figure 25 in Ultra-high-speed SD/SDIO/MMC host<br>interface (uSDHC) AC timing |
  1799. | | | • Updated descriptions and footnotes in Table 60, Table 61, Table 62, Table 63, and Table<br>64 |
  1800. | | | • Updated descriptions and footnotes in Table 61, Table 62, |
  1801. | | | • Updated descriptions and footnotes in LPSPI timing parameters |
  1802. | | | • Updated Improved Inter-Integrated Circuit Interface (I3C) specifications |
  1803. | | | • Updated descriptions of CAN network AC electrical specifications |
  1804. | | | • Updated descriptions of Timer/Pulse width modulator (TPM) timing parameters |
  1805. | | | • Updated descriptions in FlexSPI timing parameters |
  1806. | | | • Updated descriptions and a footnote in Flexible I/O controller (FlexIO) electrical<br>specifications |
  1807. | | | • Updated Table 92 |
  1808. | Rev. 3 | 12/2023 | • Updated Table 2. Ordering information |
  1809. | | | • Added information about FlexIO in Table i.MX 93 modules list |
  1810. | | | • Updated Figure 1, "Part number nomenclature—i.MX 93" |
  1811. | | | • Updated Figure 2 |
  1812. | | | • Updated Table 4. Special signal considerations |
  1813. | | | • Updated Table 9. Absolute maximum ratings |
  1814. | | | • Updated Table 10. Electrostatic discharge and latch up ratings |
  1815. | | | • Added Section 4.1.2.3, 14 x 14 mm FCBGA package thermal characteristics |
  1816. | | | • Updated Table 14. Operating ranges |
  1817. | | | • Added Table 17. External clock frequency |
  1818. | | | • Updated the current values in Table 21. Maximum supply currents |
  1819. | | | • Added a note in Section 4.2.1, Power mode definition |
  1820. | | | • Updated Table 22. The power supply states |
  1821. | | | • Added footnotes in Table 23. Low power mode definition |
  1822. | | | • Added Table 24. Chip power in different LP modes |
  1823.  
  1824. | Rev.<br>Number | Date | Substantive Change(s) | |
  1825. |----------------|---------|-------------------------------------------------------------------------------------------------------------------|--|
  1826. | | | • Updated Table 26. GPIO DC parameters, Table 27. Additional leakage parameters, and<br>Table 27 | |
  1827. | | | • Updated the operating frequency in Table 30. LVDS AC parameters | |
  1828. | | | • Updated ENOB values in Table 54. ADC electrical specificatins (VREFTH =<br>VDDA_ANAx_1P8 and VADINmax ≤VREFH | |
  1829. | | | • Updated Section 4.12.9, FlexSPI timing parameters | |
  1830. | | | • Update the signal name of RMII_RX_ER in Table 63. ENET2 signal mapping and Table 67.<br>ENET QOS signal mapping | |
  1831. | | | • Updated the naming of ENET_CLK to RMII_REF_CLK, ENET_TD, and ENET_RD in<br>Section 4.12.2.2, RMII mode timing | |
  1832. | | | • Removed USB 3.0 information from Section 4.12.12, USB PHY parameters | |
  1833. | | | • Added 14 x 14 mm package information | |
  1834. | Rev. 2 | 08/2023 | • Updated the term "Consumer" to "Commercial" | |
  1835. | | | • Updated JTAG pin description in Table 1 | |
  1836. | | | • Updated Table 2. Ordering information | |
  1837. | | | • Updated remarks in Table 4. Special signal considerations | |
  1838. | | | • Added ADC and TAMPER pin information in Table 5. Unused function<br>strapping recommendations | |
  1839. | | | • Updated NVCC_BBSM_1P8 description in Section 4.1.3, Power architecture | |
  1840. | | | • Updated descriptions in Section 4.1.6.1, External clock sources | |
  1841. | | | • Updated Figure 7, "Output transition time waveform" | |
  1842. | | | • Updated Table 26. GPIO DC parameters and Table 27. Additional leakage parameters | |
  1843. | | | • Removed JTAG_TRST information from Section 4.8.3, JTAG timing parameters | |
  1844. | | | • Updated Table 63. ENET2 signal mapping and Table 67. ENET QOS signal mapping | |
  1845. | | | • Updated footnotes of Table 68 and Table 69 | |
  1846. | | | • Updated Table 98. Fuses and associated pins used for boot | |
  1847. | Rev. 1 | 04/2023 | • Initial version | |
  1848.  
  1849. | Document status[1][2] | Product status[3] | Definition | | |
  1850. |--------------------------------|-------------------|------------------------------------------------------------------------------------------|--|--|
  1851. | Objective [short] data sheet | Development | This document contains data from the objective specification for product<br>development. | | |
  1852. | Preliminary [short] data sheet | Qualification | This document contains data from the preliminary specification. | | |
  1853. | Product [short] data sheet | Production | This document contains the product specification. | | |
  1854.  
  1855. | 1 | i.MX 93 introduction2 |
  1856. |-------|------------------------------------------------|
  1857. | 1.1 | Ordering information5 |
  1858. | 2 | Block diagram7 |
  1859. | 3 | Special signal considerations 8 |
  1860. | 3.1 | Unused input and output guidance9 |
  1861. | 4 | Electrical characteristics10 |
  1862. | 4.1 | Chip-level conditions 11 |
  1863. | 4.1.1 | Absolute maximum ratings 11 |
  1864. | 4.1.2 | Thermal resistance12 |
  1865. | 4.1.3 | Power architecture 13 |
  1866. | 4.1.4 | Operating ranges15 |
  1867. | 4.1.5 | Maximum frequency of main modules16 |
  1868. | 4.1.6 | Clock sources16 |
  1869. | 4.1.7 | Maximum supply currents 18 |
  1870. | 4.2 | Power modes 19 |
  1871. | 4.2.1 | Power mode definition19 |
  1872. | 4.2.2 | Low power modes 20 |
  1873. | 4.2.3 | Chip power in different Low Power modes21 |
  1874. | 4.3 | Power supplies requirements and restrictions22 |
  1875. | 4.3.1 | Power-up sequence 23 |
  1876. | 4.3.2 | Power-down sequence23 |
  1877. | 4.4 | PLL electrical characteristics24 |
  1878. | 4.5 | I/O DC parameters 24 |
  1879. | 4.5.1 | General purpose I/O (GPIO) DC parameters 24 |
  1880. | 4.5.2 | DDR I/O DC electrical characteristics 25 |
  1881. | 4.5.3 | LVDS DC parameters26 |
  1882. | 4.6 | I/O AC parameters 26 |
  1883. | 4.6.1 | General purpose I/O (GPIO) AC parameters 27 |
  1884. | 4.6.2 | DDR I/O AC electrical characteristics29 |
  1885. | 4.6.3 | LVDS AC Parameters 29 |
  1886. | 4.7 | Differential I/O output buffer impedance31 |
  1887. | 4.7.1 | DDR I/O output impedance 31 |
  1888. | 4.8 | System modules timing 31 |
  1889. | 4.8.1 | Reset timing parameters 31 |
  1890. | 4.8.2 | WDOG Reset timing parameters31 |
  1891. | 4.8.3 | JTAG timing parameters 32 |
  1892. | 4.8.4 | SWD timing parameters 33 |
  1893. | 4.8.5 | DDR SDRAM–specific parameters (LPDDR4/ |
  1894. | | LPDDR4X)34 |
  1895. | 4.9 | Display and graphics 35 |
  1896. | 4.9.1 | MIPI D-PHY electrical characteristics35 |
  1897. | 4.9.2 | LCD Controller (LCDIF) timing parameters 38 |
  1898.  
  1899. | 4.10 | Audio 39 | |
  1900. |---------|---------------------------------------------------|--|
  1901. | 4.10.1 | SAI switching specifications 39 | |
  1902. | 4.10.2 | SPDIF timing parameters 42 | |
  1903. | 4.10.3 | PDM Microphone interface timing parameters 43 | |
  1904. | 4.10.4 | Medium Quality Sound (MQS) electrical | |
  1905. | | specifications44 | |
  1906. | 4.11 | Analog 45 | |
  1907. | 4.11.1 | 12-bit ADC electrical specifications 45 | |
  1908. | 4.11.2 | 12-bit ADC input impedance equivalent circuit | |
  1909. | | diagram 46 | |
  1910. | 4.12 | External peripheral interface parameters 47 | |
  1911. | 4.12.1 | Ultra-high-speed SD/SDIO/MMC host interface | |
  1912. | | (uSDHC) AC timing 47 | |
  1913. | 4.12.2 | Ethernet controller (ENET) AC electrical | |
  1914. | | specifications55 | |
  1915. | 4.12.3 | Ethernet Quality-of-Service (QOS) electrical | |
  1916. | | specifications58 | |
  1917. | 4.12.4 | LPSPI timing parameters 62 | |
  1918. | 4.12.5 | LPI2C timing parameters66 | |
  1919. | 4.12.6 | Improved Inter-Integrated Circuit Interface (I3C) | |
  1920. | | specifications66 | |
  1921. | 4.12.7 | CAN network AC electrical specifications 68 | |
  1922. | 4.12.8 | Timer/Pulse width modulator (TPM) timing | |
  1923. | | parameters 69 | |
  1924. | 4.12.9 | FlexSPI timing parameters 70 | |
  1925. | 4.12.10 | LPUART I/O configuration and timing parameters | |
  1926. | | 77 | |
  1927. | 4.12.11 | Flexible I/O controller (FlexIO) electrical | |
  1928. | | specifications77 | |
  1929. | 4.12.12 | USB PHY parameters 78 | |
  1930. | 5 | Boot mode configuration 78 | |
  1931. | 5.1 | Boot mode configuration pins78 | |
  1932. | 5.2 | Boot device interface allocation80 | |
  1933. | 6 | Package information and contact assignments82 | |
  1934. | 6.1 | 14 x 14 mm package information 82 | |
  1935. | 6.1.1 | 14 x 14 mm, 0.65 mm pitch, ball matrix83 | |
  1936. | 6.1.2 | 14 x 14 mm supplies contact assignments and | |
  1937. | | functional contact assignments 85 | |
  1938. | 6.1.3 | 14 x 14 mm, 0.65 mm pitch, ball map 95 | |
  1939. | 6.2 | DDR pin function list100 | |
  1940. | 7 | Revision history 101 | |
  1941. | | Legal information105 | |
Advertisement
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!