Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- module booth_modificat
- #( parameter OPERAND_BITS = 8,
- parameter RESULT_BITS = 16)
- (
- input clk,
- input rst,
- input [OPERAND_BITS - 1 : 0] a,
- input [OPERAND_BITS - 1 : 0] b,
- input start,
- output[RESULT_BITS - 1 : 0] result,
- output reg ovr
- );
- reg f;
- reg [OPERAND_BITS-1 : 0] A;
- reg [OPERAND_BITS : 0] Q;
- reg Q_1;
- reg [OPERAND_BITS-1 : 0] M;
- reg [2:0] count;
- reg [3:0] state;
- localparam [3:0] s0=4'd0, s1=4'd1, s2=4'd2, s3=4'd3, s4=4'd4, s5=4'd5, s6=4'd6, s7=4'd7, s8=4'd8, s9=4'd9;
- // sequential process
- always
- @(posedge clk, posedge rst)
- begin
- if (rst)
- begin
- state <= s0;
- A <= 0;
- Q <= 0;
- M <= 0;
- Q_1 <= 0;
- count <= 0;
- end
- else
- begin
- case(state)
- s0: begin
- if(start)
- state <= s1;
- end
- s1:
- begin
- A <= 0;
- count <= 0;
- f <= 0;
- ovr <= 0;
- M <= a;
- Q <= b[7:0];
- Q_1 <= b[0];
- state <= s2;
- end
- s2:
- begin
- if(Q == 9'd0)
- state <= s9;
- else if(M == 8'd0)
- state <= s3;
- else
- state <= s4;
- end
- s3:
- begin
- Q <= 0;
- Q_1 <= 0;
- state <= s9;
- end
- s4:
- begin
- if(f == 1'b0)
- begin
- if({Q[0],Q[1]} == 2'b01)
- begin
- A <= A + M;
- ovr <= 1'b1;
- end
- else if({Q[0],Q[1]} == 2'b11)
- begin
- A <= A - M;
- ovr <= 1'b1;
- f <= 1'b1;
- end
- end
- else
- begin
- if({Q[0],Q[1]} == 2'b00)
- begin
- A <= A + M;
- ovr <= 1'b1;
- f <= 1'b0;
- end
- else if({Q[0],Q[1]} == 2'b10)
- begin
- A <= A - M;
- ovr <= 1'b1;
- end
- end
- if(count == 2'd7)
- state <= s9;
- else
- state <= s8;
- end
- s8:
- begin
- A[7] <= (A[7] && M[7] && !ovr) || (f && !M[7]) || (f && M[7] && ovr);
- //{A[7:1], Q} <= {A, Q[6:0], Q_1};
- //{Q, A[7:1]} <= {Q[6:0], Q_1, A};
- //A[7]={{A[7],M[7]},~(ovr)} + {{f,~(M[7])},ovr};
- {A[6:0],Q}={A,Q[8:1]};
- count <= count + 1'b1;
- state <= s4;
- end
- s9:
- begin
- Q[1] <= 0;
- end
- endcase
- end
- end
- assign result = {A, Q, Q_1};
- endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement