// arith_machine: execute a series of arithmetic instructions from an instruction cache
//
// except (output) - set to 1 when an unrecognized instruction is to be executed.
// clock  (input)  - the clock signal
// reset  (input)  - set to 1 to set all registers to zero, set to 0 for normal execution.

module arith_machine(except, clock, reset);
    output      except;
    input       clock, reset;

    wire [31:0] inst;
    wire [31:0] PC;
    //comments following prairie learn hw convention
    wire [31:0] nextPC, rsData, rtData, B, imm_32, zero_32, rdData;
    wire [4:0] rDest;
    wire [2:0] alu_op;
    wire [1:0] alu_src2;
    wire write_enable, rd_src, overflow, zero, negative;

    // DO NOT comment out or rename this module
    // or the test bench will break
    register #(32) PC_reg(PC, nextPC, clock, 1'b1, reset);

    alu32 alu_1(nextPC, , , , PC, 32'h4, `ALU_ADD);

    // DO NOT comment out or rename this module
    // or the test bench will break
    instruction_memory im(inst[31:0], PC[31:2]);

    mux2v #(5) mux_1(rDest, inst[15:11], inst[20:16], rd_src);

    // DO NOT comment out or rename this module
    // or the test bench will break
    regfile rf (rsData, rtData, inst[25:21], inst[20:16], rDest, rdData, write_enable, clock, reset);

    /* add other modules */

    sign_extender sign(imm_32, inst[15:0]);
    zero_extender zeroExtend(zero_32, inst[15:0]);

    mips_decode decoder(rd_src, write_enable, alu_src2, alu_op, except, inst[31:26], inst[5:0]);

    mux3v mux_2(B, rtData, imm_32, zero_32, alu_src2);
    alu32 alu_2(rdData, overflow, zero, negative, rsData, B, alu_op);
endmodule // arith_machine

module sign_extender(imm, inst);
  input [15:0] inst;
  output [31:0] imm;

  assign imm[15:0] = inst[15:0];
  assign imm[31:16] = inst[15];
  /*
  assign imm[16] = inst[15];
  assign imm[17] = inst[15];
  assign imm[18] = inst[15];
  assign imm[19] = inst[15];
  assign imm[20] = inst[15];
  assign imm[21] = inst[15];
  assign imm[22] = inst[15];
  assign imm[23] = inst[15];
  assign imm[24] = inst[15];
  assign imm[25] = inst[15];
  assign imm[26] = inst[15];
  assign imm[27] = inst[15];
  assign imm[28] = inst[15];
  assign imm[29] = inst[15];
  assign imm[30] = inst[15];
  assign imm[31] = inst[15];
  */
endmodule // sign_extender

module zero_extender(zero, inst);
  input [15:0] inst;
  output [31:0] zero;

  assign zero[15:0] = inst[15:0];
  assign zero[31:16] = 0;

  /*assign zero[17] = 0;
  assign zero[18] = 0;
  assign zero[19] = 0;
  assign zero[20] = 0;
  assign zero[21] = 0;
  assign zero[22] = 0;
  assign zero[23] = 0;
  assign zero[24] = 0;
  assign zero[25] = 0;
  assign zero[26] = 0;
  assign zero[27] = 0;
  assign zero[28] = 0;
  assign zero[29] = 0;
  assign zero[30] = 0;
  assign zero[31] = 0;
  */
endmodule // zero_extender