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vedic_div32.syr.683ce2a0e831248a3b014bc382823023a0a724f5

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May 11th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.08 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.08 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Off
  74. Reduce Control Sets : Off
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 1
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" in Library work.
  115. Architecture rtl of Entity vedic_div32 is up to date.
  116.  
  117. =========================================================================
  118. * Design Hierarchy Analysis *
  119. =========================================================================
  120. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  121.  
  122.  
  123. =========================================================================
  124. * HDL Analysis *
  125. =========================================================================
  126. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  127. WARNING:Xst:2096 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 84: Use of null array slice on signal <d_init_re_reg> is not supported.
  128. WARNING:Xst:2096 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 85: Use of null array slice on signal <init_reg.re_reg> is not supported.
  129. INFO:Xst:2679 - Register <d_init_quo_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  130. INFO:Xst:2679 - Register <init_reg.re_reg<35>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  131. INFO:Xst:2679 - Register <init_reg.re_reg<34>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  132. INFO:Xst:2679 - Register <init_reg.re_reg<33>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  133. INFO:Xst:2679 - Register <init_reg.re_reg<32>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  134. INFO:Xst:2679 - Register <init_reg.re_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  135. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  136.  
  137.  
  138. =========================================================================
  139. * HDL Synthesis *
  140. =========================================================================
  141.  
  142. Performing bidirectional port resolution...
  143.  
  144. Synthesizing Unit <vedic_div32>.
  145. Related source file is "/home/calros/enshu3-vedicdivider/vedic_div32.vhd".
  146. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  147. WARNING:Xst:646 - Signal <d_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  148. WARNING:Xst:646 - Signal <d_re_tmp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  149. WARNING:Xst:646 - Signal <d_re> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  150. WARNING:Xst:646 - Signal <d_main_re_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  151. WARNING:Xst:1780 - Signal <d_init_re_reg<31>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  152. WARNING:Xst:646 - Signal <d_init_re_reg<30:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  153. WARNING:Xst:646 - Signal <d_init_quo_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  154. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  155. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  156. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  157. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  158. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  159. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  160. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  161. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  162. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  163. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  164. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  165. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  166. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  167. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  168. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  169. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  170. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  171. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  172. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  173. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  174. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  175. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  176. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  177. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  178. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  179. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  180. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  181. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  182. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  183. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  184. Found finite state machine <FSM_0> for signal <state>.
  185. -----------------------------------------------------------------------
  186. | States | 4 |
  187. | Transitions | 9 |
  188. | Inputs | 3 |
  189. | Outputs | 4 |
  190. | Clock | mclk1 (rising_edge) |
  191. | Reset | state$and0000 (positive) |
  192. | Reset type | synchronous |
  193. | Reset State | fin_state |
  194. | Power Up State | init_state |
  195. | Encoding | automatic |
  196. | Implementation | LUT |
  197. -----------------------------------------------------------------------
  198. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  199. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  200. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  201. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  202. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  203. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  204. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  205. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  206. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  207. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  208. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  209. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  210. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  211. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  212. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  213. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  214. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  215. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  216. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  217. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  218. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  219. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  220. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  221. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  222. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  223. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  224. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  225. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  226. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  227. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  228. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  229. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  230. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  231. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  232. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  233. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  234. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  235. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  236. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  237. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  238. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  239. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  240. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  241. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  242. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  243. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  244. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  245. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  246. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  247. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  248. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  249. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  250. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  251. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  252. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  253. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  254. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  255. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_31>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  256. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  257. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  258. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  259. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  260. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  261. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  262. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  263. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 123: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  264. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  265. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  266. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  267. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  268. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  269. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  270. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  271. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  272. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 122: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  273. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  274. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  275. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  276. Found 34x4-bit multiplier for signal <$mult0000> created at line 207.
  277. Found 34x5-bit multiplier for signal <$mult0001> created at line 207.
  278. Found 34x4-bit multiplier for signal <$mult0002> created at line 207.
  279. Found 34x5-bit multiplier for signal <$mult0003> created at line 207.
  280. Found 5-bit register for signal <i>.
  281. Found 5-bit subtractor for signal <i$addsub0000> created at line 155.
  282. Found 32-bit register for signal <i_quo>.
  283. Found 32-bit register for signal <i_re>.
  284. Found 32-bit register for signal <k_reg.quo>.
  285. Found 36-bit register for signal <k_reg.re_reg>.
  286. Found 1-bit register for signal <k_reg.re_sign>.
  287. Found 32-bit register for signal <main_reg.quo>.
  288. Found 32-bit addsub for signal <main_reg.quo$mux0000>.
  289. Found 32-bit register for signal <main_reg.quo_reg>.
  290. Found 1-bit register for signal <main_reg.quo_sign>.
  291. Found 36-bit register for signal <main_reg.re_reg>.
  292. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 138.
  293. Found 36-bit adder for signal <main_reg.re_reg$share0000>.
  294. Found 1-bit register for signal <main_reg.re_sign>.
  295. Found 32-bit addsub for signal <quo$share0000>.
  296. Found 33-bit subtractor for signal <quo_reg_sub$sub0000> created at line 124.
  297. Found 32-bit adder for signal <quo_reg_sub_31_0$add0000> created at line 132.
  298. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 122.
  299. Found 29-bit comparator greatequal for signal <re$cmp_ge0000> created at line 207.
  300. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 207.
  301. Found 31-bit comparator greatequal for signal <re$cmp_ge0002> created at line 207.
  302. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 207.
  303. Found 30-bit comparator greatequal for signal <re$cmp_ge0004> created at line 207.
  304. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 207.
  305. Found 31-bit comparator greatequal for signal <re$cmp_ge0006> created at line 207.
  306. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 207.
  307. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 207.
  308. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 207.
  309. Found 31-bit comparator greatequal for signal <re$cmp_ge0010> created at line 207.
  310. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 207.
  311. Found 30-bit comparator greatequal for signal <re$cmp_ge0012> created at line 207.
  312. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 207.
  313. Found 31-bit comparator greatequal for signal <re$cmp_ge0014> created at line 207.
  314. Found 32-bit comparator greatequal for signal <re$cmp_ge0015> created at line 207.
  315. Found 33x4-bit multiplier for signal <re$mult0005> created at line 207.
  316. Found 33x3-bit multiplier for signal <re$mult0006> created at line 207.
  317. Found 33x4-bit multiplier for signal <re$mult0007> created at line 207.
  318. Found 33x3-bit multiplier for signal <re$mult0008> created at line 207.
  319. Found 33x3-bit multiplier for signal <re$mult0010> created at line 207.
  320. Found 33x4-bit multiplier for signal <re$mult0011> created at line 207.
  321. Found 33x4-bit multiplier for signal <re$mult0012> created at line 207.
  322. Found 32-bit addsub for signal <re$share0000>.
  323. Found 32-bit adder for signal <re$sub0000> created at line 207.
  324. Found 31-bit adder for signal <re$sub0001> created at line 207.
  325. Found 32-bit adder for signal <re$sub0002> created at line 207.
  326. Found 30-bit adder for signal <re$sub0003> created at line 207.
  327. Found 32-bit adder for signal <re$sub0004> created at line 207.
  328. Found 31-bit adder for signal <re$sub0005> created at line 207.
  329. Found 32-bit adder for signal <re$sub0006> created at line 207.
  330. Found 37-bit subtractor for signal <re_reg_sub$sub0000> created at line 125.
  331. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 123.
  332. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 123.
  333. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 123.
  334. Found 32-bit register for signal <tmp_quo_reg>.
  335. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_0$mux0000> created at line 110.
  336. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_1$mux0000> created at line 110.
  337. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_2$mux0000> created at line 110.
  338. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_3$mux0000> created at line 110.
  339. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_4$mux0000> created at line 110.
  340. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_5$mux0000> created at line 110.
  341. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_6$mux0000> created at line 110.
  342. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_7$mux0000> created at line 110.
  343. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_8$mux0000> created at line 110.
  344. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_shifted_0$mux0000> created at line 112.
  345. Found 36-bit adder for signal <v_re$addsub0000> created at line 196.
  346. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 200.
  347. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 120.
  348. Summary:
  349. inferred 1 Finite State Machine(s).
  350. inferred 272 D-type flip-flop(s).
  351. inferred 16 Adder/Subtractor(s).
  352. inferred 13 Multiplier(s).
  353. inferred 16 Comparator(s).
  354. inferred 42 Multiplexer(s).
  355. inferred 1 Combinational logic shifter(s).
  356. Unit <vedic_div32> synthesized.
  357.  
  358. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
  359.  
  360. =========================================================================
  361. HDL Synthesis Report
  362.  
  363. Macro Statistics
  364. # Multipliers : 13
  365. 33x3-bit multiplier : 3
  366. 33x32-bit multiplier : 2
  367. 33x4-bit multiplier : 4
  368. 34x4-bit multiplier : 2
  369. 34x5-bit multiplier : 2
  370. # Adders/Subtractors : 16
  371. 30-bit adder : 1
  372. 31-bit adder : 2
  373. 32-bit adder : 5
  374. 32-bit addsub : 3
  375. 33-bit subtractor : 1
  376. 36-bit adder : 2
  377. 37-bit subtractor : 1
  378. 5-bit subtractor : 1
  379. # Registers : 43
  380. 1-bit register : 35
  381. 32-bit register : 5
  382. 36-bit register : 2
  383. 5-bit register : 1
  384. # Latches : 65
  385. 1-bit latch : 63
  386. 31-bit latch : 1
  387. 5-bit latch : 1
  388. # Comparators : 16
  389. 29-bit comparator greatequal : 1
  390. 30-bit comparator greatequal : 2
  391. 31-bit comparator greatequal : 4
  392. 32-bit comparator greatequal : 9
  393. # Multiplexers : 42
  394. 1-bit 31-to-1 multiplexer : 1
  395. 1-bit 32-to-1 multiplexer : 41
  396. # Logic shifters : 1
  397. 36-bit shifter arithmetic right : 1
  398. # Xors : 1
  399. 1-bit xor2 : 1
  400.  
  401. =========================================================================
  402.  
  403. =========================================================================
  404. * Advanced HDL Synthesis *
  405. =========================================================================
  406.  
  407. Analyzing FSM <FSM_0> for best encoding.
  408. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  409. ------------------------
  410. State | Encoding
  411. ------------------------
  412. init_state | 0001
  413. main_state | 0100
  414. wait_state | 1000
  415. fin_state | 0010
  416. ------------------------
  417.  
  418. Synthesizing (advanced) Unit <vedic_div32>.
  419. The following registers are absorbed into accumulator <main_reg.quo>: 1 register on signal <main_reg.quo>.
  420. Unit <vedic_div32> synthesized (advanced).
  421.  
  422. =========================================================================
  423. Advanced HDL Synthesis Report
  424.  
  425. Macro Statistics
  426. # FSMs : 1
  427. # Multipliers : 13
  428. 33x3-bit multiplier : 3
  429. 33x32-bit multiplier : 2
  430. 33x4-bit multiplier : 4
  431. 34x4-bit multiplier : 2
  432. 34x5-bit multiplier : 2
  433. # Adders/Subtractors : 15
  434. 30-bit adder : 1
  435. 31-bit adder : 2
  436. 32-bit adder : 5
  437. 32-bit addsub : 2
  438. 33-bit subtractor : 1
  439. 36-bit adder : 2
  440. 37-bit subtractor : 1
  441. 5-bit subtractor : 1
  442. # Accumulators : 1
  443. 32-bit updown loadable accumulator : 1
  444. # Registers : 239
  445. Flip-Flops : 239
  446. # Latches : 65
  447. 1-bit latch : 63
  448. 31-bit latch : 1
  449. 5-bit latch : 1
  450. # Comparators : 16
  451. 29-bit comparator greatequal : 1
  452. 30-bit comparator greatequal : 2
  453. 31-bit comparator greatequal : 4
  454. 32-bit comparator greatequal : 9
  455. # Multiplexers : 42
  456. 1-bit 31-to-1 multiplexer : 1
  457. 1-bit 32-to-1 multiplexer : 41
  458. # Logic shifters : 1
  459. 36-bit shifter arithmetic right : 1
  460. # Xors : 1
  461. 1-bit xor2 : 1
  462.  
  463. =========================================================================
  464.  
  465. =========================================================================
  466. * Low Level Synthesis *
  467. =========================================================================
  468. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  469. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  470.  
  471. Optimizing unit <vedic_div32> ...
  472.  
  473. Mapping all equations...
  474. Building and optimizing final netlist ...
  475. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 19.
  476.  
  477. Final Macro Processing ...
  478.  
  479. =========================================================================
  480. Final Register Report
  481.  
  482. Macro Statistics
  483. # Registers : 274
  484. Flip-Flops : 274
  485.  
  486. =========================================================================
  487.  
  488. =========================================================================
  489. * Partition Report *
  490. =========================================================================
  491.  
  492. Partition Implementation Status
  493. -------------------------------
  494.  
  495. No Partitions were found in this design.
  496.  
  497. -------------------------------
  498.  
  499. =========================================================================
  500. * Final Report *
  501. =========================================================================
  502. Final Results
  503. RTL Top Level Output File Name : vedic_div32.ngr
  504. Top Level Output File Name : vedic_div32
  505. Output Format : NGC
  506. Optimization Goal : Speed
  507. Keep Hierarchy : No
  508.  
  509. Design Statistics
  510. # IOs : 130
  511.  
  512. Cell Usage :
  513. # BELS : 5947
  514. # GND : 1
  515. # INV : 246
  516. # LUT1 : 8
  517. # LUT2 : 594
  518. # LUT3 : 308
  519. # LUT4 : 717
  520. # LUT5 : 390
  521. # LUT6 : 1524
  522. # MUXCY : 1124
  523. # MUXF7 : 118
  524. # VCC : 1
  525. # XORCY : 916
  526. # FlipFlops/Latches : 373
  527. # FD : 184
  528. # FDE : 73
  529. # FDR : 2
  530. # FDS : 15
  531. # LDC : 1
  532. # LDCP : 98
  533. # Clock Buffers : 2
  534. # BUFG : 1
  535. # BUFGP : 1
  536. # IO Buffers : 129
  537. # IBUF : 65
  538. # OBUF : 64
  539. # DSPs : 6
  540. # DSP48E : 6
  541. =========================================================================
  542.  
  543. Device utilization summary:
  544. ---------------------------
  545.  
  546. Selected Device : 5vlx50tff1136-1
  547.  
  548.  
  549. Slice Logic Utilization:
  550. Number of Slice Registers: 373 out of 28800 1%
  551. Number of Slice LUTs: 3787 out of 28800 13%
  552. Number used as Logic: 3787 out of 28800 13%
  553.  
  554. Slice Logic Distribution:
  555. Number of LUT Flip Flop pairs used: 3864
  556. Number with an unused Flip Flop: 3491 out of 3864 90%
  557. Number with an unused LUT: 77 out of 3864 1%
  558. Number of fully used LUT-FF pairs: 296 out of 3864 7%
  559. Number of unique control sets: 108
  560.  
  561. IO Utilization:
  562. Number of IOs: 130
  563. Number of bonded IOBs: 130 out of 480 27%
  564.  
  565. Specific Feature Utilization:
  566. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  567. Number of DSP48Es: 6 out of 48 12%
  568.  
  569. ---------------------------
  570. Partition Resource Summary:
  571. ---------------------------
  572.  
  573. No Partitions were found in this design.
  574.  
  575. ---------------------------
  576.  
  577.  
  578. =========================================================================
  579. TIMING REPORT
  580.  
  581. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  582. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  583. GENERATED AFTER PLACE-and-ROUTE.
  584.  
  585. Clock Information:
  586. ------------------
  587. -----------------------------------+------------------------+-------+
  588. Clock Signal | Clock buffer(FF name) | Load |
  589. -----------------------------------+------------------------+-------+
  590. mclk1 | BUFGP | 274 |
  591. divisor<0> | IBUF+BUFG | 99 |
  592. -----------------------------------+------------------------+-------+
  593.  
  594. Asynchronous Control Signals Information:
  595. ----------------------------------------
  596. -------------------------------------------------------------+--------------------------+-------+
  597. Control Signal | Buffer(FF name) | Load |
  598. -------------------------------------------------------------+--------------------------+-------+
  599. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  600. b_n_0__and0001(b_n_mux0031<0>1:O) | NONE(b_n_0) | 1 |
  601. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  602. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  603. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  604. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  605. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  606. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  607. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  608. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  609. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  610. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  611. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  612. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  613. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  614. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  615. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  616. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  617. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  618. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  619. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  620. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  621. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  622. b_n_1__and0001(b_n_1__and00011:O) | NONE(b_n_1) | 1 |
  623. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  624. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  625. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  626. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  627. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  628. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  629. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  630. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  631. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  632. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  633. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  634. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  635. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  636. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  637. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  638. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  639. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  640. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  641. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  642. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  643. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  644. b_n_2__and0001(b_n_2__and00011:O) | NONE(b_n_2) | 1 |
  645. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  646. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  647. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  648. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  649. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  650. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  651. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  652. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  653. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  654. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  655. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  656. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  657. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  658. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  659. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  660. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  661. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  662. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  663. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O)| NONE(init_reg.quo_reg_10)| 1 |
  664. init_reg.quo_reg_10__or0000(init_reg.quo_reg_10__or0000:O) | NONE(init_reg.quo_reg_10)| 1 |
  665. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O)| NONE(init_reg.quo_reg_11)| 1 |
  666. init_reg.quo_reg_11__or0000(init_reg.quo_reg_11__or0000:O) | NONE(init_reg.quo_reg_11)| 1 |
  667. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O)| NONE(init_reg.quo_reg_12)| 1 |
  668. init_reg.quo_reg_12__or0000(init_reg.quo_reg_12__or00001:O) | NONE(init_reg.quo_reg_12)| 1 |
  669. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O)| NONE(init_reg.quo_reg_13)| 1 |
  670. init_reg.quo_reg_13__or0000(init_reg.quo_reg_13__or00001:O) | NONE(init_reg.quo_reg_13)| 1 |
  671. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O)| NONE(init_reg.quo_reg_14)| 1 |
  672. init_reg.quo_reg_14__or0000(init_reg.quo_reg_14__or00001:O) | NONE(init_reg.quo_reg_14)| 1 |
  673. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O)| NONE(init_reg.quo_reg_15)| 1 |
  674. init_reg.quo_reg_15__or0000(init_reg.quo_reg_15__or00001:O) | NONE(init_reg.quo_reg_15)| 1 |
  675. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O)| NONE(init_reg.quo_reg_16)| 1 |
  676. init_reg.quo_reg_16__or0000(init_reg.quo_reg_16__or00001:O) | NONE(init_reg.quo_reg_16)| 1 |
  677. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O)| NONE(init_reg.quo_reg_17)| 1 |
  678. init_reg.quo_reg_17__or0000(init_reg.quo_reg_17__or00001:O) | NONE(init_reg.quo_reg_17)| 1 |
  679. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O)| NONE(init_reg.quo_reg_18)| 1 |
  680. init_reg.quo_reg_18__or0000(init_reg.quo_reg_18__or00001:O) | NONE(init_reg.quo_reg_18)| 1 |
  681. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O)| NONE(init_reg.quo_reg_19)| 1 |
  682. init_reg.quo_reg_19__or0000(init_reg.quo_reg_19__or00001:O) | NONE(init_reg.quo_reg_19)| 1 |
  683. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  684. init_reg.quo_reg_1__or0000(init_reg.quo_reg_1__or00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  685. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O)| NONE(init_reg.quo_reg_20)| 1 |
  686. init_reg.quo_reg_20__or0000(init_reg.quo_reg_20__or00001:O) | NONE(init_reg.quo_reg_20)| 1 |
  687. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O)| NONE(init_reg.quo_reg_21)| 1 |
  688. init_reg.quo_reg_21__or0000(init_reg.quo_reg_21__or00001:O) | NONE(init_reg.quo_reg_21)| 1 |
  689. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O)| NONE(init_reg.quo_reg_22)| 1 |
  690. init_reg.quo_reg_22__or0000(init_reg.quo_reg_22__or00001:O) | NONE(init_reg.quo_reg_22)| 1 |
  691. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O)| NONE(init_reg.quo_reg_23)| 1 |
  692. init_reg.quo_reg_23__or0000(init_reg.quo_reg_23__or00001:O) | NONE(init_reg.quo_reg_23)| 1 |
  693. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O)| NONE(init_reg.quo_reg_24)| 1 |
  694. init_reg.quo_reg_24__or0000(init_reg.quo_reg_24__or00001:O) | NONE(init_reg.quo_reg_24)| 1 |
  695. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O)| NONE(init_reg.quo_reg_25)| 1 |
  696. init_reg.quo_reg_25__or0000(init_reg.quo_reg_25__or00001:O) | NONE(init_reg.quo_reg_25)| 1 |
  697. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O)| NONE(init_reg.quo_reg_26)| 1 |
  698. init_reg.quo_reg_26__or0000(init_reg.quo_reg_26__or00001:O) | NONE(init_reg.quo_reg_26)| 1 |
  699. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O)| NONE(init_reg.quo_reg_27)| 1 |
  700. init_reg.quo_reg_27__or0000(init_reg.quo_reg_27__or00001:O) | NONE(init_reg.quo_reg_27)| 1 |
  701. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O)| NONE(init_reg.quo_reg_28)| 1 |
  702. init_reg.quo_reg_28__or0000(init_reg.quo_reg_28__or00001:O) | NONE(init_reg.quo_reg_28)| 1 |
  703. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O)| NONE(init_reg.quo_reg_29)| 1 |
  704. init_reg.quo_reg_29__or0000(init_reg.quo_reg_29__or00001:O) | NONE(init_reg.quo_reg_29)| 1 |
  705. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  706. init_reg.quo_reg_2__or0000(init_reg.quo_reg_2__or00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  707. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O)| NONE(init_reg.quo_reg_30)| 1 |
  708. init_reg.quo_reg_30__or0000(init_reg.quo_reg_30__or00001:O) | NONE(init_reg.quo_reg_30)| 1 |
  709. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  710. init_reg.quo_reg_3__or0000(init_reg.quo_reg_3__or00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  711. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  712. init_reg.quo_reg_4__or0000(init_reg.quo_reg_4__or00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  713. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  714. init_reg.quo_reg_5__or0000(init_reg.quo_reg_5__or0000:O) | NONE(init_reg.quo_reg_5) | 1 |
  715. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  716. init_reg.quo_reg_6__or0000(init_reg.quo_reg_6__or0000:O) | NONE(init_reg.quo_reg_6) | 1 |
  717. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  718. init_reg.quo_reg_7__or0000(init_reg.quo_reg_7__or00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  719. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  720. init_reg.quo_reg_8__or0000(init_reg.quo_reg_8__or00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  721. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  722. init_reg.quo_reg_9__or0000(init_reg.quo_reg_9__or0000:O) | NONE(init_reg.quo_reg_9) | 1 |
  723. init_reg.re_reg_0__and0000(init_reg.re_reg_0__and00001:O) | NONE(init_reg.re_reg_0) | 1 |
  724. init_reg.re_reg_0__or0000(init_reg.re_reg_0__or00001:O) | NONE(init_reg.re_reg_0) | 1 |
  725. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  726. init_reg.re_reg_10__or0000(init_reg.re_reg_10__or0000:O) | NONE(init_reg.re_reg_10) | 1 |
  727. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  728. init_reg.re_reg_11__or0000(init_reg.re_reg_11__or0000:O) | NONE(init_reg.re_reg_11) | 1 |
  729. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  730. init_reg.re_reg_12__or0000(init_reg.re_reg_12__or0000:O) | NONE(init_reg.re_reg_12) | 1 |
  731. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  732. init_reg.re_reg_13__or0000(init_reg.re_reg_13__or0000:O) | NONE(init_reg.re_reg_13) | 1 |
  733. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  734. init_reg.re_reg_14__or0000(init_reg.re_reg_14__or0000:O) | NONE(init_reg.re_reg_14) | 1 |
  735. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  736. init_reg.re_reg_15__or0000(init_reg.re_reg_15__or00001:O) | NONE(init_reg.re_reg_15) | 1 |
  737. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  738. init_reg.re_reg_16__or0000(init_reg.re_reg_16__or00001:O) | NONE(init_reg.re_reg_16) | 1 |
  739. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  740. init_reg.re_reg_17__or0000(init_reg.re_reg_17__or0000:O) | NONE(init_reg.re_reg_17) | 1 |
  741. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  742. init_reg.re_reg_18__or0000(init_reg.re_reg_18__or0000:O) | NONE(init_reg.re_reg_18) | 1 |
  743. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  744. init_reg.re_reg_19__or0000(init_reg.re_reg_19__or0000:O) | NONE(init_reg.re_reg_19) | 1 |
  745. init_reg.re_reg_1__and0000(init_reg_re_reg_1_mux00311:O) | NONE(init_reg.re_reg_1) | 1 |
  746. init_reg.re_reg_1__or0000(init_reg.re_reg_1__or00001:O) | NONE(init_reg.re_reg_1) | 1 |
  747. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  748. init_reg.re_reg_20__or0000(init_reg.re_reg_20__or0000:O) | NONE(init_reg.re_reg_20) | 1 |
  749. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  750. init_reg.re_reg_21__or0000(init_reg.re_reg_21__or00001:O) | NONE(init_reg.re_reg_21) | 1 |
  751. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  752. init_reg.re_reg_22__or0000(init_reg.re_reg_22__or00001:O) | NONE(init_reg.re_reg_22) | 1 |
  753. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  754. init_reg.re_reg_23__or0000(init_reg.re_reg_23__or00001:O) | NONE(init_reg.re_reg_23) | 1 |
  755. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  756. init_reg.re_reg_24__or0000(init_reg.re_reg_24__or0000:O) | NONE(init_reg.re_reg_24) | 1 |
  757. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  758. init_reg.re_reg_25__or0000(init_reg.re_reg_25__or0000:O) | NONE(init_reg.re_reg_25) | 1 |
  759. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  760. init_reg.re_reg_26__or0000(init_reg.re_reg_26__or0000:O) | NONE(init_reg.re_reg_26) | 1 |
  761. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  762. init_reg.re_reg_27__or0000(init_reg.re_reg_27__or00002:O) | NONE(init_reg.re_reg_27) | 1 |
  763. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  764. init_reg.re_reg_28__or0000(init_reg.re_reg_28__or0000:O) | NONE(init_reg.re_reg_28) | 1 |
  765. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  766. init_reg.re_reg_29__or0000(init_reg.re_reg_29__or0000:O) | NONE(init_reg.re_reg_29) | 1 |
  767. init_reg.re_reg_2__and0000(init_reg_re_reg_2_mux00311:O) | NONE(init_reg.re_reg_2) | 1 |
  768. init_reg.re_reg_2__or0000(init_reg.re_reg_2__or00001:O) | NONE(init_reg.re_reg_2) | 1 |
  769. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  770. init_reg.re_reg_30__and0001(init_reg.re_reg_30__and00011:O) | NONE(init_reg.re_reg_30) | 1 |
  771. init_reg.re_reg_3__and0000(init_reg.re_reg_3__and00001:O) | NONE(init_reg.re_reg_3) | 1 |
  772. init_reg.re_reg_3__or0000(init_reg.re_reg_3__or00001:O) | NONE(init_reg.re_reg_3) | 1 |
  773. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  774. init_reg.re_reg_4__or0000(init_reg.re_reg_4__or0000:O) | NONE(init_reg.re_reg_4) | 1 |
  775. init_reg.re_reg_5__and0000(init_reg.re_reg_5__and00001:O) | NONE(init_reg.re_reg_5) | 1 |
  776. init_reg.re_reg_5__or0000(init_reg.re_reg_5__or0000:O) | NONE(init_reg.re_reg_5) | 1 |
  777. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  778. init_reg.re_reg_6__or0000(init_reg.re_reg_6__or0000:O) | NONE(init_reg.re_reg_6) | 1 |
  779. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and00001:O) | NONE(init_reg.re_reg_7) | 1 |
  780. init_reg.re_reg_7__or0000(init_reg.re_reg_7__or00001:O) | NONE(init_reg.re_reg_7) | 1 |
  781. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  782. init_reg.re_reg_8__or0000(init_reg.re_reg_8__or0000:O) | NONE(init_reg.re_reg_8) | 1 |
  783. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  784. init_reg.re_reg_9__or0000(init_reg.re_reg_9__or0000:O) | NONE(init_reg.re_reg_9) | 1 |
  785. init_reg_re_reg_30_or0000(init_reg_re_reg_30_or00001:O) | NONE(init_reg.quo_reg_31)| 1 |
  786. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  787. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  788. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  789. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  790. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  791. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  792. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  793. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  794. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  795. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  796. -------------------------------------------------------------+--------------------------+-------+
  797.  
  798. Timing Summary:
  799. ---------------
  800. Speed Grade: -1
  801.  
  802. Minimum period: 15.169ns (Maximum Frequency: 65.925MHz)
  803. Minimum input arrival time before clock: 11.214ns
  804. Maximum output required time after clock: 12.008ns
  805. Maximum combinational path delay: 16.763ns
  806.  
  807. Timing Detail:
  808. --------------
  809. All values displayed in nanoseconds (ns)
  810.  
  811. =========================================================================
  812. Timing constraint: Default period analysis for Clock 'mclk1'
  813. Clock period: 15.169ns (frequency: 65.925MHz)
  814. Total number of paths / destination ports: 6353685111 / 364
  815. -------------------------------------------------------------------------
  816. Delay: 15.169ns (Levels of Logic = 27)
  817. Source: state_FSM_FFd4 (FF)
  818. Destination: main_reg.quo_reg_31 (FF)
  819. Source Clock: mclk1 rising
  820. Destination Clock: mclk1 rising
  821.  
  822. Data Path: state_FSM_FFd4 to main_reg.quo_reg_31
  823. Gate Net
  824. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  825. ---------------------------------------- ------------
  826. FDR:C->Q 347 0.471 0.666 state_FSM_FFd4 (state_FSM_FFd4)
  827. LUT3:I2->O 11 0.094 0.844 reg_quo_reg<17>1 (reg_quo_reg<17>)
  828. LUT6:I2->O 1 0.094 0.480 tmp_quo_reg_15_mux000094 (tmp_quo_reg_15_mux000094)
  829. LUT6:I5->O 1 0.094 0.576 tmp_quo_reg_15_mux0000149 (tmp_quo_reg_15_mux0000149)
  830. LUT6:I4->O 1 0.094 0.000 tmp_quo_reg_15_mux0000189_F (N6911)
  831. MUXF7:I0->O 3 0.251 0.347 tmp_quo_reg_15_mux0000189 (tmp_quo_reg_15_mux0000)
  832. DSP48E:B15->PCOUT3 1 3.832 0.000 Mmult_quo_tmp_mult0001 (Mmult_quo_tmp_mult0001_PCOUT_to_Mmult_quo_tmp_mult00011_PCIN_3)
  833. DSP48E:PCIN3->PCOUT6 1 2.013 0.000 Mmult_quo_tmp_mult00011 (Mmult_quo_tmp_mult00011_PCOUT_to_Mmult_quo_tmp_mult00012_PCIN_6)
  834. DSP48E:PCIN6->P0 1 1.816 0.480 Mmult_quo_tmp_mult00012 (quo_tmp_mult0001<17>)
  835. LUT6:I5->O 1 0.094 0.000 Msub_quo_reg_sub_sub0000_lut<17> (Msub_quo_reg_sub_sub0000_lut<17>)
  836. MUXCY:S->O 1 0.372 0.000 Msub_quo_reg_sub_sub0000_cy<17> (Msub_quo_reg_sub_sub0000_cy<17>)
  837. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<18> (Msub_quo_reg_sub_sub0000_cy<18>)
  838. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<19> (Msub_quo_reg_sub_sub0000_cy<19>)
  839. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<20> (Msub_quo_reg_sub_sub0000_cy<20>)
  840. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<21> (Msub_quo_reg_sub_sub0000_cy<21>)
  841. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<22> (Msub_quo_reg_sub_sub0000_cy<22>)
  842. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<23> (Msub_quo_reg_sub_sub0000_cy<23>)
  843. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<24> (Msub_quo_reg_sub_sub0000_cy<24>)
  844. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<25> (Msub_quo_reg_sub_sub0000_cy<25>)
  845. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<26> (Msub_quo_reg_sub_sub0000_cy<26>)
  846. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<27> (Msub_quo_reg_sub_sub0000_cy<27>)
  847. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<28> (Msub_quo_reg_sub_sub0000_cy<28>)
  848. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<29> (Msub_quo_reg_sub_sub0000_cy<29>)
  849. XORCY:CI->O 2 0.357 0.341 Msub_quo_reg_sub_sub0000_xor<30> (quo_reg_sub_sub0000<30>)
  850. INV:I->O 1 0.238 0.000 Madd_quo_reg_sub_31_0_not0000<30>1_INV_0 (Madd_quo_reg_sub_31_0_not0000<30>)
  851. MUXCY:S->O 0 0.372 0.000 Madd_quo_reg_sub_31_0_add0000_cy<30> (Madd_quo_reg_sub_31_0_add0000_cy<30>)
  852. XORCY:CI->O 1 0.357 0.480 Madd_quo_reg_sub_31_0_add0000_xor<31> (quo_reg_sub_31_0_add0000<31>)
  853. LUT3:I2->O 1 0.094 0.000 quo_reg_sub_31_mux00001 (quo_reg_sub_31_mux0000)
  854. FD:D -0.018 main_reg.quo_reg_31
  855. ----------------------------------------
  856. Total 15.169ns (10.955ns logic, 4.214ns route)
  857. (72.2% logic, 27.8% route)
  858.  
  859. =========================================================================
  860. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  861. Total number of paths / destination ports: 7 / 7
  862. -------------------------------------------------------------------------
  863. Offset: 2.334ns (Levels of Logic = 2)
  864. Source: go (PAD)
  865. Destination: i_0 (FF)
  866. Destination Clock: mclk1 rising
  867.  
  868. Data Path: go to i_0
  869. Gate Net
  870. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  871. ---------------------------------------- ------------
  872. IBUF:I->O 3 0.818 0.491 go_IBUF (go_IBUF)
  873. LUT3:I2->O 5 0.094 0.358 i_or00011 (i_or0001)
  874. FDS:S 0.573 i_0
  875. ----------------------------------------
  876. Total 2.334ns (1.485ns logic, 0.849ns route)
  877. (63.6% logic, 36.4% route)
  878.  
  879. =========================================================================
  880. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  881. Total number of paths / destination ports: 10245 / 99
  882. -------------------------------------------------------------------------
  883. Offset: 11.214ns (Levels of Logic = 12)
  884. Source: divisor<26> (PAD)
  885. Destination: init_reg.re_reg_29 (LATCH)
  886. Destination Clock: divisor<0> falling
  887.  
  888. Data Path: divisor<26> to init_reg.re_reg_29
  889. Gate Net
  890. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  891. ---------------------------------------- ------------
  892. IBUF:I->O 147 0.818 1.218 divisor_26_IBUF (divisor_26_IBUF)
  893. LUT6:I0->O 11 0.094 1.124 init_reg_re_reg_10_or00061 (init_reg_quo_reg_6_or0000)
  894. LUT6:I0->O 6 0.094 1.096 init_reg_re_reg_11_or00021 (init_reg_re_reg_11_or0002)
  895. LUT6:I0->O 12 0.094 0.770 init_reg_re_reg_20_or00051 (init_reg_re_reg_20_or0005)
  896. LUT3:I0->O 11 0.094 1.124 init_reg_re_reg_21_or00021 (init_reg_re_reg_21_or0002)
  897. LUT6:I0->O 12 0.094 0.636 init_reg_re_reg_30_or00021 (init_reg_re_reg_30_or0002)
  898. LUT6:I4->O 1 0.094 0.973 init_reg_re_reg_29_mux0031219 (init_reg_re_reg_29_mux0031219)
  899. LUT6:I1->O 1 0.094 0.576 init_reg_re_reg_29_mux0031276_SW0 (N277)
  900. LUT6:I4->O 1 0.094 0.480 init_reg_re_reg_29_mux0031276 (init_reg_re_reg_29_mux0031276)
  901. LUT6:I5->O 1 0.094 0.576 init_reg_re_reg_29_mux0031339_SW0 (N531)
  902. LUT6:I4->O 1 0.094 0.789 init_reg_re_reg_29_mux0031339 (init_reg_re_reg_29_mux0031339)
  903. LUT6:I2->O 3 0.094 0.000 init_reg_re_reg_29_mux0031401 (init_reg_re_reg_29_mux0031)
  904. LDCP:D -0.071 init_reg.re_reg_29
  905. ----------------------------------------
  906. Total 11.214ns (1.852ns logic, 9.362ns route)
  907. (16.5% logic, 83.5% route)
  908.  
  909. =========================================================================
  910. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  911. Total number of paths / destination ports: 2645574 / 64
  912. -------------------------------------------------------------------------
  913. Offset: 12.008ns (Levels of Logic = 55)
  914. Source: i_re_1 (FF)
  915. Destination: re<30> (PAD)
  916. Source Clock: mclk1 rising
  917.  
  918. Data Path: i_re_1 to re<30>
  919. Gate Net
  920. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  921. ---------------------------------------- ------------
  922. FD:C->Q 26 0.471 0.915 i_re_1 (i_re_1)
  923. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi (Mcompar_re_cmp_ge0015_lutdi)
  924. MUXCY:DI->O 1 0.362 0.000 Mcompar_re_cmp_ge0015_cy<0> (Mcompar_re_cmp_ge0015_cy<0>)
  925. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<1> (Mcompar_re_cmp_ge0015_cy<1>)
  926. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<2> (Mcompar_re_cmp_ge0015_cy<2>)
  927. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<3> (Mcompar_re_cmp_ge0015_cy<3>)
  928. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<4> (Mcompar_re_cmp_ge0015_cy<4>)
  929. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<5> (Mcompar_re_cmp_ge0015_cy<5>)
  930. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<6> (Mcompar_re_cmp_ge0015_cy<6>)
  931. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<7> (Mcompar_re_cmp_ge0015_cy<7>)
  932. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<8> (Mcompar_re_cmp_ge0015_cy<8>)
  933. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<9> (Mcompar_re_cmp_ge0015_cy<9>)
  934. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<10> (Mcompar_re_cmp_ge0015_cy<10>)
  935. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<11> (Mcompar_re_cmp_ge0015_cy<11>)
  936. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<12> (Mcompar_re_cmp_ge0015_cy<12>)
  937. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<13> (Mcompar_re_cmp_ge0015_cy<13>)
  938. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0015_cy<14> (Mcompar_re_cmp_ge0015_cy<14>)
  939. MUXCY:CI->O 31 0.254 0.837 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015)
  940. LUT3:I0->O 5 0.094 0.811 re_mux0000<11>2111 (N751)
  941. LUT6:I2->O 1 0.094 0.480 re_mux0000<1>102_SW0 (N237)
  942. LUT6:I5->O 1 0.094 0.576 re_mux0000<1>102 (re_mux0000<1>102)
  943. LUT6:I4->O 1 0.094 0.576 re_mux0000<1>171_SW0 (N293)
  944. LUT5:I3->O 1 0.094 0.576 re_mux0000<1>171 (re_mux0000<1>)
  945. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  946. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  947. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  948. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  949. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  950. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  951. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  952. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  953. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  954. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  955. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  956. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  957. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  958. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  959. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  960. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  961. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  962. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  963. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  964. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  965. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  966. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  967. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  968. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  969. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  970. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  971. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  972. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  973. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  974. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  975. XORCY:CI->O 1 0.357 0.789 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  976. LUT5:I1->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  977. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  978. ----------------------------------------
  979. Total 12.008ns (6.112ns logic, 5.896ns route)
  980. (50.9% logic, 49.1% route)
  981.  
  982. =========================================================================
  983. Timing constraint: Default path analysis
  984. Total number of paths / destination ports: 894319019 / 64
  985. -------------------------------------------------------------------------
  986. Delay: 16.763ns (Levels of Logic = 76)
  987. Source: divisor<2> (PAD)
  988. Destination: re<30> (PAD)
  989.  
  990. Data Path: divisor<2> to re<30>
  991. Gate Net
  992. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  993. ---------------------------------------- ------------
  994. IBUF:I->O 110 0.818 0.718 divisor_2_IBUF (divisor_2_IBUF)
  995. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd_lut<2> (Mmult_re_mult0012_Madd_lut<2>)
  996. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd_cy<2> (Mmult_re_mult0012_Madd_cy<2>)
  997. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<3> (Mmult_re_mult0012_Madd_cy<3>)
  998. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<4> (Mmult_re_mult0012_Madd_cy<4>)
  999. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<5> (Mmult_re_mult0012_Madd_cy<5>)
  1000. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<6> (Mmult_re_mult0012_Madd_cy<6>)
  1001. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<7> (Mmult_re_mult0012_Madd_cy<7>)
  1002. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<8> (Mmult_re_mult0012_Madd_cy<8>)
  1003. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<9> (Mmult_re_mult0012_Madd_cy<9>)
  1004. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<10> (Mmult_re_mult0012_Madd_cy<10>)
  1005. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<11> (Mmult_re_mult0012_Madd_cy<11>)
  1006. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<12> (Mmult_re_mult0012_Madd_cy<12>)
  1007. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<13> (Mmult_re_mult0012_Madd_cy<13>)
  1008. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<14> (Mmult_re_mult0012_Madd_cy<14>)
  1009. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<15> (Mmult_re_mult0012_Madd_cy<15>)
  1010. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<16> (Mmult_re_mult0012_Madd_cy<16>)
  1011. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<17> (Mmult_re_mult0012_Madd_cy<17>)
  1012. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<18> (Mmult_re_mult0012_Madd_cy<18>)
  1013. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<19> (Mmult_re_mult0012_Madd_cy<19>)
  1014. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<20> (Mmult_re_mult0012_Madd_cy<20>)
  1015. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<21> (Mmult_re_mult0012_Madd_cy<21>)
  1016. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<22> (Mmult_re_mult0012_Madd_cy<22>)
  1017. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<23> (Mmult_re_mult0012_Madd_cy<23>)
  1018. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<24> (Mmult_re_mult0012_Madd_cy<24>)
  1019. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<25> (Mmult_re_mult0012_Madd_cy<25>)
  1020. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<26> (Mmult_re_mult0012_Madd_cy<26>)
  1021. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<27> (Mmult_re_mult0012_Madd_cy<27>)
  1022. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<28> (Mmult_re_mult0012_Madd_cy<28>)
  1023. XORCY:CI->O 1 0.357 0.576 Mmult_re_mult0012_Madd_xor<29> (Mmult_re_mult0012_Madd_29)
  1024. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd1_lut<29> (Mmult_re_mult0012_Madd1_lut<29>)
  1025. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd1_cy<29> (Mmult_re_mult0012_Madd1_cy<29>)
  1026. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0012_Madd1_xor<30> (re_mult0012<30>)
  1027. INV:I->O 1 0.238 0.000 Madd_re_not0006<30>1_INV_0 (Madd_re_not0006<30>)
  1028. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0006_cy<30> (Madd_re_sub0006_cy<30>)
  1029. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0006_xor<31> (re_sub0006<31>)
  1030. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi15 (Mcompar_re_cmp_ge0015_lutdi15)
  1031. MUXCY:DI->O 31 0.590 0.837 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015)
  1032. LUT3:I0->O 5 0.094 0.811 re_mux0000<11>2111 (N751)
  1033. LUT6:I2->O 1 0.094 0.480 re_mux0000<1>102_SW0 (N237)
  1034. LUT6:I5->O 1 0.094 0.576 re_mux0000<1>102 (re_mux0000<1>102)
  1035. LUT6:I4->O 1 0.094 0.576 re_mux0000<1>171_SW0 (N293)
  1036. LUT5:I3->O 1 0.094 0.576 re_mux0000<1>171 (re_mux0000<1>)
  1037. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  1038. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  1039. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  1040. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  1041. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  1042. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  1043. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  1044. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  1045. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  1046. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  1047. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  1048. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  1049. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  1050. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  1051. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  1052. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  1053. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  1054. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  1055. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  1056. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  1057. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  1058. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  1059. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  1060. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  1061. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  1062. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  1063. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  1064. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  1065. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  1066. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  1067. XORCY:CI->O 1 0.357 0.789 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  1068. LUT5:I1->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  1069. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  1070. ----------------------------------------
  1071. Total 16.763ns (9.358ns logic, 7.405ns route)
  1072. (55.8% logic, 44.2% route)
  1073.  
  1074. =========================================================================
  1075.  
  1076.  
  1077. Total REAL time to Xst completion: 1506.00 secs
  1078. Total CPU time to Xst completion: 1504.63 secs
  1079.  
  1080. -->
  1081.  
  1082.  
  1083. Total memory usage is 819200 kilobytes
  1084.  
  1085. Number of errors : 0 ( 0 filtered)
  1086. Number of warnings : 90 ( 0 filtered)
  1087. Number of infos : 37 ( 0 filtered)
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