`timescale 1ns / 1ps

module verilog_main(
    input CLK_50MHz,
//    input [n-1:0] SetFreq,
//    input [k-1:0] SetPWM,
//    input enc_1_A,
//    input enc_1_B,
//    input enc_2_A,
//    input enc_2_B,
//    output Dir,
    output PWM
//    output Break
    );
	 localparam n=10;
	 localparam k=10;


	reg [n-1:0] setFreq=4'd10;
	reg [k-1:0] setPWM=4'd5;
	reg clock=1'b0;
	reg [3:0] counter=1'b0;

 always@(posedge CLK_50MHz)
 begin
	counter<=counter+1;
	if(counter>4'd10)
	begin
		counter<=1'b0;
		clock<=~clock;
	end
	else
	begin
		clock<=clock;
	end
 end

 always@(posedge clock)
 begin
		if(setFreq>setPWM)
		begin
			setFreq<=setFreq+4'd10;
			setPWM<=setPWM+4'd5;
		end
		else
		begin
			setFreq<=4'd10;
			setPWM<=4'd5;
		end

 end


 pwm_gen
 #
 (
	.n(n),
	.k(k)
 ) pewuemus
 (
	.clk(CLK_50MHz),
	.setFreq(setFreq),
	.setPWM(setPWM),
	.pwm(PWM)
 );

endmodule

`timescale 1ns / 1ps

module pwm_gen
#
(
	parameter n=10,
	parameter k=10
)
    (
    input clk,
	 input [n-1:0] setFreq,
	 input [k-1:0] setPWM,
    output pwm
    );

    reg [n-1:0] counter=1'b0;
	 reg r_PWM=1'b0;

    always@(posedge(clk))
	 begin
			counter<=counter+1;
			if(counter<setPWM)
				r_PWM<=1'b1;
			else
				begin
				r_PWM<=1'b0;
				if(counter>=setFreq)
					counter<=1'b0;
				else
					counter<=counter;
				end
    end


assign pwm=r_PWM;
endmodule