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800MT/s working

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Sep 15th, 2021
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  1. =============== SoC ==================--
  2. CPU: VexRiscv SMP-LINUX @ 50MHz
  3. BUS: WISHBONE 32-bit @ 4GiB
  4. CSR: 32-bit data
  5. ROM: 64KiB
  6. SRAM: 8KiB
  7. L2: 0KiB
  8. SDRAM: 524288KiB 16-bit @ 800MT/s (CL-10 CWL-6)
  9.  
  10. --========== Initialization ============--
  11. Initializing SDRAM @0x40000000...
  12. Switching SDRAM to software control.
  13. Write leveling:
  14. tCK equivalent taps: 48
  15. Cmd/Clk scan (0-24)
  16. |000000000011111111111111| best: 9
  17. Setting Cmd/Clk delay to 9 taps.
  18. Data scan:
  19. m0: |00000000000000000000| delay: -
  20. m1: |11111111111111111111| delay: 00
  21. Write latency calibration:
  22. m0:14 m1:14
  23. Write DQ-DQS training:
  24. m0: |11111111111111111111000000000000| delays: 10+-10
  25. m1: |11111111111111111111000000000000| delays: 10+-10
  26. Read leveling:
  27. m0, b00: |00000000000000000000000000000000| delays: -
  28. m0, b01: |00000000000000000000000000000000| delays: -
  29. m0, b02: |00000000000000000000000000000000| delays: -
  30. m0, b03: |00000000000000000000000000000000| delays: -
  31. m0, b04: |00000000000000000000000000000000| delays: -
  32. m0, b05: |00000000000000000000000000000000| delays: -
  33. m0, b06: |00000000000000000000000000000000| delays: -
  34. m0, b07: |00000000000000000000000000000000| delays: -
  35. m0, b08: |00000000000000000000000000000000| delays: -
  36. m0, b09: |11111110000000000000000000000000| delays: 03+-03
  37. m0, b10: |00000000000000000011111111111100| delays: 24+-06
  38. m0, b11: |00000000000000000000000000000000| delays: -
  39. m0, b12: |00000000000000000000000000000000| delays: -
  40. m0, b13: |00000000000000000000000000000000| delays: -
  41. m0, b14: |00000000000000000000000000000000| delays: -
  42. m0, b15: |00000000000000000000000000000000| delays: -
  43. best: m0, b10 delays: 24+-06
  44. m1, b00: |00000000000000000000000000000000| delays: -
  45. m1, b01: |00000000000000000000000000000000| delays: -
  46. m1, b02: |00000000000000000000000000000000| delays: -
  47. m1, b03: |00000000000000000000000000000000| delays: -
  48. m1, b04: |00000000000000000000000000000000| delays: -
  49. m1, b05: |00000000000000000000000000000000| delays: -
  50. m1, b06: |00000000000000000000000000000000| delays: -
  51. m1, b07: |00000000000000000000000000000000| delays: -
  52. m1, b08: |00000000000000000000000000000000| delays: -
  53. m1, b09: |11111111100000000000000000000000| delays: 04+-04
  54. m1, b10: |00000000000000001111111111111111| delays: 24+-08
  55. m1, b11: |00000000000000000000000000000000| delays: -
  56. m1, b12: |00000000000000000000000000000000| delays: -
  57. m1, b13: |00000000000000000000000000000000| delays: -
  58. m1, b14: |00000000000000000000000000000000| delays: -
  59. m1, b15: |00000000000000000000000000000000| delays: -
  60. best: m1, b10 delays: 24+-08
  61. Switching SDRAM to hardware control.
  62. Memtest at 0x40000000 (2.0MiB)...
  63. Write: 0x40000000-0x40200000 2.0MiB
  64. Read: 0x40000000-0x40200000 2.0MiB
  65. Memtest OK
  66. Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  67. Write speed: 15.8MiB/s
  68. Read speed: 15.5MiB/s
  69.  
  70.  
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