new2

Defects fixed in XCELIUM19.09.001
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CCRID        Product                 Title
------       ---------    ------------------------------------------------------
1524869      CORE_AMSD       irun always compile elaborate even though nothing changes
1714279      CORE_AMSD       svams fails with multiple global supply error
1806840      CORE_AMSD       update  the xmvlog: *F,NOECBF error message to aid in MS binding debug
1833710      CORE_AMSD       Request for a tool command switch to locate the AMSD directory - bigger picture: need ability to control compiled IP
1861595      CORE_AMSD       duplicate port specification at Verilog/SV and SPICE boundary causes SFE-46 error - request better error message
1872810      CORE_AMSD       Cannot bind Verilog module to Spice when using bus ports
1917425      CORE_AMSD       SVRNM: Support SIE models with mixed-language net connections
1920228      CORE_AMSD       Support Electrical signals as control signals in CPF
1922547      CORE_AMSD       Xcelium AMS: xmsim: *E,SYFATAL : `$clog2' - Unsupported system task/function.
1932145      CORE_AMSD       SV nets with custom resolution function don't find SVAMS CMs when connected to electrical modules
1952400      CORE_AMSD       Need rnm_coerce on switch that is complementary to rnm_coerce off
1966486      CORE_AMSD       RNM Debug: Question about creating a breakpoint on a wreal signal/port using TCL stop command
1976222      CORE_AMSD       RNM Debug: Question about creating a strobe on a wreal signal using TCL strobe command
1992798      CORE_AMSD       $SIE_input is used on a port with EEnet, all the real pins in the block. On the top level but the values is not computed
1999555      CORE_AMSD       Provide a switch to downgrade PIEMRSG error to warning
2029773      CORE_AMSD       Scoped ie card with nettype causes E,CUVNCM (No connection module found) error
2031032      CORE_AMSD       Valid spice OOMR's are ignored with autospiceoomr option
2038143      CORE_AMSD       Unexpected UDFUOBJ and CSNIHT when using a rmn custom vct in 3-steps
2039056      CORE_AMSD       CUVMCP: Recursive multiple concatenation for digital block
2040324      CORE_AMSD       xmvlog -zparse dumps different file content for 32bit and 64bit
2042492      CORE_AMSD       INTERR: sv_seghandler - trapno -1 addr(0xc5) in cu_xvlog_cmp_signature
2048928      CORE_AMSD       LPS(UPF) - 18.09-s005 improper exit - control signals is resolved as electrical by DR optimization
2050293      CORE_AMSD       Allow hierarchical reference in create_power_nets and create_ground_nets commands in CPF
2050653      CORE_AMSD       more intelligent discipline resolution default logic assignment for designs that do not require disres
2050926      CORE_AMSD       Degradation in Xcelium vs Incisive -- related to RL_bidir.vams update in Xcelium
2051145      CORE_AMSD       MSIE+SVRNM: Internal error during elaboration with RNM coercion
2051355      CORE_AMSD       xrun in multi step compile need to find AMSCOMM automatically
2052942      CORE_AMSD       W, AMSNLOG is not expected for a design with no MS content
2055893      CORE_AMSD       Invoke SimVision standalone also checking out Xcelium_SC_DMS_Option along  with "Affirma_sim_analysis_env
2059987      CORE_AMSD       Call of schematic in Standalone invocation of simvision checkouts Xcelium_SC_DMS_option feature
2062579      CORE_AMSD       XMELAB improper tool exit with message update_power_domain - invalid power domain
2064157      CORE_AMSD       Spurious AMSNLG warning with  "xcelium.d.rtl", used with -xmlibdirname.
2067227      CORE_AMSD       MSDEBUG: Parameters which are expressions should be displayed in evaluated form
2067233      CORE_AMSD       VerilogAMS analogmodel instances currently not processed for schematic/symbol rendering
2067237      CORE_AMSD       Remove current probes from instance parameter string in schematic tracer
2067245      CORE_AMSD       MSDEBUG: Remove requirement of -snapshot option when invoking Simvision with MSDEBUG flow
2067260      CORE_AMSD       MSDEBUG: add r3 model type to analog primitive/symbol binding flow
2068580      CORE_AMSD       How to remove '2 Virtuoso_Multi_mode_Simulation' from license options
2068725      CORE_AMSD       outstanding error *E,WUDNSP  in xcelium
2069860      CORE_AMSD       AMSD : Inverter instance is not inverting the input
2070700      CORE_AMSD       Customer experiencing internal error in xmelab
2072986      CORE_AMSD       Invalid BNDERC with reused design
2074309      CORE_AMSD       Improve the CCSNAN error message on real variable
2076507      CORE_AMSD       xrun (xmelab) Internal Exception error in mixed-signal design
2078600      CORE_AMSD       BNDERC error when accessing SV UDN struct through virtual interface
2081094      CORE_AMSD       AMS fails when DPI-C is used with Spice On top
2081717      CORE_AMSD       DMS CPF testcase unresponsive at elaboration stage; stuck at amspwrParsePrimaryPGNets()
2094541      CORE_AMSD       add an option to disable PIEMRSG error during elaboration on selected nets
2096150      CORE_AMSD       Getting 'xmsim: *E,SYFATAL : $clog2' - Unsupported system task/function' in an AMS-SV run
2100481      CORE_AMSD       Remove sqrt DPI import from EE_pkg.sv file
2102256      CORE_AMSD       Using genvar in a generate block with OOMR gives wrong results
2107390      CORE_AMSD       XMELAB: ams_add_to_td_list - parent data already in child internal exception error
2110197      CORE_AMSD       Elaborator tries to insert isolation cell for nets already having level shifter and isolation as a part of functionality
2112683      CORE_AMSD       Elaboration trapno -1 : xmelab internal error during mixed signal IP Reuse(via VIPER) flow for top-level MS verification
2118373      CORE_AMSD       Need xrun option to print soft error and allow pure SV elaboration for real port connected to logic variable
2119598      CORE_AMSD       Internal exception xmelab message ams_mk_disciplinep - no discipline
2123550      CORE_AMSD       FATAL error for mixed language testcase using $SEI_input function
2124348      CORE_AMSD       Using ams_weak_setd argument with xrun the elaboration fails with internal error
2125767      CORE_AMSD       AMS - Boundary port domains are not honored for macro CPF level in AMS
2128439      CORE_AMSD       Analog signal being used as isolation control gives CCSNAN error
2130053      CORE_AMSD       Downgrade errors PIEMASG and PIEMRSG to warnings
2130482      CORE_AMSD       Elaboration internal error related to mixed signal on boundary with VHDL   3 party VIP
2132024      CORE_AMSD       Virtuoso Verilogams Import: Symbol default parameter values are not properly
2134796      CORE_AMSD       Internal exception error in AMS Low Power simulation with stack trace in ams_pwr_get_active_ordinary_id and  ams_pwr_get
2024207      CORE_ASSERTION  disabled_count being incremented by 1000
2047372      CORE_ASSERTION  elaboration performance - NY HDC xTb
2048572      CORE_ASSERTION  Behavior of assertion change between 18.12 to 19.10 xcelium version
2050689      CORE_ASSERTION  ABVCTR warning does not have enough debug info
2082175      CORE_ASSERTION  xrun elab Internal Exception error when using $assertoff in code
2083911      CORE_ASSERTION  Builtin system function <> not yet implemented
2115770      CORE_ASSERTION  Simulation deadlock in 19.03 whereas it finishes in 18.03 stream.
2120328      CORE_ASSERTION  Internal Exception Error during compile/elab of design
1546294      CORE_CODEGEN    Provide detailed information on COD generation for UVM/SV code
2015627      CORE_CODEGEN    Need to show srandom calls in dbg_seed tracing
2029801      CORE_CODEGEN    ncvlog_cg internal error 'gq_gen - SVHR type mismatch'
2032408      CORE_CODEGEN    Internal exception on 18.09-002, Incisive works OK
2045028      CORE_CODEGEN    NCSIM Internal exception with message "Continuous Assignment: (File: XX)"
2055953      CORE_CODEGEN    xmvlog_cg *F, SOPARM causes a elaboration failure
2059348      CORE_CODEGEN    xmvlog_cg internal error gq_mvlabel - no blocks
2067489      CORE_CODEGEN    Urgent issue: ncsim  MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x15b)
2069665      CORE_CODEGEN    Internal error at xmvlog-cg stage "gq_pop_constraint - wrong identifier"
2085557      CORE_CODEGEN    xmelab: *E,CUVCGF: Code generation for worklib.uvm_pkg:sv <0x41231003> failed.
2086044      CORE_CODEGEN    elaboration internal error due to uvm_ml_adapter_imp with 19.03
2093570      CORE_CODEGEN    Xcelium causes infinity loop.
2099673      CORE_CODEGEN    xmvlog_cg, *F,INTERR: INTERNAL EXCEPTION gq_finalize_stuck_at_behavior
2105078      CORE_CODEGEN    Provide detailed information on COD generation for UVM/SV code
2119072      CORE_CODEGEN    xmvlog_cg internal exception error with - gq_e_concatenation - word not a tab
2123186      CORE_CODEGEN    PERF : C function svh_castcheck is required to be inlined for standard classes.
1319528      CORE_COVERAGE   Toggle coverage for mod ports inside interface needed
1323358      CORE_COVERAGE   Change expression table for control scoring to take into account short circuiting
1326704      CORE_COVERAGE   support for toggle coverage for modports needed
1326710      CORE_COVERAGE   Toggle coverage support for I/F and modport ports for a module needed
1658614      CORE_COVERAGE   Request interface/modport ports toggle coverage for a module
1774085      CORE_COVERAGE   Unsupported bins-with syntax
1776287      CORE_COVERAGE   coverage pragma not turning off expression coverage when vector scoring is enabled
1785632      CORE_COVERAGE   CNDIR expanded message does not include all reasons why directory cannot be created
1835393      CORE_COVERAGE   Request Toggle Coverage Support for MDA of enums
1860437      CORE_COVERAGE   CNDIR expanded error does not tell user about exceeding linux character limit for directory name
1866993      CORE_COVERAGE   Add support for toggle coverage in instantiated SV interfaces (modports).
1883615      CORE_COVERAGE   Request interface/modport ports toggle coverage for a module
1927517      CORE_COVERAGE   Adding ignore bin to covergroup causes simulation slowdown 10x
1938068      CORE_COVERAGE   CGBNOL warning even though there is no overlapping bins
1938323      CORE_COVERAGE   Internal exception when using set_refinement_resilience and -v200x
1949340      CORE_COVERAGE   Smarter analysis of statically unhittable expression terms in control coverage
1949550      CORE_COVERAGE   Need support toggle coverage for I/F modport
1958659      CORE_COVERAGE   Need option to do pure type-based code coverage to reduce memory footprint
1961787      CORE_COVERAGE   expression coverage not scored properly when $unsigned system function used in expression
1971851      CORE_COVERAGE   SOP expression with nested ternary doesn't seem to be correct
1972669      CORE_COVERAGE   I want to turn on block coverage, but not per-instance block coverage.  I only want type coverage.  I don't see any way
1976155      CORE_COVERAGE   Add support for toggle coverage of interface modports
2029089      CORE_COVERAGE   vManager improper exit - Can't open coverage analysis.
2034354      CORE_COVERAGE   Internal exception when excluding signals w/ -ere
2041623      CORE_COVERAGE   FSM arc is not scored but it must be according to the code
2044564      CORE_COVERAGE   Coverage merging consumes excessive amount of memory, causing improper tool exit
2045250      CORE_COVERAGE   merge of parameterized vector signal shows incorrect range in Variables Pane
2045953      CORE_COVERAGE   expression is marked uncovered when function call used in one term of the expression
2047082      CORE_COVERAGE   xmsim INTERR when -conditional left out of set_expr_coverable_operators
2047525      CORE_COVERAGE   Incorrect number of bins detected in a cross cover point
2056560      CORE_COVERAGE   vManager client crush on coverage merge
2058058      CORE_COVERAGE   Coverpoint sampling issue on element of an array of packed struct
2058912      CORE_COVERAGE   xmsim INTERR when enabling enum array toggle coverage
2060713      CORE_COVERAGE   [Update] FSM Coverage Analysis in IMC show some transitions as uncovered even when the waveform shows the transition
2061258      CORE_COVERAGE   xrun of previously existing snapshot with coverage enabled causes INTERR
2062508      CORE_COVERAGE   bad coverage when function used in expression coverage with set_glitch_strobe
2066940      CORE_COVERAGE   Getting issue in dumping code coverage data base. Using TOOL:	xmsim(64)	18.03-s009
2073618      CORE_COVERAGE   INTERNAL ERROR on coverage dumping phase
2075107      CORE_COVERAGE   IMC FSM transition coverage not being scored correctly
2086118      CORE_COVERAGE   smart_refine: Smart exclusion wrongly excludes extra struct signal
2096860      CORE_COVERAGE   expression is marked uncovered when function call used in one term of the expression and vector scoring is enabled
2097632      CORE_COVERAGE   Internal exception during xmvlog_cg
2122445      CORE_COVERAGE   Coverage model generation iterates over unnecessary instances
2123812      CORE_COVERAGE   code coverage causes INTERR
2136896      CORE_COVERAGE   INTERR xmvlog_cg: Unexpected signal #11, program terminated (null)
2152595      CORE_COVERAGE   Incorrectly reported overlap bins warning CGBNOL
784355       CORE_ELAB       Solve...before on array size results in EXPITT error
800341       CORE_ELAB       solve...before on array size results in EXPITT error
883078       CORE_ELAB       Please enhance the solve before with hierarchical_identifier
1324913      CORE_ELAB       Solve...before on array size results in EXPITT error
1368171      CORE_ELAB       ncelab: *E,CUINFI
1436418      CORE_ELAB       SOPARM error/extended error need improvement
1469574      CORE_ELAB       celab: *E,INNOTR :: initializing Virtual interface using interface instance created inside vhdl_entity
1492654      CORE_ELAB       *E,INNOTR when SV i/f bind into VHDL + uvm_config_db::set
1524645      CORE_ELAB       OOPR to interface enhancement request
1579575      CORE_ELAB       Support OOPR for interfaces
1634615      CORE_ELAB       SV interface binding issue
1650687      CORE_ELAB       ncelab internal error when trying to blackbox/bbconect a module thats getting binded
1696049      CORE_ELAB       ncelab: *E,INNOTR :: initializing Virtual interface using interface instance created inside vhdl_entity
1738799      CORE_ELAB       Please enhance CUVPOM error to report module/instance name that has the bad port connection
1739297      CORE_ELAB       SVBMUF error message should provide hints to use instance binding
1748131      CORE_ELAB       xmvlog: *E,EXPITT (): Expecting a variable of an integral type
1750253      CORE_ELAB       Support assignment to interface member from one primary to another
1769185      CORE_ELAB       SVBDUPI error when instance is already bound when using -libmap or -compcnfg with -nncbind
1781601      CORE_ELAB       TYCMPAT error does not have enough information to debug
1784412      CORE_ELAB       Enhance CUVUNF error to print out instance path of the module which caused the error
1791127      CORE_ELAB       misleading error message regarding non-constant operand assigned to parameter using $sformatf.
1796309      CORE_ELAB       Enhance CUVUNF error to include instance name of problematic block with the OOMR
1805208      CORE_ELAB       EXPITT with solve x before y.size
1817219      CORE_ELAB       CUVUNF elab error on single irun MSIE when adding unrelated bind statement to the CU
1857733      CORE_ELAB       Elaboration not giving required warnings when using sv configs
1874113      CORE_ELAB       NOTDOT for member select of interface port
1875070      CORE_ELAB       VCFGUUR not generated without -libverbose
1884386      CORE_ELAB       VCFGUUR warning message when running with SV configuration and MSIE single irun
1895568      CORE_ELAB       xmvlog: *E,EXPITT: Expecting a variable of an integral type.
1918227      CORE_ELAB       verilog config or libmap file not working as expected, need better ERROR message
1940736      CORE_ELAB       Enhancement req. xmelab: *E,DSSUFE [MSIE] Unsupported formal expression in port connection
1946347      CORE_ELAB       Regarding xmelab NOTDOT error
1946468      CORE_ELAB       xmelab: *W,EVBPRM: bad parameter value in (-gpg) association (pp => /abc/e).
1951019      CORE_ELAB       xmelab: *E,NOTDOT when using $bits on svi signal
1952799      CORE_ELAB       configverbose - add first level module where liblist is applied to
1972366      CORE_ELAB       xrun internal exception
1981029      CORE_ELAB       Confusing error message TYCMPAT for misspelled symbol
1990706      CORE_ELAB       Xcelium config liblist does not warn about non-existent library
1990879      CORE_ELAB       Unable to understand the warning from MSIE v2k config support warnings
1990908      CORE_ELAB       VPI returns wrong lib name when queried for hierarchical vpiConfig property
1993592      CORE_ELAB       OOMR to a VHDL object specified in SV force is not supported .
1993606      CORE_ELAB       CUIMBC error with interfaces
1997972      CORE_ELAB       Support for unpacked structure as a datatype for mailbox
1999322      CORE_ELAB       cross language boundaries for binding of modules issues CUOOMR
1999668      CORE_ELAB       VHDL bind with SV interface does not work
2000057      CORE_ELAB       Calling $size on VHDL to check array size not supported
2008334      CORE_ELAB       Elab failing (internal exception) with xcelium 18.03-s009 version: MESSAGE: if_alloc - <= 0 bytes
2010489      CORE_ELAB       xmelab: *E,MULAXX
2010492      CORE_ELAB       xmelab: *E,ICDPAV
2010510      CORE_ELAB       Need ability to turn on -warnmax 0 for specific mnemonics
2013123      CORE_ELAB       xmelab: *E,CUCIHD : Class inheritance hierarchy instantiation depth (100) exceeded.
2023054      CORE_ELAB       Internal error on final incremental snapshot build with multiple primtop
2030554      CORE_ELAB       localparam bug in Xcelium version 2018.07.001_agile
2033383      CORE_ELAB       xmelab: *F,SOPARM (<..filename..>): Special otp not parameter (529).
2033506      CORE_ELAB       struct used for mailbox not supported
2034450      CORE_ELAB       [MSIE] :Report error for inconsistency for vhdlsync option with incremental partition
2036510      CORE_ELAB       CUPARF on parameter evaluation for a virtual class
2037928      CORE_ELAB       elaboration becomes slower at "CHECKPOIN 15 (after cu_doic1)"
2040953      CORE_ELAB       config uses incorrect libraries for binding
2041148      CORE_ELAB       elaboration performance
2041621      CORE_ELAB       Improper tool exit during elaboration when MSIE is enabled. addr(0xc058)
2041752      CORE_ELAB       erroneous CUIOAI error message generated when referencing hierarchical reference inside generate block
2041824      CORE_ELAB       RTL test case Internal Exception during build with Xcelium EHF versions 19.01-a001-20190110 & 19.02.a001.20190117
2042106      CORE_ELAB       xmelab: *E,CUVUNF error in single step MSIE for out of module reference inside uvm class from module
2044181      CORE_ELAB       Improper tool exit during Elaboration on 18.09-s06 (also tested with agile release18.12-a01) used in 64 bit mode
2045358      CORE_ELAB       Internal error - xmelab/LP - via_get_corresponding_interface_highconn_object
2047186      CORE_ELAB       Elab takes 3 hours for digital case with generate and array
2048857      CORE_ELAB       Internal exception error with Auto MSIE
2050063      CORE_ELAB       [Dynamic Test] *E,DLNORD codegen error
2051239      CORE_ELAB       internal elaboration error with signature: cu_xrenumber_tablet() - We depend upon a tablet which has NULL upscope
2053714      CORE_ELAB       Incremental snapshot build taking long time in SDF testcase
2053914      CORE_ELAB       MSIE, a tool failure for elaboration
2054328      CORE_ELAB       Breakpoint issue
2056479      CORE_ELAB       xmsim Internal Exception error:  MESSAGE: svh_find_itable_entry : Entry for uvm_reg not found inside uvm_reg_map
2057238      CORE_ELAB       xmelab: *F,SVBDUPI (./m1.sv,14
2057556      CORE_ELAB       [Dynamic Test] xmsim Internal Exception error with $fseek
2057967      CORE_ELAB       xmelab: *E,DSSUFE (./aa.v,1
2058175      CORE_ELAB       internal elaboration error with test case that passes in GREEN
2058226      CORE_ELAB       Unexpected CUVUNF on sum with expression without valid array type.
2059186      CORE_ELAB       elab performance slow with varying delay in the tran
2059192      CORE_ELAB       xmelab NOTDOT with $bits usage in Hierarchical name not allowed within a constant expression
2059754      CORE_ELAB       xmelab DYNGPE  hierarchical reference from one primary to another primary
2061079      CORE_ELAB       SARC : Error SVBMIM on primary build
2061081      CORE_ELAB       Huge performance overhead on incremental partition build due to class specialization unification
2061083      CORE_ELAB       Code generation exception error on incremental build : gq_datatype_write_net -  vbits/!TAB or CAB
2062214      CORE_ELAB       Internal exception error when DPI-C is used in parameter declaration.
2064406      CORE_ELAB       improper tool exit during elaboration
2065074      CORE_ELAB       xrun internal error when putting multiple pacakges as ancillary tops in single primary makeprim
2065413      CORE_ELAB       2 dimension array parameter value was overwritten incorectly in generate block
2066071      CORE_ELAB       xmelab: *F,SVMLED: System virtual memory limit exceeded.
2066396      CORE_ELAB       Elab won't finish, more than 24 hours
2066567      CORE_ELAB       internal elab error related to interface in1803/1809/1903 consistently
2066608      CORE_ELAB       -betaperf causes Int. Exception Message: cu_vifc_xtrack_semantically_single_caller_pass1 - fork-join/ no function-task
2070092      CORE_ELAB       Wrong error: MULAXX Multiple drivers to always_comb
2074866      CORE_ELAB       xmelab: *F,INTERR: INTERNAL EXCEPTION : MESSAGE: ddict_create - called whem ddict system is not ready
2076661      CORE_ELAB       MSIE improper tool exit while running incremental: xmelab: *F,SVMLED: System virtual memory limit exceeded
2076817      CORE_ELAB       xmsim crash with fseek function
2082054      CORE_ELAB       Customer seeing E,CSGMSS on 19.03.002. Are there any options to avoid this error?
2091854      CORE_ELAB       xmelab: *F,INTERR: INTERNAL EXCEPTION error observed with partition compile
2096327      CORE_ELAB       xmelab, *F,INTERR: INTERNAL EXCPETION
2096382      CORE_ELAB       Internal exception during elab when migrating from Incisive to Xcelium
2096802      CORE_ELAB       Internal Exception during HAL linting with message sv_seghandler - trapno -1 addr((nil))
2098035      CORE_ELAB       XCELIUM tool crashes during elaboration stage
2098193      CORE_ELAB       MESSAGE: sv_seghandler - trapno -1 addr((nil))
2099168      CORE_ELAB       MSIE fails on TYCMPAT however MONO works well
2099984      CORE_ELAB       xrun: *F,INTERR: INTERNAL EXCEPTION in incremental build of parallel build
2100331      CORE_ELAB       msie build suffers with internal exception sv_seghandler
2102923      CORE_ELAB       xrun internal exception error when trying to recompile a design
2104850      CORE_ELAB       parameterized classes show different default values when compared, casting fails for valid case
2107394      CORE_ELAB       internal exception sv_seghandler found at elaboration
2107479      CORE_ELAB       Wrong behavior with binds while trying to connect a port that doesnt exist in parent/destination module
2110252      CORE_ELAB       TBBLDF error generated when xrun ran with -dpiheader and -errorchk 3
2110422      CORE_ELAB       ivia_pair_sanity_check - vst and ot mismatch : Internal Exception
2120013      CORE_ELAB       Internal error occurred during elaboration
2120561      CORE_ELAB       VHDL internal error during elaboration, while accessing records
2121543      CORE_ELAB       xmelab INTERR : cu_sigpv after adding (-lps_sv_interface_port_enh, -lps_viso)
2123853      CORE_ELAB       xmelab: *F,INTERR: INTERNAL EXCEPTION cu_dvpm_get_fsigid_offset - unexpected nettmp_vhdl_driver
2125159      CORE_ELAB       error in passing interface through modules instantiations in generate block
2125201      CORE_ELAB       liblist based configuration reported via -configverbose
2128391      CORE_ELAB       VHDL Elaboration internal error with vserror
2134152      CORE_ELAB       Unexpected CUVUNF in hierarchical reference primary to incremental
1893032      CORE_GLS        multi-Tiered hierarchical gate level model Flop not properly propagating value unless probed
1919947      CORE_GLS        SDF annotations are different with Incisive and Xcelium
1925395      CORE_GLS        SDF annotation result different between IRUN and XRUN gate level simulation
1935454      CORE_GLS        INTERCONNECT multi source int delays does not annotate correctly.
1957682      CORE_GLS        How to set pulse control to specific instance/module
1969101      CORE_GLS        [GLS enhancement] Warning message is for ignored INTERCONNECT delay.
2013577      CORE_GLS        xmelab: *W,TRNDELAY: Moving the Interconnect delay on net :TB:uut_TOP.top_ana_inst.RESET_inst.IOFT outside of the tran n
2019809      CORE_GLS        GLS : Simulation result is incorrect, even if same SnapShot is used.
2020904      CORE_GLS        SDF annotation not matching in Incisive and Xcelium
2034441      CORE_GLS        gate simulation issue with improper SDF interpretation.
2036455      CORE_GLS        Internal Exception during elaboration when using SDFs with Negative delay and -negdelay
2037098      CORE_GLS        18.09-s006, Internal Exception error during elaboration using SDFs with Negative delay and -negdelay
2048697      CORE_GLS        "-entrandelay" option make iopath delay 0.01ns shorter
2063312      CORE_GLS        Xcelium with options "ENGATECDPMO -tch_stap_cnt 2 -enable_town" shows strange behavior
2065408      CORE_GLS        csi-xmelab - CSI: *F,INTERR: INTERNAL EXCEPTION with sv_sighandler - trapno -1 ((nil))
2066386      CORE_GLS        tranif0/1 delay behaves like Rise/Fall, instead of ON/OFF
2067576      CORE_GLS        GLS sim tool exception error
2071019      CORE_GLS        resetting and rerunning gatelevel simulations with dynamic SDF annotation results in SDFNET warnings
2086430      CORE_GLS        tfile could not work normally
2090421      CORE_GLS        Hold time timing violation with huge hold value, negative timing calculated by tool seems not correct
2094261      CORE_GLS        [MSIE] INTERR, MESSAGE: ptrblk: rwire is supply
2098602      CORE_GLS        Internal Error during running $dumpvars
2109169      CORE_GLS        Issue with backannotation - Signals become undefined when crossing the scope of the design
2109373      CORE_GLS        Internal error during simulation when SDF is annotated.
2114692      CORE_GLS        xmelab Internal Exception with sv_seghandler -trapno -1 addr message
2119856      CORE_GLS        Internal exception during gate level elaboration.
2121369      CORE_GLS        continuous assignment does not work for unpacked dimension signal
2123190      CORE_GLS        xmelab: *F,INTERR: INTERNAL EXCEPTION
2125696      CORE_GLS        xmelab: *W,SDFRDE: Read error for default code, skipping annotation of chip_top.verilog.sdf.worst.gz.X.
2147716      CORE_GLS        Difference in SDF annotation seen between Xcelium and Incisive
1548136      CORE_LP         support VHDL attributes to define RTL parts as always_on
1640256      CORE_LP         Support isolation in SV interfaces
1649309      CORE_LP         SVI arrays are not supported in low power simulations (UPF)
1686816      CORE_LP         support of create_power_state_group along with all new -supply/-group…  options in add_power_state
1701277      CORE_LP         Enhance IES to support the same supply net in both RTL and UPF
1724973      CORE_LP         UPF: wildcards in connect_supply_net -ports don't work on UPF ports
1788322      CORE_LP         LBRTPM message reports internal_power, direction internal, as mismatch with RTL
1805793      CORE_LP         [lps-cpf] Handling of escape character in Verilog object
1860989      CORE_LP         Print a NOTE when an SDA attribute is encountered that LP doesn't recognize
1870465      CORE_LP         [NCsim]: UPF restore_condition issue when 3-d array with multiple assignments
1882930      CORE_LP         add support for add_power_state_group and add_power_state_group -group
1896253      CORE_LP         Always block not getting replayed after power up because the driver is an OOMR
1897981      CORE_LP         Support supply nets defined in both the RTL & UPF .
1922661      CORE_LP         Tool is not connecting the power port of level-shifter isolation combination as per expectation
1937805      CORE_LP         *E,NOPPIN:Primary power doesn't exist in Liberty cell
1951558      CORE_LP         Support of clk_low retention model
1956483      CORE_LP         Isolation outside of terminal boundary using -sink
1967322      CORE_LP         *E,ILLAKO with multidimensional array pin driven by create_power_switch -ack_port
1997761      CORE_LP         [UPF enhancement] support of create_power_state_group.
2000729      CORE_LP         1801_LINT_CMD6 Tcl issue in command: extra characters after close-brace
2002957      CORE_LP         Command support request: create_power_state_group & add_power_state -group
2005208      CORE_LP         [UPF] set_repeater command support
2005210      CORE_LP         [UPF] -applies_to_boundary support
2012531      CORE_LP         support for -power_source in LP simulation
2015534      CORE_LP         UPF  : Not Insertion a virtual ISO on boundary of MacroModel
2028894      CORE_LP         State retention performance enhancements
2030740      CORE_LP         nxmbind with CPF causes  ILLOBJM messages, old bind does not
2035316      CORE_LP         ncelab Internal Exception error while migrating from INCISIVE to XCELIUM
2038090      CORE_LP         the behavior of connect_logic_net without -reconnect is unexpected
2041132      CORE_LP         *W,SNDRMU should list the drivers responsible for the warning
2043989      CORE_LP         message identifying a missed connection when there is a rtl with liberty cell instantiated within another rtl with liber
2047027      CORE_LP         Manage collision between HDL nets and 1801 supply_nets
2047068      CORE_LP         make automatic connections to liberty cells that are instantiated within SV bind code
2047069      CORE_LP         xmlib2cdb generates a strange error
2048741      CORE_LP         ncelab: *F,INTERR: INTERNAL EXCEPTION ( sv_seghandler - trapno -1 addr(0x8) )
2050671      CORE_LP         xmlib2cdb support environment variables in in -lib_mfile
2050742      CORE_LP         Support implicit port connections in 1801
2052775      CORE_LP         LP MSIE INTERR because of an internal msie file
2053862      CORE_LP         Force is not reapplied after domain is powered in 18.09 with CPF
2055087      CORE_LP         xmelab Internal Exception error: cuv_lpeswait - not ESWAIT
2057430      CORE_LP         alias upf onto hdl for pg pins defined in same scope
2062570      CORE_LP         Same lps options(5) exist in betaperf and new perf
2063283      CORE_LP         Simulator Internal Exception error while running UPF sims
2065160      CORE_LP         DFF doesn't recover if you use SV interface to pass clock and reset
2065772      CORE_LP         Remove direction check from lps_pa_strict
2068120      CORE_LP         Xcelium issues incorrect error when a define_power_model -for contains a list of cells
2070724      CORE_LP         UPF produces internal error
2071410      CORE_LP         Isolation added during synthesis, but not in LP simulation
2072072      CORE_LP         Unprotected LPS assertion file which made by -lps_verify_unprotect causes Warning.
2074435      CORE_LP         Forces in LP consume huge amount of memory
2074991      CORE_LP         nmi DFF doesn't recover if you use SV interface to pass clock and reset
2078661      CORE_LP         lps_relax_hierarchy option : the report of instances name displayed twice.
2079083      CORE_LP         Integrate 1801 Linter bug fix  release
2079174      CORE_LP         dma_req_pending DFF doesn't recover if you use SV interface to pass clock and reset
2079452      CORE_LP         Low Power simulation crash during wake up after a deep sleep
2080449      CORE_LP         lps_iso_hybrid doesn't generate NORPCN error for missing explicit connections to backup power of ret cells
2081097      CORE_LP         Generate error message if create_power_domain -exclude_elements is used
2081778      CORE_LP         Provide time spent in liberty compilation as part of -status3
2082120      CORE_LP         xmelab: *E,PSCNFLT: [LPS] A power source domain and its base domain cannot be declared as power source simultaneously.
2084352      CORE_LP         1801 processing incorrectly issues error if object of create_logic_port/net already exists
2085849      CORE_LP         Power up restore not working with clk_low_strict
2091379      CORE_LP         Reset is not honored in the new clk_low_strict retention model
2094702      CORE_LP         LIBDTM should Not be a soft error message
2095423      CORE_LP         Phase 2 implementation of clk_low_strict retention model
2095573      CORE_LP         add location of force command to *E,FONOVA error message
2095587      CORE_LP         *E, FONOVA causing several tests to fail in pre-qual
2095650      CORE_LP         Clock low strict retention latch gets corrupted on the save edge
2096478      CORE_LP         Support latest UPF linter ( d016)
2096815      CORE_LP         clk low strict retention applied to latch even though -target_type flop is in state retention rule
2098376      CORE_LP         Spurious LP force at power-up causes test failure
2098492      CORE_LP         Do not create NOISELE for design top without testbench when -location self is used
2098939      CORE_LP         make xmelab: *W,CFLCPG a strong error instead of warning
2099042      CORE_LP         Message on the ARM retention rule violation
2104163      CORE_LP         *W,LPSFREXPR warning in LP simulation with latest green release
2106362      CORE_LP         Registers getting excluded from retention policy for no evident reason
2106800      CORE_LP         Make the option -lps_pacell_disable_ic default behavior
2107513      CORE_LP         xmelab internal error in LP simulation
2110798      CORE_LP         Replay of continuous assignment outside of process not executing on wake up
2111625      CORE_LP         Internal error on apply_power_model with customer design
2116729      CORE_LP         port in UNDETERMINED while using pre-compile liberty - in 19.06.e313
2117402      CORE_LP         *E, PSILLPM: [LPS] A power source domain and its mapped parent domain cannot be declared as power source simultaneously
2118027      CORE_LP         State retention of packed struct type register doesn't work correctly
2118978      CORE_LP         Force disappears incorrectly in LP simulation resulting in test failure
2119933      CORE_LP         set_design_attributes does not get applied when used at the top level
2120767      CORE_LP         UPF : PST result is incorrect when to use logic_expr_drives_supply_expr attribute.
2122519      CORE_LP         elab error with *W,LIB1801/*E,UDFUOBJ - UPF commands like create_power_domain are not applied when cell has liberty
2123716      CORE_LP         INTERR when PA models are used instead of NPA models
2128963      CORE_LP         Forces do not work for array of instances as expected
2130205      CORE_LP         xmelab *F: INTERNAL EXCEPTION during elaboration with Xcelium 19.03s005
2131727      CORE_LP         LP issue - always_latch doesn't wake up when power is turned on
2134576      CORE_LP         Will the retention work if the simstate of retention supply is in CORRUPT_ON_ACTIVITY state?
2138756      CORE_LP         SNDRMU warning - show net name rather than port name
2139107      CORE_LP         Internal exception when simulating with UPF
2142619      CORE_LP         Reset is not honored for a clk violation at restore_edge with clk_low_strict retention even if the reset is asserted
2142635      CORE_LP         improper exit during elaboration at pwr_ptop() with EHF kit 19.08e419 which has clk_low_strict retention phase 2 fix
2153405      CORE_LP         Internal Exception during elaboration in pwr_ptop () while running the design in 1909 Beta kit
1544021      CORE_PARSE      protected typedef not allowed in incisive
1659327      CORE_PARSE      covergroup instance is dumped even though instantiation/new is in code that is not hit.
1677393      CORE_PARSE      ncvlog internal exception error due to undefined variable. MESSAGE: p4_mexpr - default VST_U_EXPRESSION
1694043      CORE_PARSE      Internal error with ncvlog due to wrong selection of label's name - Unexpected signal #11, program terminated (null)
1726617      CORE_PARSE      False parser NOTFXX error for struct initialiser
1728503      CORE_PARSE      Ports being treated as variables when they should be wires
1747415      CORE_PARSE      deposit prevents verilog actual driver
1756809      CORE_PARSE      Add switch to prioritize packages in own library.
1763741      CORE_PARSE      *E, UNDIDN: Undeclared identifier even after using typedef.
1790032      CORE_PARSE      constraint reference to struct/union in class defined in package results in ILLHIN error - works in vcs
1796343      CORE_PARSE      inline constraint does not recognize class object from a parameterized class of an inheritance
1817656      CORE_PARSE      INCISIVE Compilation is 8X slower as compared to competition
1888502      CORE_PARSE      typedef derived from 2-state typedef becomes 4-state
1947292      CORE_PARSE      some parameters not being passed correctly when parameter functions used
1949220      CORE_PARSE      E,ILLHIN unresolved when refer the member variable of base class in constraint block.
1953993      CORE_PARSE      option to convert all compilation warnings to errors by single flag
2022043      CORE_PARSE      Linking macro with string in readmemh
2029415      CORE_PARSE      Inline constraint on object member variable not working when class being randomized is a mixin
2031771      CORE_PARSE      The defparam doesn't overwrite to parameter.
2032788      CORE_PARSE      A comment after the /* sparse*/ declaration results in error:E,REGSOV:(./rtl_memory.v,12
2036317      CORE_PARSE      Incisive / Xcelium segfault on generated RTL
2036846      CORE_PARSE      Incisive segfault on Stratus generated RTL
2052990      CORE_PARSE      ncvlog internal error issue 'el_start_list_at - increase EL_NESTSIZE!'
2053279      CORE_PARSE      xmvlog can't handle Japanese Character as syntax error
2053464      CORE_PARSE      xmvlog internal exception with relax_svbind_target and new bind
2053471      CORE_PARSE      xmelab internal error with relax_svbind_target:   MESSAGE: cu_process_declaration - VST_E_UNKNOWN
2054423      CORE_PARSE      input ports with unpacked array dimensions defaulting to variable instead of wire
2057279      CORE_PARSE      macro cannot be parsed inside quotation marks
2061063      CORE_PARSE      Unexplained ILLHIN: illegal location for a hierarchical name (in a package)
2061807      CORE_PARSE      recompilation failing on SV import of vhdl packages with -v200x switch
2065920      CORE_PARSE      INTERR - smi_set_sm - object is only a SMI_1ST class yet sel == 1
2066344      CORE_PARSE      xmvlog internal error on February agile release
2067271      CORE_PARSE      SPDUSD warning suppressed with -q even after promotion to error
2076143      CORE_PARSE      Getting UNDIDN error when vectors are referred from extended class.
2081938      CORE_PARSE      xmvlog Internal Exception error on nightly debug agile
2090622      CORE_PARSE      WBINOPAR needs to be an error
2105431      CORE_PARSE      xmelab *F via_get_ots_field: No ots structure of kind 49 exists
2157866      CORE_PARSE      compaliation error at non-defined area
2159152      CORE_PARSE      default_array_input_wire not working on unpacked array of ports with bind syntax
2161260      CORE_PARSE      Unexpected NOPAR in assignment pattern with field name matching function name
1240722      CORE_RAND       constraint solver not consistent on array size
1336226      CORE_RAND       constrain on array element  is ignored
1464598      CORE_RAND       Problem with SV constraint
1494934      CORE_RAND       Randomization problem with function-argument call
1495719      CORE_RAND       2D array with inside constraint on the size
1503905      CORE_RAND       Change of randomization order needed?
1536253      CORE_RAND       Unexpected failure from foreach loop referencing 2D array
1536756      CORE_RAND       Randomization performance issue in 14.21
1698241      CORE_RAND       Randomization is taking a very long time and increases runtime memory footprint 10times.
1767066      CORE_RAND       False contradiction when using sum() on object elements
1819615      CORE_RAND       Constraint contradiction for a solvable constraints
1871350      CORE_RAND       Randomization performance degrades as simulation progresses
1936927      CORE_RAND       Randomisation failure
1952356      CORE_RAND       Randomization distribution not correct in Xcelium
1955185      CORE_RAND       disable soft not working on element of array of object.
1977529      CORE_RAND       Functionality of soft disable on a class array element.
1989068      CORE_RAND       Multi-pass issue with pre-TRAT. TRAT is failing over: array size on inner dimension ( rnc_array.cpp,
1990213      CORE_RAND       xmsim: *E, RNDCNSTE due to "Solve before not allowed on empty array"
1996141      CORE_RAND       Problem constraining 2D queues
1999665      CORE_RAND       Need to make this Multipass testcase working with TRAT
2008229      CORE_RAND       xmsim: *E,RNDCNSTE (./const_struct.sv,13
2011657      CORE_RAND       TRAT_NOT_IMPLEMENTED: array size on inner dimension
2012645      CORE_RAND       TRAT not implemented instances in customer code
2014412      CORE_RAND       Array resize and multipass
2024170      CORE_RAND       Enhance SVRNC to support solve-before on MDA items
2032777      CORE_RAND       Randomization with soft constraints creates unexpected results
2035607      CORE_RAND       support limitation of calculation floating point number in constraint
2041133      CORE_RAND       Solver is giving a contradiction message, same partition solved on previous versions
2045895      CORE_RAND       randomization Internal Exception -- Assertion !wif_lists_empty failed
2047661      CORE_RAND       Make XLGENENV have N severity instead of W and make XCELIGEN__* env vars work silently
2048518      CORE_RAND       *W,RNDOCS, conflicting constraints on dynamic array sizes. (Failed on TRAT, too)
2049012      CORE_RAND       Partition is giving a contradiction on 19.01.a001 but solved on 18.07.v001
2049236      CORE_RAND       Constraint solver multipass shows contradiction
2054439      CORE_RAND       Multipass needed to solve multi dimension dynamic array
2055785      CORE_RAND       W,RNDCNSTW output shows a randomize call in the pre_randomize() call of the actual problematic randomize call
2056443      CORE_RAND       Partition is showing a contradiction message with xceligen , solved properly on earlier release
2056475      CORE_RAND       real constraints partition contradicts on 19.01 solved on 18.07
2057877      CORE_RAND       Randomization not working properly
2062866      CORE_RAND       Xcelium 18.09 randomize performance even worse than IES 15.22.038
2064192      CORE_RAND       Incorrect RNDFUNAC warning, polluting log files
2064728      CORE_RAND       Getting SAT timeout for unclear reason
2068871      CORE_RAND       RNDERR cause Internal exception in TRAT
2069421      CORE_RAND       Internal exception in the solver. Pointing to: rnc_node_solver::rr_add_enum_ranges_to_wif(...
2081169      CORE_RAND       Randomization performance issue seen with user testcase
2081929      CORE_RAND       Solver solves with a value that does not match constraint
2082353      CORE_RAND       Incorrect randomisation results, caught with checkers=2
2083710      CORE_RAND       New solver order alg is causing an error with latest nightly
2085417      CORE_RAND       xmsim: *F,SCSIG: Signal SIGFPE raised by a SystemC library call from user application code.
2089614      CORE_RAND       TRAT is failing for customer with latest nightly build
2089750      CORE_RAND       MESSAGE: sv_fpehandler - user generated SIGFPE
2092735      CORE_RAND       TRAT failover possibly causing pre_randomize to not be called
2094103      CORE_RAND       Randomization failure without any explanation
2101302      CORE_RAND       Xcelium Constraint solver seems to ingnore the constraints.
2101620      CORE_RAND       TRAT solver fail with "rolling over to Pre-TRAT mode" then Internal Exception
2102798      CORE_RAND       Partition solved on 18.06, takes X60 more time on 19.03
2106229      CORE_RAND       RNDALF: Not enough information to debug
2107217      CORE_RAND       Constraint solver has problem interpreting a parameter if it is a 2-dimensional packed array.
2108424      CORE_RAND       segmentation fault in simulation
2109311      CORE_RAND       randomization doesn't work properly
2109595      CORE_RAND       TRAT solver required for a constraint but causes improper exit in 19.03.s005
2111451      CORE_RAND       Randomization error in 19.05. Was working in 19.04
2111673      CORE_RAND       RNDCNSTE for constant guard expression
2112581      CORE_RAND       SVRNDF error seen in TRAT
2117569      CORE_RAND       Constraint size failure of multidimensional array through foreach command for second dimension
2122827      CORE_RAND       segmentation fault from CCMPR02108424 reappearing in 19.06.a001
2125902      CORE_RAND       INTERR Internal Exception: illegal list underflow -  stacktrace shows svrnc calls before exception
2128775      CORE_RAND       static_analysis_data::replace_var_arefs: rand aref on assoc array ( rnc_solver.cpp,5726 )
2128797      CORE_RAND       TRAT still failing to call pre_randomize
2134203      CORE_RAND       Simulation is failing with rnc error inside wpi.cpp
2147303      CORE_RAND       SV constraint solver doesn't honor soft constraint
1462904      CORE_SIM        Not possible to probe SV structs with BIG arrays
1498623      CORE_SIM        Subprogram body: PRINT_NODE (line: 775 in design unit UVVM_UTIL.HIERARCHY_LINKED_LIST_PKG:body)
1499988      CORE_SIM        VHDL2008 compilation: internal exception
1545212      CORE_SIM        Internal Exception with OSVVM
1572980      CORE_SIM        ncsim/RTSOVF - max size of dynamic array provided in error code message is incorrect
1584938      CORE_SIM        Systemverilog support for force of an entire unpacked array.
1590905      CORE_SIM        TSKFUN does not give enough information to debug problem
1743400      CORE_SIM        ncvlog: *E,UNSFRC (test.sv,8/27): Force/release of unpacked array nets is not currently supported.
1782197      CORE_SIM        process::halt not effective for children of finished threads
1825546      CORE_SIM        Memory RTL Model Performance Enhancement
1851002      CORE_SIM        Please update ncprofmem.pl in xcelium installation so it matches Xcelium Branding
1868018      CORE_SIM        x-prop fails to detect behavioral construct === 1'bx
1954264      CORE_SIM        $countdrivers memory consumption issue (3G)
1971917      CORE_SIM        The process-based save/restore creates a .process_save directory which doesn't follow umask settings
1976213      CORE_SIM        fine grained xprop enables
1985008      CORE_SIM        using 'xrun -write_metrics' modifies UVM_TESTNAME xrun plusarg
1992714      CORE_SIM        Complimentary scanning failing due to specman filter being automatically applied to incorrect logfile
1992892      CORE_SIM        xprop fox mode not propagating X for synchronous flop
1993570      CORE_SIM        Supported VHDL OOMR target (signal) is giving error when hierarchically referenced.
2007972      CORE_SIM        Internal Exception seen in Incisive
2012149      CORE_SIM        SAIF format not readable by Synthesis tool
2018909      CORE_SIM        Significant slowdown from non-blocking assignments
2020261      CORE_SIM        Compilation internal error with  vst_class() - null ptr
2022254      CORE_SIM        xmsim *F XPROF Internal Exception error
2032781      CORE_SIM        INTERR: SIGSEGV in non-blocking assignment to virtual interface variable from class
2034617      CORE_SIM        memory profiler numbers are not consistent
2039306      CORE_SIM        internal simulation error sv_seghandler - trapno -1 addr((nil))
2039750      CORE_SIM        xprof Internal Exception error with MESSAGE: Xprof database dump failed!
2042271      CORE_SIM        xmsim Internal Exception with specify block and -sdf_simtime in MSIE flow
2043312      CORE_SIM        xmprofmerge.pl does not exist in the install area
2043434      CORE_SIM        -mem_xpof -profcstk not showing relevant information
2043534      CORE_SIM        index from for loop in fork/join mixed
2043603      CORE_SIM        Multi-step MSIE internal error during simulation, however Mono and 1-MSIE works fine
2045954      CORE_SIM        -memdetail loosing track of freed memory
2045961      CORE_SIM        -memdetail should provide memory footprint overhead on memory report
2047707      CORE_SIM        Simulation failing
2048454      CORE_SIM        replay wreal internal error with rpl_traverse-inspector
2049429      CORE_SIM        The log information is incorrect when to use -status and -simlogsize both.
2049783      CORE_SIM        customer testcase failure with "newperf" option
2049938      CORE_SIM        xmelab internal error:  vst_contains - id not identifier, class 750
2049943      CORE_SIM        xmelab internal error: cu_update_assign_amalg - bad subsumed
2050438      CORE_SIM        Dramatic performance degradation when probing dynamic arrays
2050450      CORE_SIM        Xmelab internal error : vst_contains - id not identifier, class 750
2051968      CORE_SIM        xmelab error: flatten_expr - index selects of arrays not handled yet
2053006      CORE_SIM        fault simulation internal error with HDLICE memories
2054745      CORE_SIM        Entire regression results showing as failed in vManagerCS though some are passing
2056754      CORE_SIM        [FATAL] Failed to create timer thread (errno: 22)
2061175      CORE_SIM        Xprop issues XFAINC warning message but generate-endgenerate hierarchy path is valid
2061214      CORE_SIM        VHDL record port does not get value from packed struct
2062695      CORE_SIM        Dumpsaif does not generate a toggle count for implicit wire connection
2063507      CORE_SIM        Performance issue with L2W on parameterized modules
2063559      CORE_SIM        LTW - -enable_var_opt_core changes BNDWRN to BNDERR
2064420      CORE_SIM        xprop -- x not propagating when delay is specified with time unit
2064857      CORE_SIM        CLONE internal error: sv_seghandler trapno -1 addr ((nil))
2065137      CORE_SIM        Functional discrepancies between 2 same simulation, works fine with linedebug and fails without linedebug
2065166      CORE_SIM        Collapsed network of converted logic has been forced: Provide messages to help in debug under option
2065921      CORE_SIM        assign statement fails to update under -enable_var_opt_core
2066174      CORE_SIM        Sometimes D=>Q cannot transfer in always block
2067950      CORE_SIM        internal Elab error with L2W - sv_seghandler - trapno -1 addr((nil))
2067954      CORE_SIM        internal Elab error with L2W dt_is_array hit unknown datatype
2068065      CORE_SIM        xp_elab.log corrupted
2068352      CORE_SIM        nettmp_is_finalized - id out of range - Internal Exception error during elaboration, introduced by -enable_var_opt_core
2068707      CORE_SIM        sv_bushandler - trapno -1 addr((nil))  - SIGBUS not in rts_xfer -enable_var_opt_core
2068734      CORE_SIM        INTERR: cuv_pewaitset - reads (but not writes) to non-wire during xprop testing
2068853      CORE_SIM        logic-real-logic connection behavior changes with LTW
2069270      CORE_SIM        SST2ER: SST2 interface error:  Series sort buffer maximum size reached.
2069875      CORE_SIM        Switch naming and messages to use Var to Wire
2071618      CORE_SIM        Internal Exception error when dumping waves and coverage is enabled with en_vaca_opt(default setting)
2072050      CORE_SIM        improper tool exit during Elab with VTW file
2073776      CORE_SIM        flatten_expr crash during elaboration with VTW
2073827      CORE_SIM        How to improve FSDB dumping performance , which is about 1.1~1.6x time behind competitor.
2074854      CORE_SIM        Simulator internal error while trying to add a signal to the VCD database
2074874      CORE_SIM        Elab improper exit when W access is removed from build
2075028      CORE_SIM        Severe degradation in Elab time: "After third cu_dop2nlrefs"
2075576      CORE_SIM        Mirror on array of reals provides an internal exception error
2075666      CORE_SIM        mirror to array of reals issue unexpected Error : *E,NCTYMM
2076908      CORE_SIM        xmsim tool failure when dumping VCD for gate-level mixed-signal design
2077127      CORE_SIM        Xprop issues XFAIND message for a named for-loop block within generate/endgenerate
2077864      CORE_SIM        xmelab *F, MESSAGE:  dt_get =_known_datatype hit unknown datatype
2078586      CORE_SIM        INTERR sv_seghandler
2078591      CORE_SIM        xmsim internal vst_root if_ptoroot
2079011      CORE_SIM        TCF file written by xcelium was adding non-numeric string (,) in the duration value
2079501      CORE_SIM        Customer design fails with -ENABLE_NTICM
2081895      CORE_SIM        TCF file for VHDL generate block is not complete
2081898      CORE_SIM        VL_XMBV suppresses xprop warnings
2081941      CORE_SIM        Need help debugging source of PROPTH error
2082514      CORE_SIM        Xcelium internal error with VCD dumping
2084323      CORE_SIM        FATAL ERROR DURING INCREMENTAL COMPILATION
2085641      CORE_SIM        signals concatenation not updated in module port connection
2086051      CORE_SIM        SHM dump run without access leads to SCHECK firing and Internal Exception
2087092      CORE_SIM        INTERR when $xm_mirror used in constructor of class
2087671      CORE_SIM        The simulation behavior different when added -linedebug option
2088965      CORE_SIM        Internal Exception error when force on unpacked array in GUI mode
2088997      CORE_SIM        problems with Tcl command value -keys
2089084      CORE_SIM        xmsim INTERRR while probing MESSAGE: probe_install_shm - switch
2090092      CORE_SIM        gq_taskfunc_prune_enable - incorrect type for VST_S_NONBLOCKING_ASSIGNMENT
2090123      CORE_SIM        XP_INSTANCE_INFO gives incorrect hierarchy for AOI
2091073      CORE_SIM        OSS profiler becomes unresponsive with xmsim for 12.5/12.6 version; improper exit in 12.4
2091476      CORE_SIM        E*, NOTPAR error causing many builds to fail
2091507      CORE_SIM        memory corruption during simulation with stack overflow, asan backtrace attached
2092127      CORE_SIM        Error due to permission differences between -process_save and -checkpoint_enable
2092356      CORE_SIM        E,NOTPAR happens at the xmelab with enable_var_opt_core
2093506      CORE_SIM        incorrect NOTPAR error on element of nested structs
2094150      CORE_SIM        xmelab INTERR: dt_get_known_datatype hit unknown datatype
2094656      CORE_SIM        Internal Error during profile dumping when using -enable_prof_info
2096016      CORE_SIM        GLS UPF simulation becomes unresponsive at _wordcopy_fwd_aligned via sslu_codprb_force()
2096914      CORE_SIM        initialization failure with -enable_var_opt_core
2096927      CORE_SIM        xmvlog: *E,UNSFRC (tb.sv,19
2097947      CORE_SIM        xmvlog_cg: *F,INTERR: INTERNAL EXCEPTION
2097948      CORE_SIM        xmelab Internal Exception when running with option -lwdgen
2100639      CORE_SIM        Symkeepsim stuck at popen call in prof_run_nm function
2100984      CORE_SIM        -enable_sync_comb not working in my environment
2103278      CORE_SIM        -enable_sensitivity_opt causing simulations to become unresponsive
2104011      CORE_SIM        Xprop LP simulation becomes unresponsive at time 0 with latest green release
2104472      CORE_SIM        Simulation fails without -access +rwc
2105867      CORE_SIM        xmelab: *F,INTERR: INTERNAL EXCEPTION
2106861      CORE_SIM        Questions about clocking block output delay
2107533      CORE_SIM        Improved messaging and reporting for XPUCI
2108008      CORE_SIM        INTERR: probe_install_shm - switch
2108671      CORE_SIM        xmelab internal error: tl_reg_prune_count - no pruned blocks
2108790      CORE_SIM        xmsim internal error with Cadence OCP VIP and enable_reg_update_inv option under newperf
2111039      CORE_SIM        INTERR: illegal list underflow
2115245      CORE_SIM        Incorrect or missing XFSTNC/XFSTND
2115993      CORE_SIM        simulation hang with performance options set
2118325      CORE_SIM        -access +r with xprop enabled causes misbehavior
2124299      CORE_SIM        Customer test case cu_optimize is taking 1243 seconds on nightly agile
2128692      CORE_SIM        csi-xmelab - CSI: *F,INTERR: INTERNAL EXCEPTION
2130430      CORE_SIM        Complex combinatorial assignment calculates the wrong value
2134193      CORE_SIM        Existing force on reg causes simulation internal error when specifying xmreplay
2135239      CORE_SIM        Wrong message from lmstat - Xcelium Multi Core - Simulation does not use Multi Core engine
2140009      CORE_SIM        INTERR: sv_seghandler in ssl_pwr_sn_driver with -lwdgen
1317224      CORE_SV         SIGUSR message issues
1371867      CORE_SV         Please add a note to this DPI warning telling the user how to fix it now
1406753      CORE_SV         SIGSEGV from user DPI code must call ncdbg_fatal
1426872      CORE_SV         Regarding ncvlog_cg: *E,UOPAW
1526705      CORE_SV         ncvlog_cg: *E,UOPAW : Unsupported array assignment to output variable port
1671705      CORE_SV         SIGRNG warning does not indicate what will happen
1697358      CORE_SV         [SEAGATE] ncelab: *F,CGFAIL: Code generation failed for one or more modules.
1709638      CORE_SV         SV unsupported syntax
1752933      CORE_SV         SIGRNG warning does not explain the resulting behavior
1755573      CORE_SV         elab warning to error
1771588      CORE_SV         NOFDPI fatal error needs to include file/line where the DPI import exist
1893009      CORE_SV         ncvlog_cg: *E,UOPAW  Unsupported array assignment to output variable port 'oIqReqClear'.
1994676      CORE_SV         xmsim: *E,OBNOVL: Object does not have a value: uvm_pkg::uvm_resource_db#(virtual interface bus_if)::m_show_msg.rsrc.
2019901      CORE_SV         INTL_LKF: Xcelium giving unsupported feature issue
2024155      CORE_SV         A switch that would print when the simulator entered or exited DPI calls
2034490      CORE_SV         incorrect result due to wrong subtraction calculation
2041285      CORE_SV         INT_LKFC: getting elab error SOLNAB  Need support streaming concatenation to output/inout port of type unpacked struct
2043493      CORE_SV         OOMR which has the vecotor index outside of declared range makes event triggered.
2044376      CORE_SV         INT_LKFC:xmelab: *E,PCANLV:Expression connected to an 'output', 'inout', or 'ref' port/terminal must be an lvalue.
2044958      CORE_SV         INT_LKFC:xmelab: *E,SOLVNT:Streaming concatenation expression of nets is not a legal lvalue
2044959      CORE_SV         INT_LKFC:xmelab: *E,SOLVNT:Streaming concatenation expression of nets is not a legal lvalue
2052808      CORE_SV         xmelab INTERR : cu_sigpv - unexpanded REG in concat
2057494      CORE_SV         error: '_unit_0__t_fe_events_tlm_signal_list {aka struct <anonymous>}' has no member named '_a6'; did you mean '_a0'?
2061138      CORE_SV         perf degradation for always block
2071284      CORE_SV         ncvlog_cg: *E, UOPAW, Unsupported array assignment to output variable port
2080417      CORE_SV         LP primary snapshot generation fails with - vst_declarative_items() - invalid class, class 1023
2085942      CORE_SV         LP elaboration INTERR - cu_lpii_merge_ports_for_isolated_pot - !iso_pot
2088880      CORE_SV         Clocking blocks deadcode - should support SV interface and SV checker
2089711      CORE_SV         Support isolation on SV interface - with clocking blocks.
2090147      CORE_SV         MESSAGE: vst_declarative_items() - invalid class
2090156      CORE_SV         MESSAGE: sv_seghandler - trapno -1 addr(0xb)
2092768      CORE_SV         ixcom:xmelab: *E,UNADIR: Unable to create directory
2095258      CORE_SV         Elaboration error when running with "-dpiheader" and "-errorchk"
2099725      CORE_SV         INTERNAL EXCEPTION xmelab during codegen
2100935      CORE_SV         [Ehancement req.] foreach illegal for wildcard index of associative array(Currently unsupported)
2106531      CORE_SV         significant performance issue using 3rd party VIP in xcelium
2108679      CORE_SV         Default clocking appearing as a clocking block on profiler
2108749      CORE_SV         INTERR cu_vifc_check_access - mark flags mismatched with 19.06.h275
2116792      CORE_SV         xmprotect behavior unclear
2124523      CORE_SV         NOCLNG warning when systemC is not used
2131887      CORE_SV         Elaborator error DPIEXP with DPI export function in _sv_export.so
2132056      CORE_SV         Value deposit failed due to -disable_sv_access under plusperf
2034041      CORE_SYSC       Make the SystemC .so library loading behavior under env var XM_LOAD_SC_LIB_STRICT as the default behavior
2040851      CORE_SYSC       xrun strips gcc options containing '@' symbol
2053863      CORE_SYSC       Introduction of a "nouvmsc" switch to Xcelium (xmsc_run/xrun)
2089971      CORE_SYSC       XMSC_SC_TIME_CHECKS modifies system behavior
1363255      CORE_VHDL       ncsim fatal error with OSVVM
1410599      CORE_VHDL       Support VHDL 2008 Unconstrained array type oomr
1659887      CORE_VHDL       VHDL 2008 simplified case statements fail with Incisive
1825035      CORE_VHDL       Try to simulate VHDL OSVVM Testbench
1837969      CORE_VHDL       Compile error when using vhdl function maximum. [function MAXIMUM (L: T) return E;]
1934035      CORE_VHDL       Assert statement present in to_unsigned subprogram leads to disable of PES optimizations
1941632      CORE_VHDL       VHDL Assignment Incorrect
1944611      CORE_VHDL       Cannot compile OSVVM test suite
2018065      CORE_VHDL       VHDL Scheduling issue when InterProcessCommunication signals were bundled into records
2024683      CORE_VHDL       All sensitivity fail with array (VHDL-2008)
2036161      CORE_VHDL       internal exception at ncvhdl_cg with error SELPFX, DLNCOD
2043703      CORE_VHDL       improper exit after SELPFX
2045092      CORE_VHDL       VHPI improper exit with vhdlsparsearray
2083059      CORE_VHDL       MESSAGE: Unable to evaluate vector expression at gq_eval - RANGE_BOUND
2103253      CORE_VHDL       internal error vlog_port_association_list - Illegal VHDL name for port after NOLDUS
2107885      CORE_VHDL       Specman overwrites a forced signal
2032118      CORE_VPI        Unable to determine what bind, `include, and import statements are in the compilation unit scope
2048346      CORE_VPI        need vpi interface for dot-star(.*) port mapping instance to external customer
2065935      CORE_VPI        VPI error: NOFORCO when LTW option is used
2080362      CORE_VPI        Unexpected format value (0) on value change callback - user format was 5
2104882      CORE_VPI        VPI INVPINT Invalid property vpiACCSupported for object of type vpiEnumNet passed to vpi_get()
2106298      CORE_VPI        Internal VPI error experimenting with debug tools
2131169      CORE_VPI        Incorrect representation of always block in LWD mode when OOMRs are involved
1576289      DBG_SIMVISION   Renamed bus saved in waveform signal list does not load
1707976      DBG_SIMVISION   Analog overlay inside a group goes missing when .svcf file is loaded again
1816115      DBG_SIMVISION   Problem in using analog overlay group
1911423      DBG_SIMVISION   In simvision(64) 15.20-s024 if I Create and Rename a bus (from the illegible long sequence of signal names, to the name
1925046      DBG_SIMVISION   Simvision save command script issue
1950037      DBG_SIMVISION   The optimized signals in SimVision show up as optimized in the translated VCD making it useless for power estimation.
2052000      DBG_SIMVISION   Opening UVM sequence viewer makes simvision " unstable"
2055527      DBG_SIMVISION   Schematic zoom bugs
2072830      DBG_SIMVISION   simvision might be unstable after a given number of mouse shortcuts for zoom in/out
2076430      DBG_SIMVISION   Unable to load expression calculator signals from a file in Simvision
2081028      DBG_SIMVISION   Xcelium generates VCD that cannot be read into Innovus
2114926      DBG_SIMVISION   simvisdbutil translates SST2 optimized signals activity into unreadable format
2123492      DBG_SIMVISION   Request to add "Waveform window" as an option to the "Send to new" item in the source window context menu
2143218      DBG_SIMVISION   Simvision save command script issue with renaming bus
1971970      FUNC_SAFETY     FS_FAULT_HIERACHY_TO/FROM shouldn't do a GLOBAL seach on the from string
1987444      FUNC_SAFETY     xfr summary is different between 10 and 2 splits.
1987751      FUNC_SAFETY     Concurrent generate different annotation results if different number of faults are injected
2013656      FUNC_SAFETY     Design extraction hangs
2025890      FUNC_SAFETY     strobe_event in strobe list is not mapped to a correct Tcl implementation when there is no FS_STROBE_DEFAULT_EVENT
2027158      FUNC_SAFETY     DCAN test Internal Exception during fault injection with forced signals
2031508      FUNC_SAFETY     support -single_value in strobe_event ( strobe list AND FS_STROBE_DEFAULT_EVENT)
2036480      FUNC_SAFETY     There are some differences between the result of serial and concurrent.
2054357      FUNC_SAFETY     Different detection status between concurrent and serial
2054687      FUNC_SAFETY     misleading warning message due usage of fault_test option
2058615      FUNC_SAFETY     -fault_hier_iso option does not support on XFS and X490
2059231      FUNC_SAFETY     Xcelium elaboration Internal Exception error when running with -FAULT_XML_GEN and related arguments
2062819      FUNC_SAFETY     SEU not instrumented due to hierachy inside of the sequential cell
2064310      FUNC_SAFETY     a sa1 fault is labeled as sa0 after level-0 fault reduction
2072950      FUNC_SAFETY     Wrong annotation if fault is potentially detected and FO/CO strobes point to the same pin/vector
2076621      FUNC_SAFETY     MESSAGE: spath_bestpath() - bad parameter
2077052      FUNC_SAFETY     Different Detection Serial vs Concurrent on ARM test-case
2078633      FUNC_SAFETY     MESSAGE: sv_seghandler - trapno -1 addr(0xfffffffffffffffc)
2083318      FUNC_SAFETY     Internal Error with "-setenv CDN_FAULT_ANALYZE_CONC=1"
2094473      FUNC_SAFETY     Huge memory usage with this testcase
2095578      FUNC_SAFETY     Detection results different with XFS concurrent versus serial in 1905e226
2098296      FUNC_SAFETY     Fault detection difference between concurrent and serial 1905e261
2103622      FUNC_SAFETY     CLONE Wrong annotation if fault is potentially detected and FO/CO strobes point to the same pin/vector
2108825      FUNC_SAFETY     Ignoring System Task in concurrent simulation
2109268      FUNC_SAFETY     MESSAGE: spath_bestpath() - bad parameter
2130203      FUNC_SAFETY     XFS has partially backward propagation
1813313      INDAGO          [Indago] : UVM hierarchy not available with parametrized classes.
1926254      INDAGO          Waveform not visible for probed signals in interactive mode
1948919      INDAGO          Demote STRPIN Could not initialize SimVision connection: can't register with service manager
2031650      INDAGO          LWD created in unexpected location
2044858      INDAGO          Could not trace the driver over the interface with lwdgen
2050698      INDAGO          Restarting from saved process based snapshot causes internal error - SimVision GUI
2056075      INDAGO          SimVision caught in loop when doing Driver Tracing
2000859      MULTI_CORE      xmelab Internal Exception error with -xufe: extra first bracket pair around "binsof" of ignore_bins
2007331      MULTI_CORE      using -xufe causes global datatype to be hidden by local variable due to parsing
2044528      MULTI_CORE      xufe flow Internal Exception error in elaboration
2058840      MULTI_CORE      AVSREQ-62535 XUFE internal error while creating a config
2090812      MULTI_CORE      xmelab: *E,XUFEE: %/path/c_checker_counts.sv%278%loop generate construct%at /dv/p4Cusers01nd/dvcmin_noida_agile_rc_xceli
2106794      MULTI_CORE      Assertions written in ske.sv file seems to miss the parentheses - causing the wrong assertion intent and test failure
1317154      PERSPEC         SVR generation issue, not following constraints
1469670      PERSPEC         composer internal exception error during save a test.sln scenario
1672944      PERSPEC         [DEGRADATION] test table reload mechanism is broken, used to work in previous versions
1742037      PERSPEC         Code Gen: Different results for same test (same seed)
1848889      PERSPEC         Solver/constraints: "constraint default" does not accept max-uint value
1858422      PERSPEC         Solver: add a user accessible phase / hook such as "end of scenario expansion"
1866383      PERSPEC         perspec should avoid to assign testbench SLAVE treads to actions with tokens
1916690      PERSPEC         get_active_executable() should return a note/warning if used in pre_gen_code() hook
1969444      PERSPEC         document the new ipc memory allocation behavior
1976905      PERSPEC         gen flow with -top_action switch generates incorrect code while composer / standard gen flow work correctly
2025402      PERSPEC         SML: Incorrect value displayed in read_check_data error message
2026043      PERSPEC         True_sharing_multi_copy_chain test failure due to patch: "patch_perspec_default_mem_block_assignment"
2031825      PERSPEC         Language: Fix fill and random_schedule operators (for repeated or sequential fill with random scheduling)
2036679      PERSPEC         Code Gen: generated C file show "Top Action: N/A" in their header (instead of N/A should be the top action)
2037768      PERSPEC         local initialization of perspec_batch when using set_global_ptr()
2037918      PERSPEC         Code Gen: perspec_batch initialization missing (sln_init_mailbox() generated empty and not called in code)
2060229      PERSPEC         Support exec file exec blocks for compound actions
2070375      PERSPEC         clarification of use-model for me->comp_handle in the RM, chapter "4.5.1. Exported fields"
2071155      PERSPEC         fix the example in UG 3.1.5.6.1.1. Setting the starting address of perspec_batch
2096809      PERSPEC         Call back error encountered in newer version
2105337      PERSPEC         libexpat.so.0 required for create_image but not found under Centos/RH 7
2114585      PERSPEC         in-line ASM code for atomic_base_operation missing "cc" and "memory" clobber
2126742      PERSPEC         Composer does not save false_sharing_random_operator scenario correctly
2128437      PERSPEC         Native CSV utility does not support empty tables
2129766      PERSPEC         Code Gen: duplicate declaration of same field, when runtime attribute is defined in token of memory[*]
2129815      PERSPEC         EL0 in cdn_exception_level_cov.to_el/from_EL always show 100% coverage
2136202      PERSPEC         Native CSV utility does not treat size_const as a const while parsing SLN
1457707      SPECMAN         please add a hook method that is called whenever any coverage group is being collected.
1516357      SPECMAN         coverage grade : lower than actually is (on ungradeable item with a few buckets not ignored)
1584192      SPECMAN         specman debug current execution points incorrect line number for check true-block
1585966      SPECMAN         provide option to use use set_check_by_name() on error emitted for illegal coverage values
1686377      SPECMAN         Specview window affects zombies
1692552      SPECMAN         irun error - SNNOLS with elibs and snstage
1698582      SPECMAN         Memory consumption of UCM creation should be optimized
1803711      SPECMAN         Simple port methods should be supported also in any_simple_port
1882762      SPECMAN         add a warning when allocation request is greater than Optimal Process Size before the actual allocation
1909931      SPECMAN         VHPI internal error - ssl_set_time_snare failed.
1934614      SPECMAN         Request for an interface that supports struct conversion from E to C and vice versa similar to FLI
1939185      SPECMAN         False contradiction at transaction generation after a long testrun
2029679      SPECMAN         Missing implementation for 'external_scalar_ref_param.eval4get_ref()
2032029      SPECMAN         bool(bits:1) forces improper compiler exit
2040041      SPECMAN         Specman is unable to recognize runtime errors in initialization file reader read_ini.sh
2043037      SPECMAN         improve VPI NEGTIME error message to point source code line number
2045144      SPECMAN         e linting rule EARBSC has unexpected fails
2065593      SPECMAN         Usage of Template <type> Parameter in as_a() Cast Operation
2067952      SPECMAN         WARN_METHOD_DEFINED errors emitted at buffer_port definition
2072817      SPECMAN         incorrect error source ref. in a mixed compiled and interpreted env.
2091832      SPECMAN         using a macro inside gen
2097753      SPECMAN         Specman segmentation fault when Indago launches
2102924      SPECMAN         Error during coverage analysis at finalize_test()
2102944      SPECMAN         HAL internal error at E_GENERATION checks
2104817      SPECMAN         Specman function has_mvl_value(MVL_0) returns erroneous value
2118103      SPECMAN         Specman tool failure using 'trace change -wave' on longuint
2118175      SPECMAN         Issue in UVM SB matching algorithm
2118206      SPECMAN         UVM score board use model without ports need to be enhanced
2119176      SPECMAN         Generation error using elib with str_replace()
2122834      SPECMAN         Internal Specman error at 'do sequence' using 'trace -wave'
2122935      SPECMAN         Coverage related activities not disabled when mode is off
2124242      SPECMAN         19.03 OS Signal 11 when running with probing in GUI mode
2135946      SPECMAN         Symbol `esi_simple_has_mvl' not found in the program object
2138223      SPECMAN         wrong gen action executed without any error or warning
2152418      SPECMAN         FLI glue code compilation error on non-physical struct field
1654267      UVM             The UVM_ERROR messages for assertion errors while using  cdns_assert2uvm_pkg does not contain name
2045012      UVM             uvm_hdl_deposit performance issue
1501167      XRUN            ARMFM: SystemCExport - missing symbols - due to ignored static lib
1962395      XRUN            snrebuild not working as expected
2016825      XRUN            xrun with -fast_recompilation does not properly consider SV package dependencies
2045799      XRUN            xrun does not bring in import symbols from archives
2047387      XRUN            tmp/ncsim.args files are corrupted if multiple runs are in parallel
2057491      XRUN            AMSD: When setting XLM_ERRORLOG env var, not able to read spectre version when using "spectre_args" switch
2060315      XRUN            xrun -elabonly deletes librun.so if C source changes without modifying C files list
2063970      XRUN            *E,DLCSMD: Dependent checksum error at xrun rerun after modifyiing a SV header file in UVM-ML env
2069346      XRUN            Document the support for -setenv in xrun options
2071533      XRUN            XRUN option "-setenv" not documented
2086018      XRUN            Add support to use the existing xmsim_sym instead of rebuilding with -rebuild
2094002      XRUN            segmentation fault hits Internal Exception when simulation loading snapshot at sim 0 time
2110716      XRUN            Files recompilation issue, without any file change, with -fast_recompilation option
2110856      XRUN            Unexpected signal 11 in compilation using xrun
2132021      XRUN            TWOWRN warning unnecessary
2145910      XRUN            Changing snapshot with -primname  doesnot re-elaborate already build incremental snapshot
2158534      XRUN            Option -enable_single_yvlib option not working in performance release

INDAGO-94    INDAGO  CCMPR01948665  CCR Message 'The LWD is not compatible with this version of Indago' when launching Indago from Simvision GUI
INDAGO-133   INDAGO  Change Indago's default font
INDAGO-26201 INDAGO  Improve the way that the design hierarchy is initially opened
INDAGO-25283 INDAGO  Waveform radix change is not applied to waveform preview
INDAGO-27001 INDAGO  testing JIRA notification : PLEASE IGNORE
INDAGO-204   INDAGO  CCMPR01661625  CCR Error message when opening Indago.
INDAGO-37    INDAGO  CCMPR01634891  CCR Double-clicking on a signal in a maximized window does not automatically open the Source Browser
INDAGO-26295 INDAGO  ctrl+w doesn't work from the exploration window but works from the right-click menu
INDAGO-26523 INDAGO  Memory consumption in interactive debug - without touching the application, memory consumption can growing very fast
INDAGO-72    INDAGO  CCMPR01746550  Unexplained blue-to-grey transition in new Indago waveforms
INDAGO-25892 INDAGO  Disable the database reload option in Indago's pxp flow
INDAGO-100   INDAGO  CCMPR01571842  clicking on an entry in the Calls stack makes it lose the rest of the stack
INDAGO-153   INDAGO  CCMPR01751341 - the ida_database command complains about missing path (in 15.20) but also creates it
INDAGO-26462 INDAGO  Investigate - Improve .wsf file load time
INDAGO-27137 INDAGO  Opening only the smartlog in a LP environment doesn't show the power browser
INDAGO-339   INDAGO  No value for bus signal with Indago Phase2
INDAGO-26834 INDAGO  DT not working properly in Indago-Palladium flow
INDAGO-25933 INDAGO  Make the tops/source sync configurable ... and not under env variable
INDAGO-26538 INDAGO  Investigate - when loading wsf files in Indago, Indago steals the X focus of each loaded signal
INDAGO-342   INDAGO  CCMPR01751485  CCR error while launching Indago: DB 'newname.db' is not a valid Indago app database
INDAGO-26246 INDAGO  Allow users who don't have write permission to the phy dir to launch Indago
INDAGO-151   INDAGO  CCMPR01693110  CCR Long timestamps are shown incorrectly when recorded in timescale other than fs
INDAGO-22746 INDAGO  CCMPR01920127  When zoomed out while comparing 2 signals, v18.01 displays green markers while v18.04 displays no markers at all
INDAGO-26871 INDAGO  Bus splitting inside a group in the Waveform Viewer is not restored with save-reload
INDAGO-207   INDAGO  CCMPR01634883  CCR In Indago's Source Viewer, some icons are hidden during driver tracing
INDAGO-223   INDAGO  CCMPR01756103  ida_probe -wave -wave_probe_args command errors
INDAGO-26515 INDAGO  Need a GUI method to shift selected signal(s) by some amount of time
INDAGO-26296 INDAGO  The Smartlog filter by tag drop down menu is not ordered alphabetically
INDAGO-24922 INDAGO  Signal shows as probed for entire window while it was probed in multiple dump windows
INDAGO-209   INDAGO  CCMPR01634871  CCR Source Window missing a horizontal scrollbar
INDAGO-1703  INDAGO  Cleanup - find control (source and tables)
INDAGO-25922 INDAGO  1806013  CCR "Break at line if..." is not working for C code. Behaving same way as "Break at line"
INDAGO-25252 INDAGO  When an index is n/a, show the full value of array that is indexed
INDAGO-25043 INDAGO  the shm generated by a parallel SHM flow is not the same as one created in non-parallel mode
INDAGO-22868 INDAGO  Investigate - insertion point indicator is sluggish when the mouse moves
INDAGO-26202 INDAGO  Some user settings are not saved across Indago sessions
INDAGO-301   INDAGO  The search tool does not show the 'log' result tab in interactive sessions
INDAGO-25932 INDAGO  Double clicking between table columns should adjust the width to show all of the content of the column
INDAGO-27140 INDAGO  Need a way to configure the number of messages saved in console history
INDAGO-26469 INDAGO  xmsim crash with message: vst_name() - invalid class when ida_probe -log enabled
INDAGO-251   INDAGO  Need an API to record source mapping (source and target)
INDAGO-29    INDAGO  User should be able to copy the UVM hierarchy path from the Tops Tree
INDAGO-274   INDAGO  Unable to see where xmsim runtime warnings originate from in Indago flow recording
INDAGO-26527 INDAGO  Investigation - cannot bring the trace calculator to the front after clicking on Indago
INDAGO-22641 INDAGO  Cannot drag and drop groups - degradation
INDAGO-22584 INDAGO  Request a tcl API that calculates average, min, and max values on select signals
INDAGO-27436 INDAGO  There is no indication to the user when the DISPLAY is not set correctly
INDAGO-116   INDAGO  CCMPR02047380  Need access to Tops window in latest Indago ESWD with new waveforms
INDAGO-12    INDAGO  Cannot open ida.db if path contains dir names with '.' and ':'
INDAGO-27383 INDAGO  Virtual Liberty text references are missing