OC

module booth_modificat
#( parameter OPERAND_BITS = 8,
parameter RESULT_BITS = 16)
(

input clk,
input rst,
input [OPERAND_BITS - 1 : 0] a,
input [OPERAND_BITS - 1 : 0] b,
input start,
output[RESULT_BITS - 1 : 0] result,
output reg ovr
);

reg f;
reg [OPERAND_BITS-1 : 0] A;
reg [OPERAND_BITS : 0] Q;
reg Q_1;
reg [OPERAND_BITS-1 : 0] M;
reg [2:0] count;

reg [3:0] state;

localparam [3:0] s0=4'd0, s1=4'd1, s2=4'd2, s3=4'd3, s4=4'd4, s5=4'd5, s6=4'd6, s7=4'd7, s8=4'd8, s9=4'd9;

// sequential process

always
@(posedge clk, posedge rst)

begin

if (rst)

begin

state <= s0;
A <= 0;
Q <= 0;
M <= 0;
Q_1 <= 0;
count <= 0;

end

else

begin
   case(state)
       s0: begin
            if(start)
              state <= s1;
          end
       s1:
          begin
              A <= 0;
              count <= 0;
              f <= 0;
              ovr <= 0;
              M <= a;
              Q <= b[7:0];
              Q_1 <= b[0];
              state <= s2;
          end
       s2:
          begin
              if(Q == 9'd0)
                state <= s9;
              else if(M == 8'd0)
                state <= s3;
              else
                state <= s4;
          end
       s3:
          begin
              Q <= 0;
              Q_1 <= 0;
              state <= s9;
          end
       s4:
          begin
              if(f == 1'b0)
               begin
                 if(Q[7] == 1'b1)
                    if(Q[6] == 1'b0)
                    begin
                        A <= A + M;
                        ovr <= 1'b1;
                    end
                    else
                    begin
                        A <= A - M;
                        ovr <= 1'b1;
                        f <= 1'b1;
                    end
               end
               else
               begin
                   if(Q[7] == 1'b1)
                      if(Q[6] == 1'b0)
                      begin
                          A <= A + M;
                          ovr <= 1'b1;
                          f <= 1'b0;
                      end
                      else
                      begin
                          A <= A - M;
                          ovr <= 1'b1;
                      end
               end
               if(count == 2'd7)
                  state <= s9;
               else
                  state <= s8;
          end
       s8:
          begin
              A[7] <= (A[0] && M[0] && ovr) || (f && M[0]) || (f && M[0] && ovr);
              {A[7:1], Q} <= {A, Q[6:0], Q_1};
              count <= count + 1'b1;
              state <= s4;
          end
       s9:
          begin
             Q[6] <= 0;
          end
   endcase
// do something

end
end

assign result = {A, Q[6:0], Q_1};

endmodule




//TB

module booth_modificat_tb

#( parameter OPERAND_BITS = 8,
parameter RESULT_BITS = 16)

(
output reg clk,
output reg rst,
output reg start,

output reg [OPERAND_BITS - 1 : 0] a,
output reg [OPERAND_BITS - 1 : 0] b,

output [RESULT_BITS - 1 : 0] result,
output ovr
);

booth_modificat b1(
   .clk(clk),
   .rst(rst),
   .start(start),
   .a(a),
   .b(b),
   .result(result),
   .ovr(ovr)
);

initial begin
      clk = 0;
      repeat (30) #50 clk = ~clk;
end

initial begin
   a = 8'd2;
   b = 8'd3;
end

initial begin
   start = 1'b0;
   #50 start = 1'b1;
end

initial begin
    rst = 1'b0;
    #50 rst = 1'b1;
    #100 rst = 1'b0;
end

endmodule



module vga_intf
#(
parameter hRez = 640,
parameter vRez = 480,
parameter hFP = 16,
parameter hSyP = 96,
parameter hBP = 48,
parameter vFP = 10,
parameter vSyP = 2,
parameter vBP = 33
)
(
   input clk50M,
   input rst,
   //input[9:0] rIn, bIn, gIn,
   output[9:0] vga_r, vga_b, vga_g, //xPos, yPos,
   output reg hSync, vSync,
   output blank, //might need to be inversed, to check
   output clkO
);
reg valid;
reg[9:0] hCnt, vCnt, hSyncCnt;
reg[19:0] vSyncCnt;
wire[9:0] red, green, blue;
parameter vSyT = hRez + hFP + hSyP + hBP;
reg clk25M;
reg clkCnt;

`ifdef debug
colour_select cs(
   .clk(clk25M),
   .valid(valid),
   .vCnt(vCnt),
   .hCnt(hCnt),
   .red(red),
   .green(green),
   .blue(blue)
);
assign vga_r = red;
assign vga_g = green;
assign vga_b = blue;
`else
assign vga_r = rIn;
assign vga_b = bIn;
assign vga_g = gIn;
`endif
assign blank = valid;
assign xPos = (hCnt < hRez) ? (hCnt) : (hRez - 1);
assign yPos = (vCnt < vRez) ? (vCnt) : (vRez - 1);
assign clkO = clk25M;
always @ (posedge clk50M) begin
    if(rst)
        clkCnt <= 0;
    else begin
        clkCnt <= clkCnt + 1'd1;
        if(clkCnt == 1'd1)
            clk25M = clk25M + 1'd1;
    end
end
always @ (posedge clk25M) begin
    if(rst) begin
        hCnt <= 0;
        vCnt <= 0;
        hSync <= 1'd1;
        vSync <= 1'd1;
        hSyncCnt <= 0;
        vSyncCnt <= 0;
        valid <= 0;
    end
    else begin
        if(hCnt == 0 && vCnt != (vRez)) valid <= 1'd1;
        if(hCnt < (hRez-1)) hCnt <= hCnt + 1'd1;
        if(hCnt >= (hRez-1)) begin
        if(hSyncCnt == 0) valid <= 0;
            if(hSyncCnt < (hFP-1) && (hCnt >= (hRez-1))) hSyncCnt <= hSyncCnt + 1'd1;
            else begin
                if(hSyncCnt == (hFP)) hSync <= 0;
                if(hSyncCnt < (hFP + hSyP)) hSyncCnt <= hSyncCnt +1'd1;
                else begin
                    if(hSyncCnt == (hFP + hSyP)) hSync <= 1'd1;
                    if(hSyncCnt < (hFP + hSyP + hBP)) hSyncCnt <= hSyncCnt + 1'd1;
                    else begin
                        if(hSyncCnt == (hFP + hSyP + hBP)) begin
                            if(vCnt < (vRez)) begin
                                hCnt <= 0;
                                vCnt <= vCnt +1'd1;
                                hSyncCnt <= 0;
                                if(vCnt != (vRez-1)) valid <= 1'd1;
                            end
                            else begin
                                hSyncCnt <= 0;
                                hCnt <= 0;
                            end
                        end
                   end
                end
            end
        end
        if(vCnt == (vRez)) begin
            valid <= 0;
            if(vSyncCnt < (vFP*vSyT)-1)   vSyncCnt <= vSyncCnt + 1'd1;
            else begin
                if(vSyncCnt == (vFP*vSyT)-1)   vSync <= 0;
                if(vSyncCnt < ((vFP + vSyP)*vSyT)-1) vSyncCnt <= vSyncCnt + 1'd1;
                else begin
                    if(vSyncCnt == ((vFP + vSyP)*vSyT)-1) vSync <= 1'd1;
                    if(vSyncCnt < ((vFP + vSyP + vBP)*vSyT)-1)   vSyncCnt <= vSyncCnt + 1'd1;
                    else begin
                        vSyncCnt <= 0;
                        vCnt <= 0;
                        valid <= 1'd1;
                        hCnt <= 0;
                        hSyncCnt <= 0;
                    end
                end
            end
        end
    end
end
endmodule



module vga_tb ();

reg clk50M, rst;
wire[9:0] vga_g, vga_r, vga_b, xPos, yPos, rIn, bIn, gIn;
wire hSync, vSync;
wire blank;

integer i;

vga_intf
/*#(
.hRez(2),
.vRez(3),
.hFP(3),
.hSyP(3),
.hBP(5),
.vFP(2),
.vSyP(4),
.vBP(6)
)*/
test(
   .clk50M(clk50M),
   .rst(rst),
   .hSync(hSync),
   .vSync(vSync),
   .vga_r(vga_r),
   .vga_b(vga_b),
   .vga_g(vga_g),
   .blank(blank),
   .xPos(xPos),
   .yPos(yPos),
   .rIn(rIn),
   .bIn(bIn),
   .gIn(gIn)
   );

initial begin
    rst = 1'd1;
    #100 rst = 1'd0;
end

initial begin
    clk50M = 1'd0;
    for (i=0; i<800*600*10; i=i+1) begin
       #10 clk50M = 1'd1;
       #10 clk50M = 1'd0;
    end
end

endmodule



module colour_select(
   input clk,
   input valid,
   input[9:0] vCnt, hCnt,
   output reg[9:0] red, green, blue
);

parameter hRez = 800;
parameter vRez = 600;
parameter cHalf = 700;
parameter cSize = 1023;

always @ (negedge clk) begin
    if(valid) begin
        if((vCnt + hCnt) < cHalf) begin
            red <= cSize - (vCnt + hCnt) * cSize / cHalf;
            blue <= 0;
            green <= (vCnt + hCnt) * cSize / cHalf;
        end
        else begin
            red <= 0;
            green <= cSize - (vCnt + hCnt - cHalf) * cSize / cHalf;
            blue <= (vCnt + hCnt - cHalf) * cSize / cHalf;
        end
    end
end
endmodule


module divider(

   input clk,
   input rst,
   input [7:0] inA,
   input [7:0] inB,
   output [7:0] rem,
   output [7:0] quot

);

reg [1:0] q;
reg [7:0] A;
reg [7:0] B;
reg [8:0] P;
reg [2:0] k;
reg [3:0] cnt;

reg[3:0] state,state_nxt;
localparam s0=3'd0, s1=3'd1,s2=3'd2,s3=3'd3;

always @(posedge clk or posedge rst)
begin
    if (rst) begin
      state <= s0;
      A <= inA;
      B <= inB;
      q <= 1'b0;
      k <= 3'b0;
      P <= 5'b0;
      cnt <= 4'd0;
      q <= 2'd0;
   end
   else begin
      case(state)
        s0:
           if(B[7] == 1'd0)
              begin
                  {B,P,A} <= {B[6:0], 1'b0, P[7:0], A[7], A[6:0], 1'b0};
                  k <= k + 1'b1;
                  state <= s0;
              end
           else
              state <= s1;
        s1:
        if(cnt < 8 || q != 0)
           begin
             if(q == 0) begin
                if(P[8:6] == 0 || P[8:6] == 7) begin
                   P[8:0] <= {P[7:0], A[7]};
                   A <= {A[6:0], 1'b0};
                end
                else if(P[8] == 1) begin
                   P[8:0] <= {P[7:0], A[7]};
                   A <= {A[6:0], 1'b0};
                   q <= 2'b01;
                end
                else begin
                   P[8:0] <= {P[7:0], A[7]};
                   A <= {A[6:0], 1'b0};
                   q <= 2'b10;
                end
                cnt <= cnt + 1;
             end
             else begin
                if(q == 1) begin
                   A <= A - 1'd1;
                   P <= P + B;
                   q <= 2'b00;
                end
                else begin
                   A <= A + 1'd1;
                   P <= P - B;
                   q <= 2'b00;
                end
             end
           end
       else state <= s2;
       s2:
          if(P[8] == 1'b1) begin
             P <= P + B;
             A <= A - 1'b1;
          end
          else begin
             if(k > 0) begin
                P <= P >> k;
             end
             state <= s3;
          end
      endcase
   end
end

assign quot = A;
assign rem = P[7:0];

endmodule




module divider_tb(

   output reg clk,
   output reg rst,
   output reg [7:0] inA,
   output reg [7:0] inB,
   output [7:0] rem,
   output [7:0] quot

);

divider d1(
   .clk(clk),
   .rst(rst),
   .inA(inA),
   .inB(inB),
   .rem(rem),
   .quot(quot)

);

initial begin
      clk = 0;
      repeat (100) #50 clk = ~clk;
end

initial begin
   inA = 15;
   inB = 2;
end

initial begin
    rst = 1'b0;
    #50 rst = 1'b1;
    #100 rst = 1'b0;
end

endmodule