module morse(SW, KEY, LEDR, CLOCK_50);
    input[2:0] SW;
    input [1:0] KEY;
    input CLOCK_50;
    output [0:0] LEDR;

    morsecoder m0(
        .letters(SW[2:0]),
        .start(KEY[1]),
        .reset_n(KEY[0]),
        .out(LEDR[0]),
        .clock(CLOCK_50)
    );
endmodule

module morsecoder(letters, start, reset_n, out, clock);
    input [2:0] letters;
    input start, reset_n, clock;
    output out;

    wire[13:0] w_morsecodebinary;
    wire[24:0] w_rdivider;
    wire enable_r0;

    LUT l0(
        .letter(letters),
        .morsec_binary(w_morsecodebinary)
    );

    ratedivider rd0(
        .d(25'd24_999_999),
        .clock(clock),
        .reset_n(reset_n),
        .q(w_rdivider)
    );

    assign enable_r0 = (w_rdivider == 0)? 1: 0;

    register r0(
        .load_val(w_morsecodebinary),
        .load_n(start),
        .clock(clock),
        .reset_n(reset_n),
        .enable(enable_r0), // from rate divider
        .out(out)
    );


endmodule

module LUT(letter, morsec_binary);
    input [2:0] letter;
    output reg [13:0] morsec_binary;

    always @(*)
    begin
        case(letter)
        3'b000: morsec_binary = {6'b101010, 8'd0}; //binary for S
        3'b001: morsec_binary = {4'b1110, 10'd0}; // binary for T
        3'b010: morsec_binary = {8'b10101110, 6'd0}; // binary for U
        3'b011: morsec_binary = {10'b1010101110,4'd0}; // binary for V
        3'b100: morsec_binary = {10'b1011101110, 4'd0}; // binary for W
        3'b101: morsec_binary = {12'b111010101110,2'd0}; // binary for X
        3'b110: morsec_binary = 14'b11101011101110 // binary for Y
        3'b111: morsec_binary = {12'111011101010,2'd0} // binary for Z
    end
endmodule

module register(load_val, load_n, reset_n, clock, out, enable);
    input [13:0] load_val;
    input load_n, clock, reset_n, enable; // reset_n key 0 asynchrnous reset . load_n = key 1 start displaying morse code
    output reg out;
    reg [13:0] morsec;

    always @ (posedge clock, negedge reset_n)
    begin
        if(reset_n == 1'b0)
        begin
            load_n <= 1'b0;
            out <= 1'b0;
            morsec <= 14'd0;
        end
        else if (load_n == 1'b0)
        begin
           out <= 1'b0;
           morsec <= load_val;
        end
        else if (enable == 1'b1)
        begin
            out <= morsec[13];
            morsec <= morsec << 1'b1;
        end
    end

endmodule


module ratedivider(d, clock, reset_n, q);
    input [24:0] d; // because 2^25 equal to 33 million which is more than enough for 25 million
    input clock, reset_n;
    output reg [24:0] q;

    always @(posedge clock, negedge reset_n)
    begin
        if(reset_n == 1'b0)
            q <= d;
        else if(q == 1'b0)
            q <= d
        else
            q<= q - 1'b1;
    end