Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:36:48 2020
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:36:48 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led_twinkle -c led_twinkle
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file led_twinkle.v
	Info (12023): Found entity 1: led_twinkle
	Info (12023): Found entity 1: led_twinkle
Info (12127): Elaborating entity "led_twinkle" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at led_twinkle.v(24): truncated value with size 32 to match size of target (25)
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
	Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
	Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 52 device resources after synthesis - the final resource count might be different
	Info (21058): Implemented 1 input pins
	Info (21059): Implemented 4 output pins
	Info (21061): Implemented 47 logic cells
	Info (21058): Implemented 1 input pins
	Info (21059): Implemented 4 output pins
	Info (21061): Implemented 47 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
	Info: Peak virtual memory: 4779 megabytes
	Info: Processing ended: Sun May 17 19:36:59 2020
	Info: Elapsed time: 00:00:11
	Info: Total CPU time (on all processors): 00:00:25
	Info: Peak virtual memory: 4779 megabytes
	Info: Processing ended: Sun May 17 19:36:59 2020
	Info: Elapsed time: 00:00:11
	Info: Total CPU time (on all processors): 00:00:25
Info: *******************************************************************
Info: Running Quartus Prime Fitter
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:37:00 2020
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:37:00 2020
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led_twinkle -c led_twinkle
Info: qfit2_default_script.tcl version: #1
Info: Project  = led_twinkle
Info: Revision = led_twinkle
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (119006): Selected device EP4CE6E22C8 for design "led_twinkle"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
	Info (176445): Device EP4CE10E22C8 is compatible
	Info (176445): Device EP4CE15E22C8 is compatible
	Info (176445): Device EP4CE22E22C8 is compatible
	Info (176445): Device EP4CE10E22C8 is compatible
	Info (176445): Device EP4CE15E22C8 is compatible
	Info (176445): Device EP4CE22E22C8 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
	Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
	Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
	Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
	Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
	Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101
	Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
	Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
	Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
	Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
	Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (332012): Synopsys Design Constraints File file not found: 'led_twinkle.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (176353): Automatically promoted node clk~input (placed in PIN 23 (CLK1, DIFFCLK_0n))
	Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
	Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info (176233): Starting register packing
Info (176235): Finished register packing
	Extra Info (176219): No registers were packed into other blocks
	Extra Info (176219): No registers were packed into other blocks
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
	Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y11
	Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y11
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
	Info (170201): Optimizations that may affect the design's routability were skipped
	Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.14 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
Warning (169177): 1 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
	Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at 23
	Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at 23
Info (144001): Generated suppressed messages file D:/FPGA_HDL/projects/quartus/led_twinkle/led_twinkle.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings
	Info: Peak virtual memory: 5625 megabytes
	Info: Processing ended: Sun May 17 19:37:07 2020
	Info: Elapsed time: 00:00:07
	Info: Total CPU time (on all processors): 00:00:06
	Info: Peak virtual memory: 5625 megabytes
	Info: Processing ended: Sun May 17 19:37:07 2020
	Info: Elapsed time: 00:00:07
	Info: Total CPU time (on all processors): 00:00:06
Info: *******************************************************************
Info: Running Quartus Prime Assembler
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:37:09 2020
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:37:09 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off led_twinkle -c led_twinkle
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
	Info: Peak virtual memory: 4683 megabytes
	Info: Processing ended: Sun May 17 19:37:10 2020
	Info: Elapsed time: 00:00:01
	Info: Total CPU time (on all processors): 00:00:01
	Info: Peak virtual memory: 4683 megabytes
	Info: Processing ended: Sun May 17 19:37:10 2020
	Info: Elapsed time: 00:00:01
	Info: Total CPU time (on all processors): 00:00:01
Info (293026): Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:37:11 2020
	Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
	Info: Processing started: Sun May 17 19:37:11 2020
Info: Command: quartus_sta led_twinkle -c led_twinkle
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'led_twinkle.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
	Info (332105): create_clock -period 1.000 -name clk clk
	Info (332105): create_clock -period 1.000 -name clk clk
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -3.286
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.286             -59.760 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.286             -59.760 clk
Info (332146): Worst-case hold slack is 0.453
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):     0.453               0.000 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):     0.453               0.000 clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.000             -41.662 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.000             -41.662 clk
Warning (18330): Ignoring Synchronizer Identification setting Off, and using Auto instead.
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -2.899
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -2.899             -53.721 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -2.899             -53.721 clk
Info (332146): Worst-case hold slack is 0.402
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):     0.402               0.000 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):     0.402               0.000 clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.000             -41.662 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.000             -41.662 clk
Warning (18330): Ignoring Synchronizer Identification setting Off, and using Auto instead.
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -0.894
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -0.894             -11.686 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -0.894             -11.686 clk
Info (332146): Worst-case hold slack is 0.187
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):     0.187               0.000 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):     0.187               0.000 clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.000             -36.730 clk
	Info (332119):     Slack       End Point TNS Clock
	Info (332119): ========= =================== =====================
	Info (332119):    -3.000             -36.730 clk
Warning (18330): Ignoring Synchronizer Identification setting Off, and using Auto instead.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 8 warnings
	Info: Peak virtual memory: 4777 megabytes
	Info: Processing ended: Sun May 17 19:37:14 2020
	Info: Elapsed time: 00:00:03
	Info: Total CPU time (on all processors): 00:00:02
	Info: Peak virtual memory: 4777 megabytes
	Info: Processing ended: Sun May 17 19:37:14 2020
	Info: Elapsed time: 00:00:03
	Info: Total CPU time (on all processors): 00:00:02
Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 16 warnings