audio2

module audio2(
  // Clock Input (50 MHz)
  input CLOCK_50, // 50 MHz
  input CLOCK_27, // 27 MHz
  //  Push Buttons
  input  [3:0]  KEY,
  //  DPDT Switches
  input  [17:0]  SW,
  //  7-SEG Displays
  output  [6:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
  //  LEDs
  output  [8:0]  LEDG,  //  LED Green[8:0]
  output  [17:0]  LEDR, //  LED Red[17:0]
  // TV Decoder
  output TD_RESET, // TV Decoder Reset
  // I2C
  inout  I2C_SDAT, // I2C Data
  output I2C_SCLK, // I2C Clock
  // Audio CODEC
  output/*inout*/ AUD_ADCLRCK, // Audio CODEC ADC LR Clock
  input  AUD_ADCDAT,  // Audio CODEC ADC Data
  output /*inout*/  AUD_DACLRCK, // Audio CODEC DAC LR Clock
  output AUD_DACDAT,  // Audio CODEC DAC Data
  inout  AUD_BCLK,    // Audio CODEC Bit-Stream Clock
  output AUD_XCK,     // Audio CODEC Chip Clock
  //  GPIO Connections
  inout  [35:0]  GPIO_0, GPIO_1
);


//  All inout port turn to tri-state
assign  GPIO_0      =   36'hzzzzzzzzz;
assign  GPIO_1      =   36'hzzzzzzzzz;

wire [6:0] myclock;
wire RST;
assign RST = KEY[0];

// reset delay gives some time for peripherals to initialize
wire DLY_RST;
Reset_Delay r0( .iCLK(CLOCK_50),.oRESET(DLY_RST) );

// Send switches to red leds
assign LEDR = SW;

// Turn off green leds

// Turn off 7-segment displays
parameter BLANK = 7'h7f;
assign HEX0 = BLANK;
assign HEX1 = BLANK;
assign HEX2 = BLANK;
assign HEX3 = BLANK;
assign HEX4 = BLANK;
assign HEX5 = BLANK;
assign HEX6 = BLANK;
assign HEX7 = BLANK;


assign  TD_RESET = 1'b1;  // Enable 27 MHz


samples_RAM(
                .clock(CLOCK_50),
                .address(index),
                .wren(0),
                .q(signal)
);

VGA_Audio_PLL   p1 (
    .areset(~DLY_RST),
    .inclk0(CLOCK_27),
    .c0(VGA_CTRL_CLK),
    .c1(AUD_CTRL_CLK),
    .c2(VGA_CLK)
);

I2C_AV_Config u3(
//  Host Side
  .iCLK(CLOCK_50),
  .iRST_N(KEY[0]),
//  I2C Side
  .I2C_SCLK(I2C_SCLK),
  .I2C_SDAT(I2C_SDAT)
);

assign  AUD_ADCLRCK =   AUD_DACLRCK;
assign  AUD_XCK     =   AUD_CTRL_CLK;

audio_clock u4(
//  Audio Side
   .oAUD_BCK(AUD_BCLK),
   .oAUD_LRCK(AUD_DACLRCK),
//  Control Signals
  .iCLK_18_4(AUD_CTRL_CLK),
   .iRST_N(DLY_RST)
);

audio_converter u5(
    // Audio side
    .AUD_BCK(AUD_BCLK),       // Audio bit clock
    .AUD_LRCK(AUD_DACLRCK), // left-right clock
    .AUD_ADCDAT(AUD_ADCDAT),
    .AUD_DATA(AUD_DACDAT),
    // Controller side
    .iRST_N(DLY_RST),  // reset
    .AUD_outL(audio_outL),
    .AUD_outR(audio_outR),
    .AUD_inL(audio_inL),
    .AUD_inR(audio_inR)
);

wire [15:0] audio_inL, audio_inR;
wire [15:0] audio_outL, audio_outR;
wire [15:0] signal;

reg [31:0] index = 0;
wire snareB,hihatB,bassB;

oneshot k0(KEY[0], AUD_DACLRCK, snareB);
oneshot k1(KEY[1], AUD_DACLRCK, hihatB);
oneshot k2(KEY[2], AUD_DACLRCK, bassB);

wire [15:0] snareSignal,hihatSignal,bassSignal;
reg snareFlag,hihatFlag,bassFlag;

assign audio_outR = signal;
assign audio_outL = signal;

assign LEDG[0] = snareB;
assign LEDG[1] = snareE;
assign LEDG[2] = snareD;
assign LEDG[5:3] = state;

parameter def = 0, snare = 1, hihat = 2, bass = 3;
reg [3:0] state;
reg snareE,snareD,hihatE,hihatD,bassE,bassD;

initial begin
    state = def;
end

always @(negedge AUD_DACLRCK) begin
    if(snareB) begin
        state = snare;
    end
    else if(hihatB) begin
        state = hihat;
    end
    else if(bassB) begin
        state = bass;
    end

    case(state)
        snare:
        begin
            index <= 0;
            if(index < 4000-1) index <= index + 1'b1;
            else begin
                index<=0;
                state = def;
            end
        end
        hihat:
        begin
            index <= 4000;
            if(index < 8000-1) index <= index + 1'b1;
            else begin
                index<=4000;
                state = def;
            end
        end
        bass:
        begin
            index <= 8000;
            if(index < 12000-1) index <= index + 1'b1;
            else begin
                index<=8000;
                state = def;
            end
        end
    endcase
end

endmodule

module oneshot(sin, clock, sout);
    input sin, clock;
    output sout;
    reg sout, q;

    always @(posedge sin or posedge sout) begin
        if(sout)
            q <= 0;
        else
            q <= 1;
    end
    always @(posedge clock) begin
        sout <= q;
    end
endmodule