cuberoot_tb.v

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   18:04:24 10/26/2013
// Design Name:   CubeRoot
// Module Name:   C:/Users/Siddarth/Documents/Xilinx/CubeRoot/CubeRootTest.v
// Project Name:  CubeRoot
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: CubeRoot
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module CubeRootTest;

	// Inputs
	reg [63:0] Number;
	reg clk;

	// Outputs
	wire [21:0] Answer;
	wire [63:0] Remainder;
	wire [63:0] NumberLevel1;
	wire [63:0] NumberLevel2;
	wire [63:0] NumberLevel3;
	wire [63:0] NumberLevel4;
	wire [63:0] NumberLevel5;
	wire [63:0] NumberLevel6;
	wire [63:0] NumberLevel7;
	wire [63:0] NumberLevel8;
	wire [63:0] NumberLevel9;
	wire [63:0] NumberLevel10;


	// Instantiate the Unit Under Test (UUT)
	CubeRoot uut (
		.Number(Number),
		.clk(clk),
		.Answer(Answer),
		.Remainder(Remainder),
		.NumberLevel1(NumberLevel1),
		.NumberLevel2(NumberLevel2),
		.NumberLevel3(NumberLevel3),
		.NumberLevel4(NumberLevel4),
		.NumberLevel5(NumberLevel5),
		.NumberLevel6(NumberLevel6),
		.NumberLevel7(NumberLevel7),
		.NumberLevel8(NumberLevel8),
		.NumberLevel9(NumberLevel9),
		.NumberLevel10(NumberLevel10)
	);

	initial begin
		// Initialize Inputs
		Number = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;

		// Add stimulus here
		Number = 27;
		clk = 1;
		#10;
		clk = 0;
		#10;
		Number = 64;
		clk = 1;
		#10;
		clk = 0;
		#10;
		Number = 216;
		clk = 1;
		#10;
		clk = 0;
		#10;
		Number = 8;
		clk = 1;
		#10;
		clk = 0;
		#10;
		Number = 125;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;	clk = 1;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;
		clk = 1;
		#10;
		clk = 0;
		#10;	clk = 1;



	end


endmodule