det101_tb

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity det101_tb is

end det101_tb;

architecture sim of det101_tb is
    signal x,reset : bit:='0';
    signal clk : bit:='1';
    signal q : bit;
begin
    UUT: entity work.det101 port map (clk=>clk, reset=>reset, x=>x, q=>q);

    process begin
    clk <= not clk;
    wait for 5ns;
    end process;

    process begin
    wait for 22 ns;
    x<='1';
    wait for 10 ns;
    x<='0';
    wait for 10 ns;
    x<='1';
     wait for 15ns;
     x<='0';
     wait for 30 ns;
     x<='1';
     wait for 70 ns;
     x<='0';
     wait for 20 ns;
     x<='1';
     wait for 10 ns;
     x<='0';
     wait for 10 ns;
     x<='1';
     wait for 10ns;
     x<='1';
     wait for 10 ns;
     x<='0';
     wait for 10 ns;
     x<='1';
     wait for 10ns;
     x<='0';
     wait for 10 ns;
     x<='1';
     wait for 10 ns;
     x<='0';
     wait for 10 ns;
     x<='1';
     end process;

     process begin
     reset<='0';
     wait for 160 ns;
     reset<='1';
     wait for 45 ns;
     end process;


end sim;