library ieee;
use ieee.std_logic_1164.all;


entity automat is


	port
	(
		-- Input ports
		clk,reset,n_5,n_10,n_20	: in  std_logic;


		-- Output ports
		voda_out,n5_out,n10_out	: out std_logic

	);
end automat;

architecture automat_behav of automat is
type state_type is (racunaj,izbaci);
signal state_reg,next_state: state_type;
constant cena_vode: integer := 30;
signal suma:integer range 0 to (cena_vode+15):=0;
signal novcic: integer range 0 to 20;
begin

	state_transition: process (clk, reset)
	begin
	if(reset='1') then
	state_reg<=racunaj;

	elsif (rising_edge(clk)) then
	state_reg<=next_state;
	end if;

	end process state_transition;


	next_state_logic: process (suma,state_reg)
	begin
	  case(state_reg) is
		when racunaj =>
			if(suma>=cena_vode) then
				next_state<= izbaci;
		else
			next_state<=racunaj;

		end if;
		when izbaci=>
	      next_state<= racunaj;
	  end case;


	end process next_state_logic;

	novcic<= 5 when n_5='1' else
				10 when n_10='1' else
				20 when n_20='1' else
				0;

	generisanje_sume:process (clk,reset) -- da li treba state_reg ? razlicito je sekv, komb proces , sekv=> samo kad se menja takt i reset tada se menja izlaz,  nije bitno dal se promenio state_reg ako nije rising_edge clk, za komb je bitno jer se izlaz menja (evaluira=proverava dal treba da se promeni) kad god se bilo koji ulaz promeni
	begin         -- sve sto je sa desne strane <= i sve sto je u if i u case je u sensitiviti listu za kombinacione

	if(reset='1') then
	suma<=0;

	elsif (rising_edge(clk)) then


	case(state_reg) is    --jednak prioritet svakom stanju , a if ne daje
		when racunaj =>
			suma<=suma+novcic;

		when izbaci=>
	     suma<=0;
	  end case;


	end if;

	end process generisanje_sume;



	output_logic:process(state_reg, suma)  --komb
	  variable kusur: integer range 0 to 15:=0;  --da bi upakovalo u promenljivu, ali moze i sve u case
	begin
	 case(state_reg) is
			when racunaj =>
			voda_out<='0';
			n5_out<='0';
			n10_out<='0';

			when izbaci=>
				voda_out<='1';
			   kusur:=suma-cena_vode;
				case(kusur) is
					when 15=>
						n5_out<='1';
						n10_out<='1';
					when 10=>
						n5_out<='0';
						n10_out<='1';
					when 5=>
						n5_out<='1';
						n10_out<='0';
					when others=>
						n5_out<='0';
						n10_out<='0';
					end case;

	  end case;


end process output_logic;


end automat_behav;