library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity divisor is
    generic
    (
        DATA_WIDTH : natural := 8;
        ADDR_WIDTH : natural := 3
    );

    port (
        clk     : in std_logic;
        reset   : in std_logic;
        raddr   : in natural range 0 to 2**ADDR_WIDTH - 1;
        waddr   : in natural range 0 to 2**ADDR_WIDTH - 1;
        max     : in std_logic_vector((DATA_WIDTH -1) downto 0);
        data    : in std_logic_vector((DATA_WIDTH -1) downto 0);
        q       : out std_logic_vector((DATA_WIDTH -1) downto 0)

        );

end divisor;

architecture rtl of divisor is

    -- Build a 2-D array type for the RAM
    subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
    type memory_t is array(natural range <>) of word_t;

    -- Declare the RAM signal.
    signal ram, div : memory_t((2**ADDR_WIDTH)-1 downto 0);

    -- Declare the n and max_reg signal.
    signal n,m,nb : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
    signal max_reg : std_logic_vector(((2*DATA_WIDTH)-1) downto 0);


    -- Build div_reg, ram_reg
    type memory_reg is array(natural range <>) of std_logic_vector(((2*DATA_WIDTH)-1) downto 0);

    signal ram_reg: memory_reg((2**ADDR_WIDTH)-1 downto 0);

begin
    process(clk,reset)
    begin
    if (reset = '1') then
            ram(waddr) <= X"00";
            div(waddr) <= X"00";
            max_reg <= X"0000";
            ram_reg(waddr) <= X"0000";
            n <= X"0000";
            nb <= X"0000";
            m <= X"0000";
    elsif(rising_edge(clk)) then
        ram(waddr) <= data;
        max_reg((DATA_WIDTH -1) downto 0) <= max((DATA_WIDTH -1) downto 0);
        ram_reg(waddr)((DATA_WIDTH-1) downto 0) <= ram(waddr)((DATA_WIDTH-1) downto 0);
        nb <= std_logic_vector(unsigned(nb)+1);
        if (ram(waddr) = max)then
            div(waddr) <= std_logic_vector(unsigned(div(waddr))+1);
        elsif (ram(waddr) > max)then
            while (((unsigned(div(waddr))*unsigned(ram(waddr))) > unsigned(max)) or (unsigned(m) <(DATA_WIDTH -1))) loop
                div(waddr) <= std_logic_vector(unsigned(div(waddr))+1);
                max_reg <= std_logic_vector(unsigned(max_reg) - unsigned(ram_reg(waddr)));
                m <= std_logic_vector(unsigned(m)+1);
            end loop;
            m <= std_logic_vector(unsigned(m)-1);
            while (((unsigned(div(waddr))*unsigned(ram_reg(waddr))) < unsigned(max_reg)-1) or (unsigned(n) <(DATA_WIDTH)-unsigned(m))) loop
                ram_reg(waddr)(((2*DATA_WIDTH)-1) downto 1) <= ram_reg(waddr)(((2*DATA_WIDTH)-1) downto 0);
                n <= std_logic_vector(unsigned(n)+1);
                nb <= std_logic_vector(unsigned(nb)*2);
            end loop;
            ram_reg(waddr) <= std_logic_vector(unsigned(ram_reg(waddr)) - unsigned(max_reg));
            div(waddr) <= std_logic_vector(unsigned(div(waddr))+(1/(unsigned(nb))));
        else
            while (((unsigned(div(waddr))*unsigned(ram_reg(waddr))) < unsigned(max_reg)-1) or (unsigned(n)<(DATA_WIDTH-1))) loop
                ram_reg(waddr)(((2*DATA_WIDTH)-1) downto 1) <= ram_reg(waddr)(((2*DATA_WIDTH)-1) downto 0);
                ram_reg(waddr)(0) <= '0';
                n <= std_logic_vector(unsigned(n)+1);
                nb <= std_logic_vector(unsigned(nb)*2);
            end loop;
            ram_reg(waddr) <= std_logic_vector(unsigned(ram_reg(waddr)) - unsigned(max_reg));
            div(waddr) <= std_logic_vector(unsigned(div(waddr))+(1/(unsigned(nb))));
        end if;
    else null;
    end if;

    end process;

    q <= div(waddr);

end rtl;