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OrangePiH6.dts 3.10 kernel

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  1. tk@lime2:~$ cat OrangePiH6.dts
  2. /dts-v1/;
  3.  
  4. /memreserve/ 0x0000000040020000 0x0000000000000800;
  5. /memreserve/ 0x0000000048000000 0x0000000001000000;
  6. /memreserve/ 0x0000000048100000 0x0000000000004000;
  7. /memreserve/ 0x0000000048104000 0x0000000000001000;
  8. /memreserve/ 0x0000000048105000 0x0000000000001000;
  9. / {
  10. model = "sun50iw6";
  11. compatible = "arm,sun50iw6p1";
  12. interrupt-parent = <0x1>;
  13. #address-cells = <0x2>;
  14. #size-cells = <0x2>;
  15.  
  16. clocks {
  17. compatible = "allwinner,sunxi-clk-init";
  18. device_type = "clocks";
  19. #address-cells = <0x2>;
  20. #size-cells = <0x2>;
  21. ranges;
  22. reg = <0x0 0x3001000 0x0 0x1000 0x0 0x7010000 0x0 0x400 0x0 0x7000000 0x0 0x4>;
  23.  
  24. losc {
  25. #clock-cells = <0x0>;
  26. compatible = "allwinner,fixed-clock";
  27. clock-frequency = <0x8000>;
  28. clock-output-names = "losc";
  29. linux,phandle = <0xd>;
  30. phandle = <0xd>;
  31. };
  32.  
  33. iosc {
  34. #clock-cells = <0x0>;
  35. compatible = "allwinner,fixed-clock";
  36. clock-frequency = <0xf42400>;
  37. clock-output-names = "iosc";
  38. linux,phandle = <0xe>;
  39. phandle = <0xe>;
  40. };
  41.  
  42. hosc {
  43. #clock-cells = <0x0>;
  44. compatible = "allwinner,fixed-clock";
  45. clock-frequency = <0x16e3600>;
  46. clock-output-names = "hosc";
  47. linux,phandle = <0x7>;
  48. phandle = <0x7>;
  49. };
  50.  
  51. osc48m {
  52. #clock-cells = <0x0>;
  53. compatible = "allwinner,fixed-clock";
  54. clock-frequency = <0x2dc6c00>;
  55. clock-output-names = "osc48m";
  56. linux,phandle = <0x8>;
  57. phandle = <0x8>;
  58. };
  59.  
  60. pll_cpu {
  61. #clock-cells = <0x0>;
  62. compatible = "allwinner,sunxi-pll-clock";
  63. lock-mode = "new";
  64. clock-output-names = "pll_cpu";
  65. };
  66.  
  67. pll_ddr0 {
  68. #clock-cells = <0x0>;
  69. compatible = "allwinner,sunxi-pll-clock";
  70. lock-mode = "new";
  71. clock-output-names = "pll_ddr0";
  72. linux,phandle = <0xd3>;
  73. phandle = <0xd3>;
  74. };
  75.  
  76. pll_periph0 {
  77. #clock-cells = <0x0>;
  78. compatible = "allwinner,sunxi-pll-clock";
  79. assigned-clock-rates = <0x23c34600>;
  80. lock-mode = "new";
  81. clock-output-names = "pll_periph0";
  82. linux,phandle = <0x2>;
  83. phandle = <0x2>;
  84. };
  85.  
  86. pll_periph1 {
  87. #clock-cells = <0x0>;
  88. compatible = "allwinner,sunxi-pll-clock";
  89. assigned-clock-rates = <0x23c34600>;
  90. lock-mode = "new";
  91. clock-output-names = "pll_periph1";
  92. linux,phandle = <0x3>;
  93. phandle = <0x3>;
  94. };
  95.  
  96. pll_gpu {
  97. #clock-cells = <0x0>;
  98. compatible = "allwinner,sunxi-pll-clock";
  99. lock-mode = "new";
  100. clock-output-names = "pll_gpu";
  101. linux,phandle = <0xd5>;
  102. phandle = <0xd5>;
  103. };
  104.  
  105. pll_video0 {
  106. #clock-cells = <0x0>;
  107. compatible = "allwinner,sunxi-pll-clock";
  108. lock-mode = "new";
  109. clock-output-names = "pll_video0";
  110. linux,phandle = <0x5>;
  111. phandle = <0x5>;
  112. };
  113.  
  114. pll_video1 {
  115. #clock-cells = <0x0>;
  116. compatible = "allwinner,sunxi-pll-clock";
  117. lock-mode = "new";
  118. assigned-clock-rates = <0x2367b880>;
  119. clock-output-names = "pll_video1";
  120. linux,phandle = <0x6>;
  121. phandle = <0x6>;
  122. };
  123.  
  124. pll_ve {
  125. #clock-cells = <0x0>;
  126. compatible = "allwinner,sunxi-pll-clock";
  127. device_type = "clk_pll_ve";
  128. lock-mode = "new";
  129. clock-output-names = "pll_ve";
  130. linux,phandle = <0x17>;
  131. phandle = <0x17>;
  132. };
  133.  
  134. pll_de {
  135. #clock-cells = <0x0>;
  136. compatible = "allwinner,sunxi-pll-clock";
  137. assigned-clock-rates = <0x297c1e00>;
  138. lock-mode = "new";
  139. clock-output-names = "pll_de";
  140. linux,phandle = <0x9>;
  141. phandle = <0x9>;
  142. };
  143.  
  144. pll_hsic {
  145. #clock-cells = <0x0>;
  146. compatible = "allwinner,sunxi-pll-clock";
  147. lock-mode = "new";
  148. clock-output-names = "pll_hsic";
  149. linux,phandle = <0x3f>;
  150. phandle = <0x3f>;
  151. };
  152.  
  153. pll_audio {
  154. #clock-cells = <0x0>;
  155. compatible = "allwinner,sunxi-pll-clock";
  156. lock-mode = "new";
  157. clock-output-names = "pll_audio";
  158. linux,phandle = <0x4>;
  159. phandle = <0x4>;
  160. };
  161.  
  162. pll_periph0x2 {
  163. #clock-cells = <0x0>;
  164. compatible = "allwinner,fixed-factor-clock";
  165. clocks = <0x2>;
  166. clock-mult = <0x2>;
  167. clock-div = <0x1>;
  168. clock-output-names = "pll_periph0x2";
  169. linux,phandle = <0x1b>;
  170. phandle = <0x1b>;
  171. };
  172.  
  173. pll_periph0x4 {
  174. #clock-cells = <0x0>;
  175. compatible = "allwinner,fixed-factor-clock";
  176. clocks = <0x2>;
  177. clock-mult = <0x4>;
  178. clock-div = <0x1>;
  179. clock-output-names = "pll_periph0x4";
  180. };
  181.  
  182. periph32k {
  183. #clock-cells = <0x0>;
  184. compatible = "allwinner,fixed-factor-clock";
  185. clocks = <0x2>;
  186. clock-mult = <0x2>;
  187. clock-div = <0x8f0d>;
  188. clock-output-names = "periph32k";
  189. };
  190.  
  191. pll_periph1x2 {
  192. #clock-cells = <0x0>;
  193. compatible = "allwinner,fixed-factor-clock";
  194. clocks = <0x3>;
  195. clock-mult = <0x2>;
  196. clock-div = <0x1>;
  197. clock-output-names = "pll_periph1x2";
  198. linux,phandle = <0x73>;
  199. phandle = <0x73>;
  200. };
  201.  
  202. pll_audiox4 {
  203. #clock-cells = <0x0>;
  204. compatible = "allwinner,fixed-factor-clock";
  205. clocks = <0x4>;
  206. clock-mult = <0x4>;
  207. clock-div = <0x1>;
  208. clock-output-names = "pll_audiox4";
  209. };
  210.  
  211. pll_audiox2 {
  212. #clock-cells = <0x0>;
  213. compatible = "allwinner,fixed-factor-clock";
  214. clocks = <0x4>;
  215. clock-mult = <0x2>;
  216. clock-div = <0x1>;
  217. clock-output-names = "pll_audiox2";
  218. };
  219.  
  220. pll_video0x4 {
  221. #clock-cells = <0x0>;
  222. compatible = "allwinner,fixed-factor-clock";
  223. clocks = <0x5>;
  224. clock-mult = <0x4>;
  225. clock-div = <0x1>;
  226. clock-output-names = "pll_video0x4";
  227. };
  228.  
  229. pll_video1x4 {
  230. #clock-cells = <0x0>;
  231. compatible = "allwinner,fixed-factor-clock";
  232. clocks = <0x6>;
  233. clock-mult = <0x4>;
  234. clock-div = <0x1>;
  235. clock-output-names = "pll_video1x4";
  236. };
  237.  
  238. hoscd2 {
  239. #clock-cells = <0x0>;
  240. compatible = "allwinner,fixed-factor-clock";
  241. clocks = <0x7>;
  242. clock-mult = <0x1>;
  243. clock-div = <0x2>;
  244. clock-output-names = "hoscd2";
  245. };
  246.  
  247. osc48md4 {
  248. #clock-cells = <0x0>;
  249. compatible = "allwinner,fixed-factor-clock";
  250. clocks = <0x8>;
  251. clock-mult = <0x1>;
  252. clock-div = <0x4>;
  253. clock-output-names = "osc48md4";
  254. linux,phandle = <0x39>;
  255. phandle = <0x39>;
  256. };
  257.  
  258. pll_periph0d6 {
  259. #clock-cells = <0x0>;
  260. compatible = "allwinner,fixed-factor-clock";
  261. clocks = <0x2>;
  262. clock-mult = <0x1>;
  263. clock-div = <0x6>;
  264. clock-output-names = "pll_periph0d6";
  265. };
  266.  
  267. cpu {
  268. #clock-cells = <0x0>;
  269. compatible = "allwinner,sunxi-periph-clock";
  270. clock-output-names = "cpu";
  271. };
  272.  
  273. axi {
  274. #clock-cells = <0x0>;
  275. compatible = "allwinner,sunxi-periph-clock";
  276. clock-output-names = "axi";
  277. };
  278.  
  279. cpuapb {
  280. #clock-cells = <0x0>;
  281. compatible = "allwinner,sunxi-periph-clock";
  282. clock-output-names = "cpuapb";
  283. };
  284.  
  285. psi {
  286. #clock-cells = <0x0>;
  287. compatible = "allwinner,sunxi-periph-clock";
  288. clock-output-names = "psi";
  289. };
  290.  
  291. ahb1 {
  292. #clock-cells = <0x0>;
  293. compatible = "allwinner,sunxi-periph-clock";
  294. clock-output-names = "ahb1";
  295. };
  296.  
  297. ahb2 {
  298. #clock-cells = <0x0>;
  299. compatible = "allwinner,sunxi-periph-clock";
  300. clock-output-names = "ahb2";
  301. };
  302.  
  303. ahb3 {
  304. #clock-cells = <0x0>;
  305. compatible = "allwinner,sunxi-periph-clock";
  306. clock-output-names = "ahb3";
  307. };
  308.  
  309. apb1 {
  310. #clock-cells = <0x0>;
  311. compatible = "allwinner,sunxi-periph-clock";
  312. clock-output-names = "apb1";
  313. };
  314.  
  315. apb2 {
  316. #clock-cells = <0x0>;
  317. compatible = "allwinner,sunxi-periph-clock";
  318. clock-output-names = "apb2";
  319. linux,phandle = <0xaa>;
  320. phandle = <0xaa>;
  321. };
  322.  
  323. mbus {
  324. #clock-cells = <0x0>;
  325. compatible = "allwinner,sunxi-periph-clock";
  326. clock-output-names = "mbus";
  327. };
  328.  
  329. de {
  330. #clock-cells = <0x0>;
  331. compatible = "allwinner,sunxi-periph-clock";
  332. assigned-clock-parents = <0x9>;
  333. assigned-clock-rates = <0x297c1e00>;
  334. clock-output-names = "de";
  335. linux,phandle = <0x84>;
  336. phandle = <0x84>;
  337. };
  338.  
  339. di {
  340. #clock-cells = <0x0>;
  341. compatible = "allwinner,sunxi-periph-clock";
  342. clock-output-names = "di";
  343. linux,phandle = <0xa8>;
  344. phandle = <0xa8>;
  345. };
  346.  
  347. gpu {
  348. #clock-cells = <0x0>;
  349. compatible = "allwinner,sunxi-periph-clock";
  350. clock-output-names = "gpu";
  351. linux,phandle = <0xd6>;
  352. phandle = <0xd6>;
  353. };
  354.  
  355. ce {
  356. #clock-cells = <0x0>;
  357. compatible = "allwinner,sunxi-periph-clock";
  358. clock-output-names = "ce";
  359. linux,phandle = <0xa7>;
  360. phandle = <0xa7>;
  361. };
  362.  
  363. ve {
  364. #clock-cells = <0x0>;
  365. compatible = "allwinner,sunxi-periph-clock";
  366. clock-output-names = "ve";
  367. linux,phandle = <0x18>;
  368. phandle = <0x18>;
  369. };
  370.  
  371. emce {
  372. #clock-cells = <0x0>;
  373. compatible = "allwinner,sunxi-periph-clock";
  374. clock-output-names = "emce";
  375. linux,phandle = <0xa6>;
  376. phandle = <0xa6>;
  377. };
  378.  
  379. vp9 {
  380. #clock-cells = <0x0>;
  381. compatible = "allwinner,sunxi-periph-clock";
  382. clock-output-names = "vp9";
  383. linux,phandle = <0x1a>;
  384. phandle = <0x1a>;
  385. };
  386.  
  387. dma {
  388. #clock-cells = <0x0>;
  389. compatible = "allwinner,sunxi-periph-clock";
  390. clock-output-names = "dma";
  391. linux,phandle = <0xc>;
  392. phandle = <0xc>;
  393. };
  394.  
  395. msgbox {
  396. #clock-cells = <0x0>;
  397. compatible = "allwinner,sunxi-periph-clock";
  398. clock-output-names = "msgbox";
  399. linux,phandle = <0xf>;
  400. phandle = <0xf>;
  401. };
  402.  
  403. hwspinlock_rst {
  404. #clock-cells = <0x0>;
  405. compatible = "allwinner,sunxi-periph-clock";
  406. clock-output-names = "hwspinlock_rst";
  407. linux,phandle = <0x10>;
  408. phandle = <0x10>;
  409. };
  410.  
  411. hwspinlock_bus {
  412. #clock-cells = <0x0>;
  413. compatible = "allwinner,sunxi-periph-clock";
  414. clock-output-names = "hwspinlock_bus";
  415. linux,phandle = <0x11>;
  416. phandle = <0x11>;
  417. };
  418.  
  419. hstimer {
  420. #clock-cells = <0x0>;
  421. compatible = "allwinner,sunxi-periph-clock";
  422. clock-output-names = "hstimer";
  423. };
  424.  
  425. avs {
  426. #clock-cells = <0x0>;
  427. compatible = "allwinner,sunxi-periph-clock";
  428. clock-output-names = "avs";
  429. };
  430.  
  431. dbgsys {
  432. #clock-cells = <0x0>;
  433. compatible = "allwinner,sunxi-periph-clock";
  434. clock-output-names = "dbgsys";
  435. };
  436.  
  437. pwm {
  438. #clock-cells = <0x0>;
  439. compatible = "allwinner,sunxi-periph-clock";
  440. clock-output-names = "pwm";
  441. linux,phandle = <0x8f>;
  442. phandle = <0x8f>;
  443. };
  444.  
  445. iommu {
  446. #clock-cells = <0x0>;
  447. compatible = "allwinner,sunxi-periph-clock";
  448. clock-output-names = "iommu";
  449. linux,phandle = <0xd4>;
  450. phandle = <0xd4>;
  451. };
  452.  
  453. sdram {
  454. #clock-cells = <0x0>;
  455. compatible = "allwinner,sunxi-periph-clock";
  456. clock-output-names = "sdram";
  457. };
  458.  
  459. nand0 {
  460. #clock-cells = <0x0>;
  461. compatible = "allwinner,sunxi-periph-clock";
  462. clock-output-names = "nand0";
  463. linux,phandle = <0xb2>;
  464. phandle = <0xb2>;
  465. };
  466.  
  467. nand1 {
  468. #clock-cells = <0x0>;
  469. compatible = "allwinner,sunxi-periph-clock";
  470. clock-output-names = "nand1";
  471. linux,phandle = <0xb3>;
  472. phandle = <0xb3>;
  473. };
  474.  
  475. sdmmc0_mod {
  476. #clock-cells = <0x0>;
  477. compatible = "allwinner,sunxi-periph-clock";
  478. clock-output-names = "sdmmc0_mod";
  479. linux,phandle = <0x79>;
  480. phandle = <0x79>;
  481. };
  482.  
  483. sdmmc0_bus {
  484. #clock-cells = <0x0>;
  485. compatible = "allwinner,sunxi-periph-clock";
  486. clock-output-names = "sdmmc0_bus";
  487. linux,phandle = <0x7a>;
  488. phandle = <0x7a>;
  489. };
  490.  
  491. sdmmc0_rst {
  492. #clock-cells = <0x0>;
  493. compatible = "allwinner,sunxi-periph-clock";
  494. clock-output-names = "sdmmc0_rst";
  495. linux,phandle = <0x7b>;
  496. phandle = <0x7b>;
  497. };
  498.  
  499. sdmmc1_mod {
  500. #clock-cells = <0x0>;
  501. compatible = "allwinner,sunxi-periph-clock";
  502. clock-output-names = "sdmmc1_mod";
  503. linux,phandle = <0x7f>;
  504. phandle = <0x7f>;
  505. };
  506.  
  507. sdmmc1_bus {
  508. #clock-cells = <0x0>;
  509. compatible = "allwinner,sunxi-periph-clock";
  510. clock-output-names = "sdmmc1_bus";
  511. linux,phandle = <0x80>;
  512. phandle = <0x80>;
  513. };
  514.  
  515. sdmmc1_rst {
  516. #clock-cells = <0x0>;
  517. compatible = "allwinner,sunxi-periph-clock";
  518. clock-output-names = "sdmmc1_rst";
  519. linux,phandle = <0x81>;
  520. phandle = <0x81>;
  521. };
  522.  
  523. sdmmc2_mod {
  524. #clock-cells = <0x0>;
  525. compatible = "allwinner,sunxi-periph-clock";
  526. clock-output-names = "sdmmc2_mod";
  527. linux,phandle = <0x74>;
  528. phandle = <0x74>;
  529. };
  530.  
  531. sdmmc2_bus {
  532. #clock-cells = <0x0>;
  533. compatible = "allwinner,sunxi-periph-clock";
  534. clock-output-names = "sdmmc2_bus";
  535. linux,phandle = <0x75>;
  536. phandle = <0x75>;
  537. };
  538.  
  539. sdmmc2_rst {
  540. #clock-cells = <0x0>;
  541. compatible = "allwinner,sunxi-periph-clock";
  542. clock-output-names = "sdmmc2_rst";
  543. linux,phandle = <0x76>;
  544. phandle = <0x76>;
  545. };
  546.  
  547. uart0 {
  548. #clock-cells = <0x0>;
  549. compatible = "allwinner,sunxi-periph-clock";
  550. clock-output-names = "uart0";
  551. linux,phandle = <0x1c>;
  552. phandle = <0x1c>;
  553. };
  554.  
  555. uart1 {
  556. #clock-cells = <0x0>;
  557. compatible = "allwinner,sunxi-periph-clock";
  558. clock-output-names = "uart1";
  559. linux,phandle = <0x1f>;
  560. phandle = <0x1f>;
  561. };
  562.  
  563. uart2 {
  564. #clock-cells = <0x0>;
  565. compatible = "allwinner,sunxi-periph-clock";
  566. clock-output-names = "uart2";
  567. linux,phandle = <0x22>;
  568. phandle = <0x22>;
  569. };
  570.  
  571. uart3 {
  572. #clock-cells = <0x0>;
  573. compatible = "allwinner,sunxi-periph-clock";
  574. clock-output-names = "uart3";
  575. linux,phandle = <0x25>;
  576. phandle = <0x25>;
  577. };
  578.  
  579. twi0 {
  580. #clock-cells = <0x0>;
  581. compatible = "allwinner,sunxi-periph-clock";
  582. clock-output-names = "twi0";
  583. linux,phandle = <0x28>;
  584. phandle = <0x28>;
  585. };
  586.  
  587. twi1 {
  588. #clock-cells = <0x0>;
  589. compatible = "allwinner,sunxi-periph-clock";
  590. clock-output-names = "twi1";
  591. linux,phandle = <0x2b>;
  592. phandle = <0x2b>;
  593. };
  594.  
  595. twi2 {
  596. #clock-cells = <0x0>;
  597. compatible = "allwinner,sunxi-periph-clock";
  598. clock-output-names = "twi2";
  599. linux,phandle = <0x2e>;
  600. phandle = <0x2e>;
  601. };
  602.  
  603. twi3 {
  604. #clock-cells = <0x0>;
  605. compatible = "allwinner,sunxi-periph-clock";
  606. clock-output-names = "twi3";
  607. linux,phandle = <0x31>;
  608. phandle = <0x31>;
  609. };
  610.  
  611. scr0 {
  612. #clock-cells = <0x0>;
  613. compatible = "allwinner,sunxi-periph-clock";
  614. clock-output-names = "scr0";
  615. linux,phandle = <0xa9>;
  616. phandle = <0xa9>;
  617. };
  618.  
  619. scr1 {
  620. #clock-cells = <0x0>;
  621. compatible = "allwinner,sunxi-periph-clock";
  622. clock-output-names = "scr1";
  623. linux,phandle = <0xae>;
  624. phandle = <0xae>;
  625. };
  626.  
  627. spi0 {
  628. #clock-cells = <0x0>;
  629. compatible = "allwinner,sunxi-periph-clock";
  630. clock-output-names = "spi0";
  631. linux,phandle = <0x67>;
  632. phandle = <0x67>;
  633. };
  634.  
  635. spi1 {
  636. #clock-cells = <0x0>;
  637. compatible = "allwinner,sunxi-periph-clock";
  638. clock-output-names = "spi1";
  639. linux,phandle = <0x6b>;
  640. phandle = <0x6b>;
  641. };
  642.  
  643. gmac {
  644. #clock-cells = <0x0>;
  645. compatible = "allwinner,sunxi-periph-clock";
  646. clock-output-names = "gmac";
  647. linux,phandle = <0xce>;
  648. phandle = <0xce>;
  649. };
  650.  
  651. sata {
  652. #clock-cells = <0x0>;
  653. compatible = "allwinner,sunxi-periph-clock";
  654. clock-output-names = "sata";
  655. };
  656.  
  657. sata_24m {
  658. #clock-cells = <0x0>;
  659. compatible = "allwinner,sunxi-periph-clock";
  660. clock-output-names = "sata_24m";
  661. };
  662.  
  663. ts {
  664. #clock-cells = <0x0>;
  665. compatible = "allwinner,sunxi-periph-clock";
  666. clock-output-names = "ts";
  667. linux,phandle = <0xb7>;
  668. phandle = <0xb7>;
  669. };
  670.  
  671. irtx {
  672. #clock-cells = <0x0>;
  673. compatible = "allwinner,sunxi-periph-clock";
  674. clock-output-names = "irtx";
  675. };
  676.  
  677. ths {
  678. #clock-cells = <0x0>;
  679. compatible = "allwinner,sunxi-periph-clock";
  680. clock-output-names = "ths";
  681. linux,phandle = <0xc0>;
  682. phandle = <0xc0>;
  683. };
  684.  
  685. i2s0 {
  686. #clock-cells = <0x0>;
  687. compatible = "allwinner,sunxi-periph-clock";
  688. clock-output-names = "i2s0";
  689. linux,phandle = <0x42>;
  690. phandle = <0x42>;
  691. };
  692.  
  693. i2s1 {
  694. #clock-cells = <0x0>;
  695. compatible = "allwinner,sunxi-periph-clock";
  696. clock-output-names = "i2s1";
  697. linux,phandle = <0x45>;
  698. phandle = <0x45>;
  699. };
  700.  
  701. i2s2 {
  702. #clock-cells = <0x0>;
  703. compatible = "allwinner,sunxi-periph-clock";
  704. clock-output-names = "i2s2";
  705. linux,phandle = <0x46>;
  706. phandle = <0x46>;
  707. };
  708.  
  709. i2s3 {
  710. #clock-cells = <0x0>;
  711. compatible = "allwinner,sunxi-periph-clock";
  712. clock-output-names = "i2s3";
  713. linux,phandle = <0x49>;
  714. phandle = <0x49>;
  715. };
  716.  
  717. spdif {
  718. #clock-cells = <0x0>;
  719. compatible = "allwinner,sunxi-periph-clock";
  720. clock-output-names = "spdif";
  721. linux,phandle = <0x4c>;
  722. phandle = <0x4c>;
  723. };
  724.  
  725. dmic {
  726. #clock-cells = <0x0>;
  727. compatible = "allwinner,sunxi-periph-clock";
  728. clock-output-names = "dmic";
  729. linux,phandle = <0x4f>;
  730. phandle = <0x4f>;
  731. };
  732.  
  733. ahub {
  734. #clock-cells = <0x0>;
  735. compatible = "allwinner,sunxi-periph-clock";
  736. clock-output-names = "ahub";
  737. linux,phandle = <0x52>;
  738. phandle = <0x52>;
  739. };
  740.  
  741. usbphy0 {
  742. #clock-cells = <0x0>;
  743. compatible = "allwinner,sunxi-periph-clock";
  744. clock-output-names = "usbphy0";
  745. linux,phandle = <0x34>;
  746. phandle = <0x34>;
  747. };
  748.  
  749. usbphy1 {
  750. #clock-cells = <0x0>;
  751. compatible = "allwinner,sunxi-periph-clock";
  752. clock-output-names = "usbphy1";
  753. linux,phandle = <0x3a>;
  754. phandle = <0x3a>;
  755. };
  756.  
  757. usbphy3 {
  758. #clock-cells = <0x0>;
  759. compatible = "allwinner,sunxi-periph-clock";
  760. clock-output-names = "usbphy3";
  761. linux,phandle = <0x3c>;
  762. phandle = <0x3c>;
  763. };
  764.  
  765. usbohci0 {
  766. #clock-cells = <0x0>;
  767. compatible = "allwinner,sunxi-periph-clock";
  768. clock-output-names = "usbohci0";
  769. linux,phandle = <0x37>;
  770. phandle = <0x37>;
  771. };
  772.  
  773. usbohci0_12m {
  774. #clock-cells = <0x0>;
  775. compatible = "allwinner,sunxi-periph-clock";
  776. clock-output-names = "usbohci0_12m";
  777. linux,phandle = <0x38>;
  778. phandle = <0x38>;
  779. };
  780.  
  781. usbohci3 {
  782. #clock-cells = <0x0>;
  783. compatible = "allwinner,sunxi-periph-clock";
  784. clock-output-names = "usbohci3";
  785. linux,phandle = <0x40>;
  786. phandle = <0x40>;
  787. };
  788.  
  789. usbohci3_12m {
  790. #clock-cells = <0x0>;
  791. compatible = "allwinner,sunxi-periph-clock";
  792. clock-output-names = "usbohci3_12m";
  793. linux,phandle = <0x41>;
  794. phandle = <0x41>;
  795. };
  796.  
  797. usbehci0 {
  798. #clock-cells = <0x0>;
  799. compatible = "allwinner,sunxi-periph-clock";
  800. clock-output-names = "usbehci0";
  801. linux,phandle = <0x36>;
  802. phandle = <0x36>;
  803. };
  804.  
  805. usbehci3 {
  806. #clock-cells = <0x0>;
  807. compatible = "allwinner,sunxi-periph-clock";
  808. clock-output-names = "usbehci3";
  809. linux,phandle = <0x3d>;
  810. phandle = <0x3d>;
  811. };
  812.  
  813. usb3_0_host {
  814. #clock-cells = <0x0>;
  815. compatible = "allwinner,sunxi-periph-clock";
  816. clock-output-names = "usb3_0_host";
  817. linux,phandle = <0x3b>;
  818. phandle = <0x3b>;
  819. };
  820.  
  821. usbotg {
  822. #clock-cells = <0x0>;
  823. compatible = "allwinner,sunxi-periph-clock";
  824. clock-output-names = "usbotg";
  825. linux,phandle = <0x35>;
  826. phandle = <0x35>;
  827. };
  828.  
  829. usbhsic {
  830. #clock-cells = <0x0>;
  831. compatible = "allwinner,sunxi-periph-clock";
  832. clock-output-names = "usbhsic";
  833. linux,phandle = <0x3e>;
  834. phandle = <0x3e>;
  835. };
  836.  
  837. pcieref {
  838. #clock-cells = <0x0>;
  839. compatible = "allwinner,sunxi-periph-clock";
  840. clock-output-names = "pcieref";
  841. linux,phandle = <0x6f>;
  842. phandle = <0x6f>;
  843. };
  844.  
  845. pciemaxi {
  846. #clock-cells = <0x0>;
  847. compatible = "allwinner,sunxi-periph-clock";
  848. assigned-clock-rates = <0xbebc200>;
  849. clock-output-names = "pciemaxi";
  850. linux,phandle = <0x70>;
  851. phandle = <0x70>;
  852. };
  853.  
  854. pcieaux {
  855. #clock-cells = <0x0>;
  856. compatible = "allwinner,sunxi-periph-clock";
  857. assigned-clock-rates = <0xf4240>;
  858. clock-output-names = "pcieaux";
  859. linux,phandle = <0x71>;
  860. phandle = <0x71>;
  861. };
  862.  
  863. pcie_bus {
  864. #clock-cells = <0x0>;
  865. compatible = "allwinner,sunxi-periph-clock";
  866. clock-output-names = "pcie_bus";
  867. linux,phandle = <0x72>;
  868. phandle = <0x72>;
  869. };
  870.  
  871. hdmi {
  872. #clock-cells = <0x0>;
  873. compatible = "allwinner,sunxi-periph-clock";
  874. assigned-clock-parents = <0x6>;
  875. clock-output-names = "hdmi";
  876. linux,phandle = <0x88>;
  877. phandle = <0x88>;
  878. };
  879.  
  880. hdmi_slow {
  881. #clock-cells = <0x0>;
  882. compatible = "allwinner,sunxi-periph-clock";
  883. clock-output-names = "hdmi_slow";
  884. linux,phandle = <0x89>;
  885. phandle = <0x89>;
  886. };
  887.  
  888. hdmi_cec {
  889. #clock-cells = <0x0>;
  890. compatible = "allwinner,sunxi-periph-clock";
  891. clock-output-names = "hdmi_cec";
  892. linux,phandle = <0x8b>;
  893. phandle = <0x8b>;
  894. };
  895.  
  896. display_top {
  897. #clock-cells = <0x0>;
  898. compatible = "allwinner,sunxi-periph-clock";
  899. clock-output-names = "display_top";
  900. linux,phandle = <0x85>;
  901. phandle = <0x85>;
  902. };
  903.  
  904. tcon_lcd {
  905. #clock-cells = <0x0>;
  906. compatible = "allwinner,sunxi-periph-clock";
  907. clock-output-names = "tcon_lcd";
  908. linux,phandle = <0x86>;
  909. phandle = <0x86>;
  910. };
  911.  
  912. tcon_tv {
  913. #clock-cells = <0x0>;
  914. compatible = "allwinner,sunxi-periph-clock";
  915. assigned-clock-parents = <0x6>;
  916. clock-output-names = "tcon_tv";
  917. linux,phandle = <0x87>;
  918. phandle = <0x87>;
  919. };
  920.  
  921. csi_misc {
  922. #clock-cells = <0x0>;
  923. compatible = "allwinner,sunxi-periph-clock";
  924. clock-output-names = "csi_misc";
  925. linux,phandle = <0x9a>;
  926. phandle = <0x9a>;
  927. };
  928.  
  929. csi_top {
  930. #clock-cells = <0x0>;
  931. compatible = "allwinner,sunxi-periph-clock";
  932. clock-output-names = "csi_top";
  933. linux,phandle = <0x96>;
  934. phandle = <0x96>;
  935. };
  936.  
  937. csi_master0 {
  938. #clock-cells = <0x0>;
  939. compatible = "allwinner,sunxi-periph-clock";
  940. clock-output-names = "csi_master0";
  941. linux,phandle = <0x97>;
  942. phandle = <0x97>;
  943. };
  944.  
  945. hdmi_hdcp {
  946. #clock-cells = <0x0>;
  947. compatible = "allwinner,sunxi-periph-clock";
  948. assigned-clock-parents = <0x3>;
  949. clock-output-names = "hdmi_hdcp";
  950. linux,phandle = <0x8a>;
  951. phandle = <0x8a>;
  952. };
  953.  
  954. pio {
  955. #clock-cells = <0x0>;
  956. compatible = "allwinner,sunxi-periph-clock";
  957. clock-output-names = "pio";
  958. linux,phandle = <0xb>;
  959. phandle = <0xb>;
  960. };
  961.  
  962. cpurcir {
  963. #clock-cells = <0x0>;
  964. compatible = "allwinner,sunxi-periph-cpus-clock";
  965. clock-output-names = "cpurcir";
  966. linux,phandle = <0x13>;
  967. phandle = <0x13>;
  968. };
  969.  
  970. losc_out {
  971. #clock-cells = <0x0>;
  972. compatible = "allwinner,sunxi-periph-cpus-clock";
  973. clock-output-names = "losc_out";
  974. linux,phandle = <0xd7>;
  975. phandle = <0xd7>;
  976. };
  977.  
  978. cpurcpus_pll {
  979. #clock-cells = <0x0>;
  980. compatible = "allwinner,sunxi-periph-cpus-clock";
  981. clock-output-names = "cpurcpus_pll";
  982. };
  983.  
  984. cpurcpus {
  985. #clock-cells = <0x0>;
  986. compatible = "allwinner,sunxi-periph-cpus-clock";
  987. clock-output-names = "cpurcpus";
  988. };
  989.  
  990. cpurahbs {
  991. #clock-cells = <0x0>;
  992. compatible = "allwinner,sunxi-periph-cpus-clock";
  993. clock-output-names = "cpurahbs";
  994. };
  995.  
  996. cpurapbs1 {
  997. #clock-cells = <0x0>;
  998. compatible = "allwinner,sunxi-periph-cpus-clock";
  999. clock-output-names = "cpurapbs1";
  1000. };
  1001.  
  1002. cpurapbs2_pll {
  1003. #clock-cells = <0x0>;
  1004. compatible = "allwinner,sunxi-periph-cpus-clock";
  1005. clock-output-names = "cpurapbs2_pll";
  1006. };
  1007.  
  1008. cpurapbs2 {
  1009. #clock-cells = <0x0>;
  1010. compatible = "allwinner,sunxi-periph-cpus-clock";
  1011. clock-output-names = "cpurapbs2";
  1012. };
  1013.  
  1014. cpurpio {
  1015. #clock-cells = <0x0>;
  1016. compatible = "allwinner,sunxi-periph-cpus-clock";
  1017. clock-output-names = "cpurpio";
  1018. linux,phandle = <0xa>;
  1019. phandle = <0xa>;
  1020. };
  1021.  
  1022. spwm {
  1023. #clock-cells = <0x0>;
  1024. compatible = "allwinner,sunxi-periph-cpus-clock";
  1025. clock-output-names = "spwm";
  1026. linux,phandle = <0x92>;
  1027. phandle = <0x92>;
  1028. };
  1029.  
  1030. dcxo_out {
  1031. #clock-cells = <0x0>;
  1032. compatible = "allwinner,sunxi-periph-cpus-clock";
  1033. clock-output-names = "dcxo_out";
  1034. };
  1035. };
  1036.  
  1037. soc@03000000 {
  1038. compatible = "simple-bus";
  1039. #address-cells = <0x2>;
  1040. #size-cells = <0x2>;
  1041. ranges;
  1042. device_type = "soc";
  1043.  
  1044. pinctrl@07022000 {
  1045. compatible = "allwinner,sun50iw6p1-r-pinctrl";
  1046. reg = <0x0 0x7022000 0x0 0x400>;
  1047. interrupts = <0x0 0x69 0x4 0x0 0x6f 0x4>;
  1048. clocks = <0xa>;
  1049. device_type = "r_pio";
  1050. gpio-controller;
  1051. interrupt-controller;
  1052. #interrupt-cells = <0x2>;
  1053. #size-cells = <0x0>;
  1054. #gpio-cells = <0x6>;
  1055. linux,phandle = <0xd8>;
  1056. phandle = <0xd8>;
  1057.  
  1058. s_twi0@0 {
  1059. allwinner,pins = "PL0", "PL1";
  1060. allwinner,function = "s_twi0";
  1061. allwinner,muxsel = <0x3>;
  1062. allwinner,drive = <0x0>;
  1063. allwinner,pull = <0x1>;
  1064. linux,phandle = <0x15>;
  1065. phandle = <0x15>;
  1066. };
  1067.  
  1068. s_cir0@0 {
  1069. allwinner,pins = "PL9";
  1070. allwinner,function = "s_cir0";
  1071. allwinner,muxsel = <0x2>;
  1072. allwinner,drive = <0x2>;
  1073. allwinner,pull = <0x1>;
  1074. linux,phandle = <0x12>;
  1075. phandle = <0x12>;
  1076. };
  1077.  
  1078. twi_para@0 {
  1079. linux,phandle = <0xdb>;
  1080. phandle = <0xdb>;
  1081. allwinner,pins = "PL0", "PL1";
  1082. allwinner,function = "twi_para";
  1083. allwinner,pname = "twi_scl", "twi_sda";
  1084. allwinner,muxsel = <0x3>;
  1085. allwinner,pull = <0x1>;
  1086. allwinner,drive = <0x0>;
  1087. allwinner,data = <0xffffffff>;
  1088. };
  1089.  
  1090. pwm16@0 {
  1091. linux,phandle = <0x103>;
  1092. phandle = <0x103>;
  1093. allwinner,pins = "PL8";
  1094. allwinner,function = "pwm16";
  1095. allwinner,pname = "pwm_positive";
  1096. allwinner,muxsel = <0x2>;
  1097. allwinner,pull = <0x0>;
  1098. allwinner,drive = <0xffffffff>;
  1099. allwinner,data = <0xffffffff>;
  1100. };
  1101.  
  1102. pwm16@1 {
  1103. linux,phandle = <0x104>;
  1104. phandle = <0x104>;
  1105. allwinner,pins = "PL8";
  1106. allwinner,function = "pwm16";
  1107. allwinner,pname = "pwm_positive";
  1108. allwinner,muxsel = <0x7>;
  1109. allwinner,pull = <0x0>;
  1110. allwinner,drive = <0xffffffff>;
  1111. allwinner,data = <0xffffffff>;
  1112. };
  1113.  
  1114. s_uart0@0 {
  1115. linux,phandle = <0x10a>;
  1116. phandle = <0x10a>;
  1117. allwinner,pins = "PL2", "PL3";
  1118. allwinner,function = "s_uart0";
  1119. allwinner,pname = "s_uart0_tx", "s_uart0_rx";
  1120. allwinner,muxsel = <0x2>;
  1121. allwinner,pull = <0xffffffff>;
  1122. allwinner,drive = <0xffffffff>;
  1123. allwinner,data = <0xffffffff>;
  1124. };
  1125.  
  1126. s_rsb0@0 {
  1127. linux,phandle = <0x10b>;
  1128. phandle = <0x10b>;
  1129. allwinner,pins = "PL0", "PL1";
  1130. allwinner,function = "s_rsb0";
  1131. allwinner,pname = "s_rsb0_sck", "s_rsb0_sda";
  1132. allwinner,muxsel = <0x2>;
  1133. allwinner,pull = <0x1>;
  1134. allwinner,drive = <0x2>;
  1135. allwinner,data = <0xffffffff>;
  1136. };
  1137.  
  1138. s_jtag0@0 {
  1139. linux,phandle = <0x10c>;
  1140. phandle = <0x10c>;
  1141. allwinner,pins = "PL4", "PL5", "PL6", "PL7";
  1142. allwinner,function = "s_jtag0";
  1143. allwinner,pname = "s_jtag0_tms", "s_jtag0_tck", "s_jtag0_tdo", "s_jtag0_tdi";
  1144. allwinner,muxsel = <0x2>;
  1145. allwinner,pull = <0x1>;
  1146. allwinner,drive = <0x2>;
  1147. allwinner,data = <0xffffffff>;
  1148. };
  1149. };
  1150.  
  1151. pinctrl@0300b000 {
  1152. compatible = "allwinner,sun50iw6p1-pinctrl";
  1153. reg = <0x0 0x300b000 0x0 0x400>;
  1154. interrupts = <0x0 0x33 0x4 0x0 0x35 0x4 0x0 0x36 0x4 0x0 0x3b 0x4>;
  1155. device_type = "pio";
  1156. clocks = <0xb>;
  1157. gpio-controller;
  1158. interrupt-controller;
  1159. #interrupt-cells = <0x2>;
  1160. #size-cells = <0x0>;
  1161. #gpio-cells = <0x6>;
  1162. linux,phandle = <0x7e>;
  1163. phandle = <0x7e>;
  1164.  
  1165. twi3@1 {
  1166. allwinner,pins = "PB17", "PB18";
  1167. allwinner,function = "io_disabled";
  1168. allwinner,muxsel = <0x7>;
  1169. allwinner,drive = <0x1>;
  1170. allwinner,pull = <0x0>;
  1171. linux,phandle = <0x33>;
  1172. phandle = <0x33>;
  1173. };
  1174.  
  1175. ts0@0 {
  1176. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1177. allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7";
  1178. allwinner,function = "ts0";
  1179. allwinner,muxsel = <0x3>;
  1180. allwinner,drive = <0x1>;
  1181. allwinner,pull = <0x0>;
  1182. linux,phandle = <0xb8>;
  1183. phandle = <0xb8>;
  1184. };
  1185.  
  1186. ts0_sleep@0 {
  1187. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1188. allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7";
  1189. allwinner,function = "io_disabled";
  1190. allwinner,muxsel = <0x7>;
  1191. allwinner,drive = <0x1>;
  1192. allwinner,pull = <0x0>;
  1193. linux,phandle = <0xbc>;
  1194. phandle = <0xbc>;
  1195. };
  1196.  
  1197. ts1@0 {
  1198. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16";
  1199. allwinner,pname = "ts1_clk", "ts1_err", "ts1_sync", "ts1_dvld", "ts1_d0";
  1200. allwinner,function = "ts1";
  1201. allwinner,muxsel = <0x3>;
  1202. allwinner,drive = <0x1>;
  1203. allwinner,pull = <0x0>;
  1204. linux,phandle = <0xb9>;
  1205. phandle = <0xb9>;
  1206. };
  1207.  
  1208. ts1_sleep@0 {
  1209. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16";
  1210. allwinner,pname = "ts1_clk", "ts1_err", "ts1_sync", "ts1_dvld", "ts1_d0";
  1211. allwinner,function = "io_disabled";
  1212. allwinner,muxsel = <0x7>;
  1213. allwinner,drive = <0x1>;
  1214. allwinner,pull = <0x0>;
  1215. linux,phandle = <0xbd>;
  1216. phandle = <0xbd>;
  1217. };
  1218.  
  1219. ts2@0 {
  1220. allwinner,pins = "PD17", "PD18", "PD19", "PD20", "PD21";
  1221. allwinner,pname = "ts2_clk", "ts2_err", "ts2_sync", "ts2_dvld", "ts2_d0";
  1222. allwinner,function = "ts2";
  1223. allwinner,muxsel = <0x3>;
  1224. allwinner,drive = <0x1>;
  1225. allwinner,pull = <0x0>;
  1226. linux,phandle = <0xba>;
  1227. phandle = <0xba>;
  1228. };
  1229.  
  1230. ts2_sleep@0 {
  1231. allwinner,pins = "PD17", "PD18", "PD19", "PD20", "PD21";
  1232. allwinner,pname = "ts2_clk", "ts2_err", "ts2_sync", "ts2_dvld", "ts2_d0";
  1233. allwinner,function = "io_disabled";
  1234. allwinner,muxsel = <0x7>;
  1235. allwinner,drive = <0x1>;
  1236. allwinner,pull = <0x0>;
  1237. linux,phandle = <0xbe>;
  1238. phandle = <0xbe>;
  1239. };
  1240.  
  1241. ts3@0 {
  1242. allwinner,pins = "PD22", "PD23", "PD24", "PD25", "PD26";
  1243. allwinner,pname = "ts3_clk", "ts3_err", "ts3_sync", "ts3_dvld", "ts3_d0";
  1244. allwinner,function = "ts3";
  1245. allwinner,muxsel = <0x3>;
  1246. allwinner,drive = <0x1>;
  1247. allwinner,pull = <0x0>;
  1248. linux,phandle = <0xbb>;
  1249. phandle = <0xbb>;
  1250. };
  1251.  
  1252. ts3_sleep@0 {
  1253. allwinner,pins = "PD22", "PD23", "PD24", "PD25", "PD26";
  1254. allwinner,pname = "ts3_clk", "ts3_err", "ts3_sync", "ts3_dvld", "ts3_d0";
  1255. allwinner,function = "io_disabled";
  1256. allwinner,muxsel = <0x7>;
  1257. allwinner,drive = <0x1>;
  1258. allwinner,pull = <0x0>;
  1259. linux,phandle = <0xbf>;
  1260. phandle = <0xbf>;
  1261. };
  1262.  
  1263. sdc0@1 {
  1264. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1265. allwinner,function = "io_disabled";
  1266. allwinner,muxsel = <0x7>;
  1267. allwinner,drive = <0x1>;
  1268. allwinner,pull = <0x1>;
  1269. linux,phandle = <0x7d>;
  1270. phandle = <0x7d>;
  1271. };
  1272.  
  1273. sdc1@1 {
  1274. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  1275. allwinner,function = "io_disabled";
  1276. allwinner,muxsel = <0x7>;
  1277. allwinner,drive = <0x1>;
  1278. allwinner,pull = <0x1>;
  1279. linux,phandle = <0x83>;
  1280. phandle = <0x83>;
  1281. };
  1282.  
  1283. sdc2@1 {
  1284. allwinner,pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  1285. allwinner,function = "io_disabled";
  1286. allwinner,muxsel = <0x7>;
  1287. allwinner,drive = <0x1>;
  1288. allwinner,pull = <0x1>;
  1289. linux,phandle = <0x78>;
  1290. phandle = <0x78>;
  1291. };
  1292.  
  1293. daudio0@0 {
  1294. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1295. allwinner,function = "pcm0";
  1296. allwinner,muxsel = <0x3>;
  1297. allwinner,drive = <0x1>;
  1298. allwinner,pull = <0x0>;
  1299. linux,phandle = <0x43>;
  1300. phandle = <0x43>;
  1301. };
  1302.  
  1303. daudio0_sleep@0 {
  1304. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1305. allwinner,function = "io_disabled";
  1306. allwinner,muxsel = <0x7>;
  1307. allwinner,drive = <0x1>;
  1308. allwinner,pull = <0x0>;
  1309. linux,phandle = <0x44>;
  1310. phandle = <0x44>;
  1311. };
  1312.  
  1313. daudio2@0 {
  1314. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1315. allwinner,function = "pcm2";
  1316. allwinner,muxsel = <0x2>;
  1317. allwinner,drive = <0x1>;
  1318. allwinner,pull = <0x0>;
  1319. linux,phandle = <0x47>;
  1320. phandle = <0x47>;
  1321. };
  1322.  
  1323. daudio2_sleep@0 {
  1324. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1325. allwinner,function = "io_disabled";
  1326. allwinner,muxsel = <0x7>;
  1327. allwinner,drive = <0x1>;
  1328. allwinner,pull = <0x0>;
  1329. linux,phandle = <0x48>;
  1330. phandle = <0x48>;
  1331. };
  1332.  
  1333. daudio3@0 {
  1334. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1335. allwinner,function = "pcm3";
  1336. allwinner,muxsel = <0x2>;
  1337. allwinner,driver = <0x1>;
  1338. allwinner,pull = <0x0>;
  1339. linux,phandle = <0x4a>;
  1340. phandle = <0x4a>;
  1341. };
  1342.  
  1343. daudio3_sleep@0 {
  1344. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1345. allwinner,function = "io_disabled";
  1346. allwinner,muxsel = <0x7>;
  1347. allwinner,driver = <0x1>;
  1348. allwinner,pull = <0x0>;
  1349. linux,phandle = <0x4b>;
  1350. phandle = <0x4b>;
  1351. };
  1352.  
  1353. spdif@0 {
  1354. allwinner,pins = "PH5", "PH6", "PH7";
  1355. allwinner,function = "spdif0";
  1356. allwinner,muxsel = <0x3>;
  1357. allwinner,drive = <0x1>;
  1358. allwinner,pull = <0x0>;
  1359. linux,phandle = <0x4d>;
  1360. phandle = <0x4d>;
  1361. };
  1362.  
  1363. spdif_sleep@0 {
  1364. allwinner,pins = "PH5", "PH6", "PH7";
  1365. allwinner,function = "io_disabled";
  1366. allwinner,muxsel = <0x7>;
  1367. allwinner,drive = <0x1>;
  1368. allwinner,pull = <0x0>;
  1369. linux,phandle = <0x4e>;
  1370. phandle = <0x4e>;
  1371. };
  1372.  
  1373. dmic@0 {
  1374. allwinner,pins = "PD14", "PD15", "PD16", "PD17", "PD18";
  1375. allwinner,function = "dmic";
  1376. allwinner,muxsel = <0x4>;
  1377. allwinner,driver = <0x1>;
  1378. allwinner,pull = <0x0>;
  1379. linux,phandle = <0x50>;
  1380. phandle = <0x50>;
  1381. };
  1382.  
  1383. dmic_sleep@0 {
  1384. allwinner,pins = "PD14", "PD15", "PD16", "PD17", "PD18";
  1385. allwinner,function = "io_disabled";
  1386. allwinner,muxsel = <0x7>;
  1387. allwinner,driver = <0x1>;
  1388. allwinner,pull = <0x0>;
  1389. linux,phandle = <0x51>;
  1390. phandle = <0x51>;
  1391. };
  1392.  
  1393. ahub_daudio0@0 {
  1394. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1395. allwinner,function = "pcm0";
  1396. allwinner,muxsel = <0x4>;
  1397. allwinner,driver = <0x1>;
  1398. allwinner,pull = <0x0>;
  1399. linux,phandle = <0x53>;
  1400. phandle = <0x53>;
  1401. };
  1402.  
  1403. ahub_daudio0_sleep@0 {
  1404. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1405. allwinner,function = "io_disabled";
  1406. allwinner,muxsel = <0x7>;
  1407. allwinner,driver = <0x1>;
  1408. allwinner,pull = <0x0>;
  1409. linux,phandle = <0x54>;
  1410. phandle = <0x54>;
  1411. };
  1412.  
  1413. ahub_daudio2@0 {
  1414. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1415. allwinner,function = "pcm2";
  1416. allwinner,muxsel = <0x3>;
  1417. allwinner,drive = <0x1>;
  1418. allwinner,pull = <0x0>;
  1419. linux,phandle = <0x55>;
  1420. phandle = <0x55>;
  1421. };
  1422.  
  1423. ahub_daudio2_sleep@0 {
  1424. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1425. allwinner,function = "io_disabled";
  1426. allwinner,muxsel = <0x7>;
  1427. allwinner,drive = <0x1>;
  1428. allwinner,pull = <0x0>;
  1429. linux,phandle = <0x56>;
  1430. phandle = <0x56>;
  1431. };
  1432.  
  1433. ahub_daudio3@0 {
  1434. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1435. allwinner,function = "pcm3";
  1436. allwinner,muxsel = <0x4>;
  1437. allwinner,driver = <0x1>;
  1438. allwinner,pull = <0x0>;
  1439. linux,phandle = <0x57>;
  1440. phandle = <0x57>;
  1441. };
  1442.  
  1443. ahub_daudio3_sleep@0 {
  1444. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1445. allwinner,function = "io_disabled";
  1446. allwinner,muxsel = <0x7>;
  1447. allwinner,driver = <0x1>;
  1448. allwinner,pull = <0x0>;
  1449. linux,phandle = <0x58>;
  1450. phandle = <0x58>;
  1451. };
  1452.  
  1453. csi0@1 {
  1454. allwinner,pins = "PD0", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1455. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7";
  1456. allwinner,function = "io_disabled";
  1457. allwinner,muxsel = <0x7>;
  1458. allwinner,drive = <0x1>;
  1459. allwinner,pull = <0x0>;
  1460. allwinner,data = <0x0>;
  1461. linux,phandle = <0x9e>;
  1462. phandle = <0x9e>;
  1463. };
  1464.  
  1465. csi_mclk0@0 {
  1466. allwinner,pins = "PD1";
  1467. allwinner,pname = "csi_mclk0";
  1468. allwinner,function = "csi_mclk0";
  1469. allwinner,muxsel = <0x4>;
  1470. allwinner,drive = <0x1>;
  1471. allwinner,pull = <0x0>;
  1472. allwinner,data = <0x0>;
  1473. linux,phandle = <0x98>;
  1474. phandle = <0x98>;
  1475. };
  1476.  
  1477. csi_mclk0@1 {
  1478. allwinner,pins = "PD1";
  1479. allwinner,pname = "csi_mclk0";
  1480. allwinner,function = "io_disabled";
  1481. allwinner,muxsel = <0x7>;
  1482. allwinner,drive = <0x1>;
  1483. allwinner,pull = <0x0>;
  1484. allwinner,data = <0x0>;
  1485. linux,phandle = <0x99>;
  1486. phandle = <0x99>;
  1487. };
  1488.  
  1489. csi_cci0@1 {
  1490. allwinner,pins = "PD12", "PD13";
  1491. allwinner,pname = "csi_cci0_sck", "csi_cci0_sda";
  1492. allwinner,function = "io_disabled";
  1493. allwinner,muxsel = <0x7>;
  1494. allwinner,drive = <0x1>;
  1495. allwinner,pull = <0x0>;
  1496. allwinner,data = <0x0>;
  1497. linux,phandle = <0x9c>;
  1498. phandle = <0x9c>;
  1499. };
  1500.  
  1501. scr0@0 {
  1502. allwinner,pins = "PG13", "PG14", "PG10", "PG11", "PG12";
  1503. allwinner,pname = "scr0_rst", "scr0_det", "scr0_vccen", "scr0_sck", "scr0_sda";
  1504. allwinner,function = "sim0";
  1505. allwinner,muxsel = <0x4>;
  1506. allwinner,drive = <0x0>;
  1507. allwinner,pull = <0x1>;
  1508. linux,phandle = <0xab>;
  1509. phandle = <0xab>;
  1510. };
  1511.  
  1512. scr0@1 {
  1513. allwinner,pins = "PG8", "PG9";
  1514. allwinner,pname = "scr0_vppen", "scr0_vppp";
  1515. allwinner,function = "sim0";
  1516. allwinner,muxsel = <0x4>;
  1517. allwinner,drive = <0x0>;
  1518. allwinner,pull = <0x1>;
  1519. linux,phandle = <0xac>;
  1520. phandle = <0xac>;
  1521. };
  1522.  
  1523. scr0@2 {
  1524. allwinner,pins = "PG8", "PG9", "PG10", "PG11", "PG12", "PG13", "PG14";
  1525. allwinner,function = "io_disabled";
  1526. allwinner,muxsel = <0x7>;
  1527. allwinner,drive = <0x0>;
  1528. allwinner,pull = <0x0>;
  1529. linux,phandle = <0xad>;
  1530. phandle = <0xad>;
  1531. };
  1532.  
  1533. scr1@0 {
  1534. allwinner,pins = "PH5", "PH6", "PH2", "PH3", "PH4";
  1535. allwinner,pname = "scr1_rst", "scr1_det", "scr1_vccen", "scr1_sck", "scr1_sda";
  1536. allwinner,function = "sim1";
  1537. allwinner,muxsel = <0x5>;
  1538. allwinner,drive = <0x1>;
  1539. allwinner,pull = <0x1>;
  1540. linux,phandle = <0xaf>;
  1541. phandle = <0xaf>;
  1542. };
  1543.  
  1544. scr1@1 {
  1545. allwinner,pins = "PH0", "PH1";
  1546. allwinner,pname = "scr1_vppen", "scr1_vppp";
  1547. allwinner,function = "sim1";
  1548. allwinner,muxsel = <0x5>;
  1549. allwinner,drive = <0x1>;
  1550. allwinner,pull = <0x1>;
  1551. linux,phandle = <0xb0>;
  1552. phandle = <0xb0>;
  1553. };
  1554.  
  1555. scr1@2 {
  1556. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6";
  1557. allwinner,function = "io_disabled";
  1558. allwinner,muxsel = <0x7>;
  1559. allwinner,drive = <0x1>;
  1560. allwinner,pull = <0x0>;
  1561. linux,phandle = <0xb1>;
  1562. phandle = <0xb1>;
  1563. };
  1564.  
  1565. nand0@2 {
  1566. allwinner,pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1567. allwinner,function = "io_disabled";
  1568. allwinner,muxsel = <0x7>;
  1569. allwinner,drive = <0x1>;
  1570. allwinner,pull = <0x0>;
  1571. linux,phandle = <0xb6>;
  1572. phandle = <0xb6>;
  1573. };
  1574.  
  1575. hdmi@1 {
  1576. allwinner,pins = "PH8", "PH9", "PH10";
  1577. allwinner,function = "io_disabled";
  1578. allwinner,muxsel = <0x7>;
  1579. allwinner,drive = <0x1>;
  1580. allwinner,pull = <0x0>;
  1581. linux,phandle = <0x8d>;
  1582. phandle = <0x8d>;
  1583. };
  1584.  
  1585. hdmi@2 {
  1586. allwinner,pins = "PH10";
  1587. allwinner,function = "cec0";
  1588. allwinner,muxsel = <0x2>;
  1589. allwinner,drive = <0x1>;
  1590. allwinner,pull = <0x0>;
  1591. linux,phandle = <0x8e>;
  1592. phandle = <0x8e>;
  1593. };
  1594.  
  1595. ac200@2 {
  1596. allwinner,pins = "PB0";
  1597. allwinner,function = "ccir_clk";
  1598. allwinner,muxsel = <0x2>;
  1599. allwinner,drive = <0x1>;
  1600. allwinner,pull = <0x0>;
  1601. linux,phandle = <0x94>;
  1602. phandle = <0x94>;
  1603. };
  1604.  
  1605. ac200@3 {
  1606. allwinner,pins = "PB0";
  1607. allwinner,function = "io_disabled";
  1608. allwinner,muxsel = <0x7>;
  1609. allwinner,drive = <0x1>;
  1610. allwinner,pull = <0x0>;
  1611. linux,phandle = <0x95>;
  1612. phandle = <0x95>;
  1613. };
  1614.  
  1615. card0_boot_para@0 {
  1616. linux,phandle = <0xd9>;
  1617. phandle = <0xd9>;
  1618. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1619. allwinner,function = "card0_boot_para";
  1620. allwinner,pname = "sdc_d1", "sdc_d0", "sdc_clk", "sdc_cmd", "sdc_d3", "sdc_d2";
  1621. allwinner,muxsel = <0x2>;
  1622. allwinner,pull = <0x1>;
  1623. allwinner,drive = <0x2>;
  1624. allwinner,data = <0xffffffff>;
  1625. };
  1626.  
  1627. card2_boot_para@0 {
  1628. linux,phandle = <0xda>;
  1629. phandle = <0xda>;
  1630. allwinner,pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  1631. allwinner,function = "card2_boot_para";
  1632. allwinner,pname = "sdc_ds", "sdc_clk", "sdc_cmd", "sdc_d0", "sdc_d1", "sdc_d2", "sdc_d3", "sdc_d4", "sdc_d5", "sdc_d6", "sdc_d7", "sdc_emmc_rst";
  1633. allwinner,muxsel = <0x3>;
  1634. allwinner,pull = <0x1>;
  1635. allwinner,drive = <0x3>;
  1636. allwinner,data = <0xffffffff>;
  1637. };
  1638.  
  1639. uart_para@0 {
  1640. linux,phandle = <0xdc>;
  1641. phandle = <0xdc>;
  1642. allwinner,pins = "PH0", "PH1";
  1643. allwinner,function = "uart_para";
  1644. allwinner,pname = "uart_debug_tx", "uart_debug_rx";
  1645. allwinner,muxsel = <0x2>;
  1646. allwinner,pull = <0x1>;
  1647. allwinner,drive = <0xffffffff>;
  1648. allwinner,data = <0xffffffff>;
  1649. };
  1650.  
  1651. jtag_para@0 {
  1652. linux,phandle = <0xdd>;
  1653. phandle = <0xdd>;
  1654. allwinner,pins = "PD23", "PD24", "PD25", "PD26";
  1655. allwinner,function = "jtag_para";
  1656. allwinner,pname = "jtag_ms", "jtag_ck", "jtag_do", "jtag_di";
  1657. allwinner,muxsel = <0x5>;
  1658. allwinner,pull = <0xffffffff>;
  1659. allwinner,drive = <0xffffffff>;
  1660. allwinner,data = <0xffffffff>;
  1661. };
  1662.  
  1663. gmac0@0 {
  1664. linux,phandle = <0xde>;
  1665. phandle = <0xde>;
  1666. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", "PD12", "PD14", "PD19", "PD20";
  1667. allwinner,function = "gmac0";
  1668. allwinner,pname = "gmac_rxd3", "gmac_rxd2", "gmac_rxd1", "gmac_rxd0", "gmac_rxck", "gmac_rxctl", "gmac_txd3", "gmac_txd2", "gmac_txd1", "gmac_txd0", "gmac_txctl", "gmac_ephyrst", "gmac_mdc", "gmac_mdio";
  1669. allwinner,muxsel = <0x5>;
  1670. allwinner,pull = <0xffffffff>;
  1671. allwinner,drive = <0x3>;
  1672. allwinner,data = <0xffffffff>;
  1673. };
  1674.  
  1675. gmac0@1 {
  1676. linux,phandle = <0xdf>;
  1677. phandle = <0xdf>;
  1678. allwinner,pins = "PD11", "PD13";
  1679. allwinner,function = "gmac0";
  1680. allwinner,pname = "gmac_txck", "gmac_clkin";
  1681. allwinner,muxsel = <0x5>;
  1682. allwinner,pull = <0xffffffff>;
  1683. allwinner,drive = <0x0>;
  1684. allwinner,data = <0xffffffff>;
  1685. };
  1686.  
  1687. twi0@0 {
  1688. linux,phandle = <0xe0>;
  1689. phandle = <0xe0>;
  1690. allwinner,pins = "PD25", "PD26";
  1691. allwinner,function = "twi0";
  1692. allwinner,pname = "twi0_scl", "twi0_sda";
  1693. allwinner,muxsel = <0x2>;
  1694. allwinner,pull = <0xffffffff>;
  1695. allwinner,drive = <0xffffffff>;
  1696. allwinner,data = <0xffffffff>;
  1697. };
  1698.  
  1699. twi0@1 {
  1700. linux,phandle = <0xe1>;
  1701. phandle = <0xe1>;
  1702. allwinner,pins = "PD25", "PD26";
  1703. allwinner,function = "twi0";
  1704. allwinner,pname = "twi0_scl", "twi0_sda";
  1705. allwinner,muxsel = <0x7>;
  1706. allwinner,pull = <0xffffffff>;
  1707. allwinner,drive = <0xffffffff>;
  1708. allwinner,data = <0xffffffff>;
  1709. };
  1710.  
  1711. twi1@0 {
  1712. linux,phandle = <0xe2>;
  1713. phandle = <0xe2>;
  1714. allwinner,pins = "PH5", "PH6";
  1715. allwinner,function = "twi1";
  1716. allwinner,pname = "twi1_scl", "twi1_sda";
  1717. allwinner,muxsel = <0x4>;
  1718. allwinner,pull = <0xffffffff>;
  1719. allwinner,drive = <0xffffffff>;
  1720. allwinner,data = <0xffffffff>;
  1721. };
  1722.  
  1723. twi1@1 {
  1724. linux,phandle = <0xe3>;
  1725. phandle = <0xe3>;
  1726. allwinner,pins = "PH5", "PH6";
  1727. allwinner,function = "twi1";
  1728. allwinner,pname = "twi1_scl", "twi1_sda";
  1729. allwinner,muxsel = <0x7>;
  1730. allwinner,pull = <0xffffffff>;
  1731. allwinner,drive = <0xffffffff>;
  1732. allwinner,data = <0xffffffff>;
  1733. };
  1734.  
  1735. twi2@0 {
  1736. linux,phandle = <0xe4>;
  1737. phandle = <0xe4>;
  1738. allwinner,pins = "PD23", "PD24";
  1739. allwinner,function = "twi2";
  1740. allwinner,pname = "twi2_scl", "twi2_sda";
  1741. allwinner,muxsel = <0x2>;
  1742. allwinner,pull = <0xffffffff>;
  1743. allwinner,drive = <0xffffffff>;
  1744. allwinner,data = <0xffffffff>;
  1745. };
  1746.  
  1747. twi2@1 {
  1748. linux,phandle = <0xe5>;
  1749. phandle = <0xe5>;
  1750. allwinner,pins = "PD23", "PD24";
  1751. allwinner,function = "twi2";
  1752. allwinner,pname = "twi2_scl", "twi2_sda";
  1753. allwinner,muxsel = <0x7>;
  1754. allwinner,pull = <0xffffffff>;
  1755. allwinner,drive = <0xffffffff>;
  1756. allwinner,data = <0xffffffff>;
  1757. };
  1758.  
  1759. twi3@0 {
  1760. linux,phandle = <0xe6>;
  1761. phandle = <0xe6>;
  1762. allwinner,pins = "PB17", "PB18";
  1763. allwinner,function = "twi3";
  1764. allwinner,pname = "twi3_scl", "twi3_sda";
  1765. allwinner,muxsel = <0x2>;
  1766. allwinner,pull = <0xffffffff>;
  1767. allwinner,drive = <0xffffffff>;
  1768. allwinner,data = <0xffffffff>;
  1769. };
  1770.  
  1771. uart0@0 {
  1772. linux,phandle = <0xe7>;
  1773. phandle = <0xe7>;
  1774. allwinner,pins = "PH0", "PH1";
  1775. allwinner,function = "uart0";
  1776. allwinner,pname = "uart0_tx", "uart0_rx";
  1777. allwinner,muxsel = <0x2>;
  1778. allwinner,pull = <0x1>;
  1779. allwinner,drive = <0xffffffff>;
  1780. allwinner,data = <0xffffffff>;
  1781. };
  1782.  
  1783. uart0@1 {
  1784. linux,phandle = <0xe8>;
  1785. phandle = <0xe8>;
  1786. allwinner,pins = "PH0", "PH1";
  1787. allwinner,function = "uart0";
  1788. allwinner,pname = "uart0_tx", "uart0_rx";
  1789. allwinner,muxsel = <0x7>;
  1790. allwinner,pull = <0x1>;
  1791. allwinner,drive = <0xffffffff>;
  1792. allwinner,data = <0xffffffff>;
  1793. };
  1794.  
  1795. uart1@0 {
  1796. linux,phandle = <0xe9>;
  1797. phandle = <0xe9>;
  1798. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  1799. allwinner,function = "uart1";
  1800. allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts";
  1801. allwinner,muxsel = <0x2>;
  1802. allwinner,pull = <0x1>;
  1803. allwinner,drive = <0xffffffff>;
  1804. allwinner,data = <0xffffffff>;
  1805. };
  1806.  
  1807. uart1@1 {
  1808. linux,phandle = <0xea>;
  1809. phandle = <0xea>;
  1810. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  1811. allwinner,function = "uart1";
  1812. allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts";
  1813. allwinner,muxsel = <0x7>;
  1814. allwinner,pull = <0x1>;
  1815. allwinner,drive = <0xffffffff>;
  1816. allwinner,data = <0xffffffff>;
  1817. };
  1818.  
  1819. uart2@0 {
  1820. linux,phandle = <0xeb>;
  1821. phandle = <0xeb>;
  1822. allwinner,pins = "PD19", "PD20", "PD21", "PD22";
  1823. allwinner,function = "uart2";
  1824. allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
  1825. allwinner,muxsel = <0x4>;
  1826. allwinner,pull = <0x1>;
  1827. allwinner,drive = <0xffffffff>;
  1828. allwinner,data = <0xffffffff>;
  1829. };
  1830.  
  1831. uart2@1 {
  1832. linux,phandle = <0xec>;
  1833. phandle = <0xec>;
  1834. allwinner,pins = "PD19", "PD20", "PD21", "PD22";
  1835. allwinner,function = "uart2";
  1836. allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
  1837. allwinner,muxsel = <0x7>;
  1838. allwinner,pull = <0x1>;
  1839. allwinner,drive = <0xffffffff>;
  1840. allwinner,data = <0xffffffff>;
  1841. };
  1842.  
  1843. uart3@0 {
  1844. linux,phandle = <0xed>;
  1845. phandle = <0xed>;
  1846. allwinner,pins = "PD23", "PD24", "PD25", "PD26";
  1847. allwinner,function = "uart3";
  1848. allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts";
  1849. allwinner,muxsel = <0x4>;
  1850. allwinner,pull = <0x1>;
  1851. allwinner,drive = <0xffffffff>;
  1852. allwinner,data = <0xffffffff>;
  1853. };
  1854.  
  1855. uart3@1 {
  1856. linux,phandle = <0xee>;
  1857. phandle = <0xee>;
  1858. allwinner,pins = "PD23", "PD24", "PD25", "PD26";
  1859. allwinner,function = "uart3";
  1860. allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts";
  1861. allwinner,muxsel = <0x7>;
  1862. allwinner,pull = <0x1>;
  1863. allwinner,drive = <0xffffffff>;
  1864. allwinner,data = <0xffffffff>;
  1865. };
  1866.  
  1867. spi0@0 {
  1868. linux,phandle = <0xef>;
  1869. phandle = <0xef>;
  1870. allwinner,pins = "PC5";
  1871. allwinner,function = "spi0";
  1872. allwinner,pname = "spi0_cs0";
  1873. allwinner,muxsel = <0x4>;
  1874. allwinner,pull = <0x1>;
  1875. allwinner,drive = <0xffffffff>;
  1876. allwinner,data = <0xffffffff>;
  1877. };
  1878.  
  1879. spi0@1 {
  1880. linux,phandle = <0xf0>;
  1881. phandle = <0xf0>;
  1882. allwinner,pins = "PC0", "PC2", "PC3";
  1883. allwinner,function = "spi0";
  1884. allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
  1885. allwinner,muxsel = <0x4>;
  1886. allwinner,pull = <0xffffffff>;
  1887. allwinner,drive = <0xffffffff>;
  1888. allwinner,data = <0xffffffff>;
  1889. };
  1890.  
  1891. spi0@2 {
  1892. linux,phandle = <0xf1>;
  1893. phandle = <0xf1>;
  1894. allwinner,pins = "PC5";
  1895. allwinner,function = "spi0";
  1896. allwinner,pname = "spi0_cs0";
  1897. allwinner,muxsel = <0x7>;
  1898. allwinner,pull = <0x1>;
  1899. allwinner,drive = <0xffffffff>;
  1900. allwinner,data = <0xffffffff>;
  1901. };
  1902.  
  1903. spi0@3 {
  1904. linux,phandle = <0xf2>;
  1905. phandle = <0xf2>;
  1906. allwinner,pins = "PC0", "PC2", "PC3";
  1907. allwinner,function = "spi0";
  1908. allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
  1909. allwinner,muxsel = <0x7>;
  1910. allwinner,pull = <0xffffffff>;
  1911. allwinner,drive = <0xffffffff>;
  1912. allwinner,data = <0xffffffff>;
  1913. };
  1914.  
  1915. spi1@0 {
  1916. linux,phandle = <0xf3>;
  1917. phandle = <0xf3>;
  1918. allwinner,pins = "PH3";
  1919. allwinner,function = "spi1";
  1920. allwinner,pname = "spi1_cs0";
  1921. allwinner,muxsel = <0x2>;
  1922. allwinner,pull = <0x1>;
  1923. allwinner,drive = <0xffffffff>;
  1924. allwinner,data = <0xffffffff>;
  1925. };
  1926.  
  1927. spi1@1 {
  1928. linux,phandle = <0xf4>;
  1929. phandle = <0xf4>;
  1930. allwinner,pins = "PH4", "PH5", "PH6";
  1931. allwinner,function = "spi1";
  1932. allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
  1933. allwinner,muxsel = <0x2>;
  1934. allwinner,pull = <0xffffffff>;
  1935. allwinner,drive = <0xffffffff>;
  1936. allwinner,data = <0xffffffff>;
  1937. };
  1938.  
  1939. spi1@2 {
  1940. linux,phandle = <0xf5>;
  1941. phandle = <0xf5>;
  1942. allwinner,pins = "PH3";
  1943. allwinner,function = "spi1";
  1944. allwinner,pname = "spi1_cs0";
  1945. allwinner,muxsel = <0x7>;
  1946. allwinner,pull = <0x1>;
  1947. allwinner,drive = <0xffffffff>;
  1948. allwinner,data = <0xffffffff>;
  1949. };
  1950.  
  1951. spi1@3 {
  1952. linux,phandle = <0xf6>;
  1953. phandle = <0xf6>;
  1954. allwinner,pins = "PH4", "PH5", "PH6";
  1955. allwinner,function = "spi1";
  1956. allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
  1957. allwinner,muxsel = <0x7>;
  1958. allwinner,pull = <0xffffffff>;
  1959. allwinner,drive = <0xffffffff>;
  1960. allwinner,data = <0xffffffff>;
  1961. };
  1962.  
  1963. nand0@0 {
  1964. linux,phandle = <0xf8>;
  1965. phandle = <0xf8>;
  1966. allwinner,pins = "PC0", "PC1", "PC2", "PC4", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  1967. allwinner,function = "nand0";
  1968. allwinner,pname = "nand0_we", "nand0_ale", "nand0_cle", "nand0_nre", "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3", "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7", "nand0_ndqs";
  1969. allwinner,muxsel = <0x2>;
  1970. allwinner,pull = <0x0>;
  1971. allwinner,drive = <0x1>;
  1972. allwinner,data = <0xffffffff>;
  1973. };
  1974.  
  1975. nand0@1 {
  1976. linux,phandle = <0xf9>;
  1977. phandle = <0xf9>;
  1978. allwinner,pins = "PC15", "PC3", "PC5", "PC16";
  1979. allwinner,function = "nand0";
  1980. allwinner,pname = "nand0_ce1", "nand0_ce0", "nand0_rb0", "nand0_rb1";
  1981. allwinner,muxsel = <0x2>;
  1982. allwinner,pull = <0x1>;
  1983. allwinner,drive = <0x1>;
  1984. allwinner,data = <0xffffffff>;
  1985. };
  1986.  
  1987. lcd0@0 {
  1988. linux,phandle = <0xfa>;
  1989. phandle = <0xfa>;
  1990. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
  1991. allwinner,function = "lcd0";
  1992. allwinner,pname = "lcdd0", "lcdd1", "lcdd2", "lcdd3", "lcdd4", "lcdd5", "lcdd6", "lcdd7", "lcdd8", "lcdd9";
  1993. allwinner,muxsel = <0x3>;
  1994. allwinner,pull = <0x0>;
  1995. allwinner,drive = <0xffffffff>;
  1996. allwinner,data = <0xffffffff>;
  1997. };
  1998.  
  1999. lcd0@1 {
  2000. linux,phandle = <0xfb>;
  2001. phandle = <0xfb>;
  2002. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
  2003. allwinner,function = "lcd0";
  2004. allwinner,pname = "lcdd0", "lcdd1", "lcdd2", "lcdd3", "lcdd4", "lcdd5", "lcdd6", "lcdd7", "lcdd8", "lcdd9";
  2005. allwinner,muxsel = <0x7>;
  2006. allwinner,pull = <0x0>;
  2007. allwinner,drive = <0xffffffff>;
  2008. allwinner,data = <0xffffffff>;
  2009. };
  2010.  
  2011. hdmi@0 {
  2012. linux,phandle = <0xfc>;
  2013. phandle = <0xfc>;
  2014. allwinner,pins = "PH8", "PH9", "PH10";
  2015. allwinner,function = "hdmi";
  2016. allwinner,pname = "ddc_scl", "ddc_sda", "cec_io";
  2017. allwinner,muxsel = <0x2>;
  2018. allwinner,pull = <0xffffffff>;
  2019. allwinner,drive = <0x1>;
  2020. allwinner,data = <0xffffffff>;
  2021. };
  2022.  
  2023. ac200@0 {
  2024. linux,phandle = <0xfd>;
  2025. phandle = <0xfd>;
  2026. allwinner,pins = "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11";
  2027. allwinner,function = "ac200";
  2028. allwinner,pname = "ccir_clk", "ccir_de", "ccir_hs", "ccir_vs", "ccir_do0", "ccir_do1", "ccir_do2", "ccir_do3", "ccir_do4", "ccir_do5", "ccir_do6", "ccir_do7";
  2029. allwinner,muxsel = <0x2>;
  2030. allwinner,pull = <0x0>;
  2031. allwinner,drive = <0xffffffff>;
  2032. allwinner,data = <0xffffffff>;
  2033. };
  2034.  
  2035. ac200@1 {
  2036. linux,phandle = <0xfe>;
  2037. phandle = <0xfe>;
  2038. allwinner,pins = "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11";
  2039. allwinner,function = "ac200";
  2040. allwinner,pname = "ccir_de", "ccir_hs", "ccir_vs", "ccir_do0", "ccir_do1", "ccir_do2", "ccir_do3", "ccir_do4", "ccir_do5", "ccir_do6", "ccir_do7";
  2041. allwinner,muxsel = <0x7>;
  2042. allwinner,pull = <0x0>;
  2043. allwinner,drive = <0xffffffff>;
  2044. allwinner,data = <0xffffffff>;
  2045. };
  2046.  
  2047. pwm0@0 {
  2048. linux,phandle = <0xff>;
  2049. phandle = <0xff>;
  2050. allwinner,pins = "PD22";
  2051. allwinner,function = "pwm0";
  2052. allwinner,pname = "pwm_positive";
  2053. allwinner,muxsel = <0x2>;
  2054. allwinner,pull = <0x0>;
  2055. allwinner,drive = <0xffffffff>;
  2056. allwinner,data = <0xffffffff>;
  2057. };
  2058.  
  2059. pwm0@1 {
  2060. linux,phandle = <0x100>;
  2061. phandle = <0x100>;
  2062. allwinner,pins = "PD22";
  2063. allwinner,function = "pwm0";
  2064. allwinner,pname = "pwm_positive";
  2065. allwinner,muxsel = <0x7>;
  2066. allwinner,pull = <0x0>;
  2067. allwinner,drive = <0xffffffff>;
  2068. allwinner,data = <0xffffffff>;
  2069. };
  2070.  
  2071. pwm1@0 {
  2072. linux,phandle = <0x101>;
  2073. phandle = <0x101>;
  2074. allwinner,pins = "PB19";
  2075. allwinner,function = "pwm1";
  2076. allwinner,pname = "pwm_positive";
  2077. allwinner,muxsel = <0x2>;
  2078. allwinner,pull = <0x0>;
  2079. allwinner,drive = <0xffffffff>;
  2080. allwinner,data = <0xffffffff>;
  2081. };
  2082.  
  2083. pwm1@1 {
  2084. linux,phandle = <0x102>;
  2085. phandle = <0x102>;
  2086. allwinner,pins = "PB19";
  2087. allwinner,function = "pwm1";
  2088. allwinner,pname = "pwm_positive";
  2089. allwinner,muxsel = <0x7>;
  2090. allwinner,pull = <0x0>;
  2091. allwinner,drive = <0xffffffff>;
  2092. allwinner,data = <0xffffffff>;
  2093. };
  2094.  
  2095. csi0@0 {
  2096. linux,phandle = <0x105>;
  2097. phandle = <0x105>;
  2098. allwinner,pins = "PD0", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  2099. allwinner,function = "csi0";
  2100. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7";
  2101. allwinner,muxsel = <0x4>;
  2102. allwinner,pull = <0xffffffff>;
  2103. allwinner,drive = <0xffffffff>;
  2104. allwinner,data = <0xffffffff>;
  2105. };
  2106.  
  2107. csi_cci0@0 {
  2108. linux,phandle = <0x106>;
  2109. phandle = <0x106>;
  2110. allwinner,pins = "PD12", "PD13";
  2111. allwinner,function = "csi_cci0";
  2112. allwinner,pname = "csi_cci0_sck", "csi_cci0_sda";
  2113. allwinner,muxsel = <0x4>;
  2114. allwinner,pull = <0xffffffff>;
  2115. allwinner,drive = <0xffffffff>;
  2116. allwinner,data = <0xffffffff>;
  2117. };
  2118.  
  2119. sdc0@0 {
  2120. linux,phandle = <0x107>;
  2121. phandle = <0x107>;
  2122. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  2123. allwinner,function = "sdc0";
  2124. allwinner,pname = "sdc0_d1", "sdc0_d0", "sdc0_clk", "sdc0_cmd", "sdc0_d3", "sdc0_d2";
  2125. allwinner,muxsel = <0x2>;
  2126. allwinner,pull = <0x1>;
  2127. allwinner,drive = <0x2>;
  2128. allwinner,data = <0xffffffff>;
  2129. };
  2130.  
  2131. sdc1@0 {
  2132. linux,phandle = <0x108>;
  2133. phandle = <0x108>;
  2134. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  2135. allwinner,function = "sdc1";
  2136. allwinner,pname = "sdc1_clk", "sdc1_cmd", "sdc1_d0", "sdc1_d1", "sdc1_d2", "sdc1_d3";
  2137. allwinner,muxsel = <0x2>;
  2138. allwinner,pull = <0x1>;
  2139. allwinner,drive = <0x3>;
  2140. allwinner,data = <0xffffffff>;
  2141. };
  2142.  
  2143. sdc2@0 {
  2144. linux,phandle = <0x109>;
  2145. phandle = <0x109>;
  2146. allwinner,pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  2147. allwinner,function = "sdc2";
  2148. allwinner,pname = "sdc2_ds", "sdc2_clk", "sdc2_cmd", "sdc2_d0", "sdc2_d1", "sdc2_d2", "sdc2_d3", "sdc2_d4", "sdc2_d5", "sdc2_d6", "sdc2_d7", "sdc2_emmc_rst";
  2149. allwinner,muxsel = <0x3>;
  2150. allwinner,pull = <0x1>;
  2151. allwinner,drive = <0x3>;
  2152. allwinner,data = <0xffffffff>;
  2153. };
  2154.  
  2155. Vdevice@0 {
  2156. linux,phandle = <0x10d>;
  2157. phandle = <0x10d>;
  2158. allwinner,pins = "PH9", "PH10";
  2159. allwinner,function = "Vdevice";
  2160. allwinner,pname = "Vdevice_0", "Vdevice_1";
  2161. allwinner,muxsel = <0x5>;
  2162. allwinner,pull = <0x1>;
  2163. allwinner,drive = <0x2>;
  2164. allwinner,data = <0xffffffff>;
  2165. };
  2166. };
  2167.  
  2168. dma-controller@03002000 {
  2169. compatible = "allwinner,sun50i-dma";
  2170. reg = <0x0 0x3002000 0x0 0x1000>;
  2171. interrupts = <0x0 0x2b 0x4>;
  2172. clocks = <0xc>;
  2173. #dma-cells = <0x1>;
  2174. };
  2175.  
  2176. mbus-controller@04002000 {
  2177. compatible = "allwinner,sun50i-mbus";
  2178. reg = <0x0 0x4002000 0x0 0x1000>;
  2179. #mbus-cells = <0x1>;
  2180. };
  2181.  
  2182. arisc {
  2183. compatible = "allwinner,sunxi-arisc";
  2184. #address-cells = <0x2>;
  2185. #size-cells = <0x2>;
  2186. clocks = <0xd 0xe 0x7 0x2>;
  2187. clock-names = "losc", "iosc", "hosc", "pll_periph0";
  2188. powchk_used = <0x0>;
  2189. power_reg = <0x2309621>;
  2190. system_power = <0x32>;
  2191. };
  2192.  
  2193. arisc_space {
  2194. compatible = "allwinner,arisc_space";
  2195. space1 = <0x48040000 0x0 0x14000>;
  2196. space2 = <0x48100000 0x18000 0x4000>;
  2197. space3 = <0x48104000 0x0 0x1000>;
  2198. space4 = <0x48105000 0x0 0x1000>;
  2199. };
  2200.  
  2201. standby_space {
  2202. compatible = "allwinner,standby_space";
  2203. space1 = <0x40020000 0x0 0x800>;
  2204. };
  2205.  
  2206. msgbox@03003000 {
  2207. compatible = "allwinner,msgbox";
  2208. clocks = <0xf>;
  2209. clock-names = "clk_msgbox";
  2210. reg = <0x0 0x3003000 0x0 0x1000>;
  2211. interrupts = <0x0 0x27 0x1>;
  2212. status = "okay";
  2213. };
  2214.  
  2215. hwspinlock@3004000 {
  2216. compatible = "allwinner,sunxi-hwspinlock";
  2217. clocks = <0x10 0x11>;
  2218. clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
  2219. reg = <0x0 0x3004000 0x0 0x1000>;
  2220. num-locks = <0x8>;
  2221. status = "okay";
  2222. };
  2223.  
  2224. s_cir@07040000 {
  2225. compatible = "allwinner,s_cir";
  2226. reg = <0x0 0x7040000 0x0 0x400>;
  2227. interrupts = <0x0 0x6d 0x4>;
  2228. pinctrl-names = "default";
  2229. pinctrl-0 = <0x12>;
  2230. clocks = <0x7 0x13>;
  2231. supply = [00];
  2232. supply_vol = [00];
  2233. status = "okay";
  2234. device_type = "s_cir0";
  2235. ir_protocol_used = <0x0>;
  2236. ir_power_key_code0 = <0x57>;
  2237. ir_addr_code0 = <0x9f00>;
  2238. ir_power_key_code1 = <0x1a>;
  2239. ir_addr_code1 = <0xfb04>;
  2240. ir_power_key_code2 = <0x14>;
  2241. ir_addr_code2 = <0x7f80>;
  2242. ir_power_key_code3 = <0x15>;
  2243. ir_addr_code3 = <0x7f80>;
  2244. ir_power_key_code4 = <0xb>;
  2245. ir_addr_code4 = <0xf708>;
  2246. ir_power_key_code5 = <0x3>;
  2247. ir_addr_code5 = <0xef>;
  2248. ir_power_key_code6 = <0xdc>;
  2249. ir_addr_code6 = <0x4cb3>;
  2250. ir_power_key_code7 = <0xa>;
  2251. ir_addr_code7 = <0x7748>;
  2252. ir_power_key_code8 = <0x45>;
  2253. ir_addr_code8 = <0xbd02>;
  2254. ir_power_key_code9 = <0x4d>;
  2255. ir_addr_code9 = <0xde21>;
  2256. ir_power_key_code10 = <0x18>;
  2257. ir_addr_code10 = <0xfe01>;
  2258. ir_power_key_code11 = <0x18>;
  2259. ir_addr_code11 = <0xff00>;
  2260. ir_power_key_code12 = <0x4d>;
  2261. ir_addr_code12 = <0xff40>;
  2262. ir_power_key_code13 = <0x88>;
  2263. ir_addr_code13 = <0xdd22>;
  2264. ir_power_key_code14 = <0xd>;
  2265. ir_addr_code14 = <0xbc00>;
  2266. ir_power_key_code15 = <0xd>;
  2267. ir_addr_code15 = <0xfc00>;
  2268. rc5_ir_power_key_code0 = <0x1>;
  2269. rc5_ir_addr_code0 = <0x4>;
  2270. };
  2271.  
  2272. s_uart@7080000 {
  2273. compatible = "allwinner,s_uart";
  2274. reg = <0x0 0x7080000 0x0 0xd0>;
  2275. interrupts = <0x0 0x6a 0x4>;
  2276. pinctrl-names = "default";
  2277. status = "disabled";
  2278. device_type = "s_uart0";
  2279. pinctrl-0 = <0x10a>;
  2280. };
  2281.  
  2282. s_twi@1f03400 {
  2283. compatible = "allwinner,s_twi";
  2284. reg = <0x0 0x1f02400 0x0 0x20>;
  2285. interrupts = <0x0 0x2c 0x4>;
  2286. pinctrl-names = "default";
  2287. pinctrl-0 = <0x15>;
  2288. status = "okay";
  2289. };
  2290.  
  2291. s_jtag0 {
  2292. compatible = "allwinner,s_jtag";
  2293. pinctrl-names = "default";
  2294. status = "disabled";
  2295. device_type = "s_jtag0";
  2296. pinctrl-0 = <0x10c>;
  2297. };
  2298.  
  2299. box_start_os0 {
  2300. compatible = "allwinner,box_start_os";
  2301. start_type = <0x1>;
  2302. irkey_used = <0x1>;
  2303. pmukey_used = <0x1>;
  2304. pmukey_num = <0x0>;
  2305. led_power = <0x0>;
  2306. led_state = <0x0>;
  2307. status = "okay";
  2308. device_type = "box_start_os";
  2309. };
  2310.  
  2311. timer@03009000 {
  2312. compatible = "allwinner,sunxi-timer";
  2313. device_type = "timer";
  2314. reg = <0x0 0x3009000 0x0 0x400>;
  2315. interrupts = <0x0 0x30 0x4>;
  2316. clock-frequency = <0x16e3600>;
  2317. timer-prescale = <0x10>;
  2318. };
  2319.  
  2320. rtc@07000000 {
  2321. compatible = "allwinner,sun50iw6-rtc";
  2322. device_type = "rtc";
  2323. reg = <0x0 0x7000000 0x0 0x200>;
  2324. interrupts = <0x0 0x65 0x4>;
  2325. gpr_offset = <0x100>;
  2326. gpr_len = <0x8>;
  2327. };
  2328.  
  2329. watchdog@030090a0 {
  2330. compatible = "allwinner,sun50i-wdt";
  2331. reg = <0x0 0x30090a0 0x0 0x20>;
  2332. interrupts = <0x0 0x32 0x4>;
  2333. };
  2334.  
  2335. ve@01c0e000 {
  2336. compatible = "allwinner,sunxi-cedar-ve";
  2337. reg = <0x0 0x1c0e000 0x0 0x1000 0x0 0x3000000 0x0 0x10 0x0 0x3001000 0x0 0x1000>;
  2338. interrupts = <0x0 0x59 0x4>;
  2339. clocks = <0x17 0x18>;
  2340. iommus = <0x19 0x3 0x1>;
  2341. };
  2342.  
  2343. vp9@01c00000 {
  2344. compatible = "allwinner,sunxi-google-vp9";
  2345. reg = <0x0 0x1c00000 0x0 0x1000 0x0 0x3000000 0x0 0x10 0x0 0x3001000 0x0 0x1000>;
  2346. interrupts = <0x0 0x5a 0x4>;
  2347. clocks = <0x17 0x1a>;
  2348. #clocks = <0x1b 0x1a>;
  2349. iommus = <0x19 0x5 0x1>;
  2350. };
  2351.  
  2352. uart@05000000 {
  2353. compatible = "allwinner,sun50i-uart";
  2354. device_type = "uart0";
  2355. reg = <0x0 0x5000000 0x0 0x400>;
  2356. interrupts = <0x0 0x0 0x4>;
  2357. clocks = <0x1c>;
  2358. pinctrl-names = "default", "sleep";
  2359. uart0_port = <0x0>;
  2360. uart0_type = <0x2>;
  2361. status = "okay";
  2362. pinctrl-0 = <0xe7>;
  2363. pinctrl-1 = <0xe8>;
  2364. };
  2365.  
  2366. uart@05000400 {
  2367. compatible = "allwinner,sun50i-uart";
  2368. device_type = "uart1";
  2369. reg = <0x0 0x5000400 0x0 0x400>;
  2370. interrupts = <0x0 0x1 0x4>;
  2371. clocks = <0x1f>;
  2372. pinctrl-names = "default", "sleep";
  2373. uart1_port = <0x1>;
  2374. uart1_type = <0x4>;
  2375. status = "okay";
  2376. pinctrl-0 = <0xe9>;
  2377. uart1_bt = <0x1>;
  2378. pinctrl-1 = <0xea>;
  2379. };
  2380.  
  2381. uart@05000800 {
  2382. compatible = "allwinner,sun50i-uart";
  2383. device_type = "uart2";
  2384. reg = <0x0 0x5000800 0x0 0x400>;
  2385. interrupts = <0x0 0x2 0x4>;
  2386. clocks = <0x22>;
  2387. pinctrl-names = "default", "sleep";
  2388. uart2_port = <0x2>;
  2389. uart2_type = <0x4>;
  2390. status = "disabled";
  2391. pinctrl-0 = <0xeb>;
  2392. pinctrl-1 = <0xec>;
  2393. };
  2394.  
  2395. uart@05000c00 {
  2396. compatible = "allwinner,sun50i-uart";
  2397. device_type = "uart3";
  2398. reg = <0x0 0x5000c00 0x0 0x400>;
  2399. interrupts = <0x0 0x3 0x4>;
  2400. clocks = <0x25>;
  2401. pinctrl-names = "default", "sleep";
  2402. uart3_port = <0x3>;
  2403. uart3_type = <0x2>;
  2404. status = "okay";
  2405. pinctrl-0 = <0xed>;
  2406. pinctrl-1 = <0xee>;
  2407. };
  2408.  
  2409. twi@0x05002000 {
  2410. #address-cells = <0x1>;
  2411. #size-cells = <0x0>;
  2412. compatible = "allwinner,sun50i-twi";
  2413. device_type = "twi0";
  2414. reg = <0x0 0x5002000 0x0 0x400>;
  2415. interrupts = <0x0 0x4 0x4>;
  2416. clocks = <0x28>;
  2417. clock-frequency = <0x61a80>;
  2418. pinctrl-names = "default", "sleep";
  2419. status = "disabled";
  2420. pinctrl-0 = <0xe0>;
  2421. pinctrl-1 = <0xe1>;
  2422. };
  2423.  
  2424. twi@0x05002400 {
  2425. #address-cells = <0x1>;
  2426. #size-cells = <0x0>;
  2427. compatible = "allwinner,sun50i-twi";
  2428. device_type = "twi1";
  2429. reg = <0x0 0x5002400 0x0 0x400>;
  2430. interrupts = <0x0 0x5 0x4>;
  2431. clocks = <0x2b>;
  2432. clock-frequency = <0x30d40>;
  2433. pinctrl-names = "default", "sleep";
  2434. status = "okay";
  2435. pinctrl-0 = <0xe2>;
  2436. pinctrl-1 = <0xe3>;
  2437. };
  2438.  
  2439. twi@0x05002800 {
  2440. #address-cells = <0x1>;
  2441. #size-cells = <0x0>;
  2442. compatible = "allwinner,sun50i-twi";
  2443. device_type = "twi2";
  2444. reg = <0x0 0x5002800 0x0 0x400>;
  2445. interrupts = <0x0 0x6 0x4>;
  2446. clocks = <0x2e>;
  2447. clock-frequency = <0x30d40>;
  2448. pinctrl-names = "default", "sleep";
  2449. status = "disabled";
  2450. pinctrl-0 = <0xe4>;
  2451. pinctrl-1 = <0xe5>;
  2452. };
  2453.  
  2454. twi@0x05002c00 {
  2455. #address-cells = <0x1>;
  2456. #size-cells = <0x0>;
  2457. compatible = "allwinner,sun50i-twi";
  2458. device_type = "twi3";
  2459. reg = <0x0 0x5002c00 0x0 0x400>;
  2460. interrupts = <0x0 0x7 0x4>;
  2461. clocks = <0x31>;
  2462. clock-frequency = <0x30d40>;
  2463. pinctrl-names = "default", "sleep";
  2464. pinctrl-1 = <0x33>;
  2465. status = "okay";
  2466. pinctrl-0 = <0xe6>;
  2467. };
  2468.  
  2469. usbc0@0 {
  2470. device_type = "usbc0";
  2471. compatible = "allwinner,sunxi-otg-manager";
  2472. usb_port_type = <0x2>;
  2473. usb_detect_type = <0x1>;
  2474. usb_host_init_state = <0x1>;
  2475. usb_regulator_io = "nocare";
  2476. usb_wakeup_suspend = <0x0>;
  2477. usb_luns = <0x3>;
  2478. usb_serial_unique = <0x0>;
  2479. usb_serial_number = "20080411";
  2480. rndis_wceis = <0x1>;
  2481. status = "okay";
  2482. usb_detect_mode = <0x0>;
  2483. usb_id_gpio;
  2484. usb_det_vbus_gpio;
  2485. usb_drv_vbus_gpio = <0xd8 0xb 0x5 0x1 0x0 0xffffffff 0x1>;
  2486. };
  2487.  
  2488. udc-controller@0x05100000 {
  2489. compatible = "allwinner,sunxi-udc";
  2490. reg = <0x0 0x5100000 0x0 0x1000 0x0 0x0 0x0 0x100>;
  2491. interrupts = <0x0 0x17 0x4>;
  2492. clocks = <0x34 0x35>;
  2493. status = "okay";
  2494. };
  2495.  
  2496. ehci0-controller@0x05101000 {
  2497. compatible = "allwinner,sunxi-ehci0";
  2498. reg = <0x0 0x5101000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2499. interrupts = <0x0 0x18 0x4>;
  2500. clocks = <0x34 0x36>;
  2501. hci_ctrl_no = <0x0>;
  2502. status = "okay";
  2503. };
  2504.  
  2505. ohci0-controller@0x05101400 {
  2506. compatible = "allwinner,sunxi-ohci0";
  2507. reg = <0x0 0x5101000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2508. interrupts = <0x0 0x19 0x4>;
  2509. clocks = <0x34 0x37 0x38 0x39 0x7 0xd>;
  2510. hci_ctrl_no = <0x0>;
  2511. status = "okay";
  2512. };
  2513.  
  2514. usbc1@0 {
  2515. device_type = "usbc1";
  2516. usb_host_init_state = <0x1>;
  2517. usb_regulator_io = "nocare";
  2518. usb_wakeup_suspend = <0x0>;
  2519. status = "okay";
  2520. usb_drv_vbus_gpio = <0xd8 0xb 0x5 0x1 0x0 0xffffffff 0x1>;
  2521. };
  2522.  
  2523. xhci-controller@0x05200000 {
  2524. compatible = "allwinner,sunxi-xhci";
  2525. reg = <0x0 0x5200000 0x0 0xfffff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2526. interrupts = <0x0 0x1a 0x4>;
  2527. clocks = <0x3a 0x3b>;
  2528. hci_ctrl_no = <0x1>;
  2529. status = "okay";
  2530. };
  2531.  
  2532. usbc2@0 {
  2533. device_type = "usbc2";
  2534. usb_host_init_state = <0x1>;
  2535. usb_regulator_io = "nocare";
  2536. usb_wakeup_suspend = <0x0>;
  2537. status = "disabled";
  2538. usb_drv_vbus_gpio;
  2539. };
  2540.  
  2541. ehci3-controller@0x05311000 {
  2542. compatible = "allwinner,sunxi-ehci3";
  2543. reg = <0x0 0x5311000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2544. interrupts = <0x0 0x1c 0x4>;
  2545. clocks = <0x3c 0x3d 0x3e 0x3e 0x3f>;
  2546. hci_ctrl_no = <0x3>;
  2547. status = "okay";
  2548. };
  2549.  
  2550. ohci3-controller@0x05311400 {
  2551. compatible = "allwinner,sunxi-ohci3";
  2552. reg = <0x0 0x5311000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2553. interrupts = <0x0 0x1d 0x4>;
  2554. clocks = <0x3c 0x40 0x41 0x39 0x7 0xd>;
  2555. hci_ctrl_no = <0x3>;
  2556. status = "okay";
  2557. };
  2558.  
  2559. ac200_codec {
  2560. compatible = "allwinner,ac200_codec";
  2561. status = "okay";
  2562. device_type = "ac200_codec";
  2563. gpio-spk = <0xd8 0xb 0x6 0x1 0x1 0xffffffff 0xffffffff>;
  2564. };
  2565.  
  2566. daudio@0x05090000 {
  2567. compatible = "allwinner,sunxi-daudio";
  2568. reg = <0x0 0x5090000 0x0 0x74>;
  2569. clocks = <0x4 0x42>;
  2570. pinctrl-names = "default", "sleep";
  2571. pinctrl-0 = <0x43>;
  2572. pinctrl-1 = <0x44>;
  2573. pcm_lrck_period = <0x20>;
  2574. slot_width_select = <0x20>;
  2575. daudio_master = <0x4>;
  2576. audio_format = <0x1>;
  2577. signal_inversion = <0x1>;
  2578. tdm_config = <0x1>;
  2579. frametype = <0x0>;
  2580. tdm_num = <0x0>;
  2581. mclk_div = <0x0>;
  2582. status = "disabled";
  2583. linux,phandle = <0x59>;
  2584. phandle = <0x59>;
  2585. device_type = "daudio0";
  2586. };
  2587.  
  2588. daudio@0x05091000 {
  2589. compatible = "allwinner,sunxi-tdmhdmi";
  2590. reg = <0x0 0x5091000 0x0 0x74>;
  2591. clocks = <0x4 0x45>;
  2592. status = "okay";
  2593. linux,phandle = <0x5b>;
  2594. phandle = <0x5b>;
  2595. device_type = "audiohdmi";
  2596. };
  2597.  
  2598. daudio@0x05092000 {
  2599. compatible = "allwinner,sunxi-daudio";
  2600. reg = <0x0 0x5092000 0x0 0x74>;
  2601. clocks = <0x4 0x46>;
  2602. pinctrl-names = "default", "sleep";
  2603. pinctrl-0 = <0x47>;
  2604. pinctrl-1 = <0x48>;
  2605. pcm_lrck_period = <0x40>;
  2606. slot_width_select = <0x20>;
  2607. daudio_master = <0x4>;
  2608. audio_format = <0x4>;
  2609. signal_inversion = <0x3>;
  2610. tdm_config = <0x1>;
  2611. frametype = <0x0>;
  2612. tdm_num = <0x2>;
  2613. mclk_div = <0x1>;
  2614. status = "okay";
  2615. linux,phandle = <0x5d>;
  2616. phandle = <0x5d>;
  2617. device_type = "daudio2";
  2618. };
  2619.  
  2620. daudio@0x0508f000 {
  2621. compatible = "allwinner,sunxi-daudio";
  2622. reg = <0x0 0x508f000 0x0 0x74>;
  2623. clocks = <0x4 0x49>;
  2624. pinctrl-names = "default", "sleep";
  2625. pinctrl-0 = <0x4a>;
  2626. pinctrl-1 = <0x4b>;
  2627. pcm_lrck_period = <0x20>;
  2628. slot_width_select = <0x20>;
  2629. daudio_master = <0x4>;
  2630. audio_format = <0x1>;
  2631. signal_inversion = <0x1>;
  2632. tdm_config = <0x1>;
  2633. frametype = <0x0>;
  2634. tdm_num = <0x3>;
  2635. mclk_div = <0x1>;
  2636. status = "okay";
  2637. linux,phandle = <0x5f>;
  2638. phandle = <0x5f>;
  2639. device_type = "daudio3";
  2640. };
  2641.  
  2642. spdif-controller@0x05093000 {
  2643. compatible = "allwinner,sunxi-spdif";
  2644. reg = <0x0 0x5093000 0x0 0x40>;
  2645. clocks = <0x4 0x4c>;
  2646. pinctrl-names = "default", "sleep";
  2647. pinctrl-0 = <0x4d>;
  2648. pinctrl-1 = <0x4e>;
  2649. status = "disabled";
  2650. linux,phandle = <0x61>;
  2651. phandle = <0x61>;
  2652. device_type = "spdif";
  2653. };
  2654.  
  2655. dmic-controller@0x05095000 {
  2656. compatible = "allwinner,sunxi-dmic";
  2657. reg = <0x0 0x5095000 0x0 0x50>;
  2658. clocks = <0x4 0x4f>;
  2659. pinctrl-names = "default", "sleep";
  2660. pinctrl-0 = <0x50>;
  2661. pinctrl-1 = <0x51>;
  2662. status = "disabled";
  2663. linux,phandle = <0x62>;
  2664. phandle = <0x62>;
  2665. device_type = "dmic";
  2666. };
  2667.  
  2668. cpudai0-controller@0x05097000 {
  2669. compatible = "allwinner,sunxi-ahub-cpudai";
  2670. reg = <0x0 0x5097000 0x0 0xadf>;
  2671. id = <0x0>;
  2672. status = "okay";
  2673. linux,phandle = <0x63>;
  2674. phandle = <0x63>;
  2675. };
  2676.  
  2677. cpudai1-controller@0x05097000 {
  2678. compatible = "allwinner,sunxi-ahub-cpudai";
  2679. reg = <0x0 0x5097000 0x0 0xadf>;
  2680. id = <0x1>;
  2681. status = "okay";
  2682. linux,phandle = <0x64>;
  2683. phandle = <0x64>;
  2684. };
  2685.  
  2686. cpudai2-controller@0x05097000 {
  2687. compatible = "allwinner,sunxi-ahub-cpudai";
  2688. reg = <0x0 0x5097000 0x0 0xadf>;
  2689. id = <0x2>;
  2690. status = "okay";
  2691. linux,phandle = <0x65>;
  2692. phandle = <0x65>;
  2693. };
  2694.  
  2695. ahub_codec@0x05097000 {
  2696. compatible = "allwinner,sunxi-ahub";
  2697. reg = <0x0 0x5097000 0x0 0xadf>;
  2698. clocks = <0x4 0x52>;
  2699. status = "okay";
  2700. linux,phandle = <0x66>;
  2701. phandle = <0x66>;
  2702. };
  2703.  
  2704. ahub_daudio0@0x05097000 {
  2705. compatible = "allwinner,sunxi-ahub-daudio";
  2706. reg = <0x0 0x5097000 0x0 0xadf>;
  2707. clocks = <0x4 0x52>;
  2708. pinctrl-names = "default", "sleep";
  2709. pinctrl-0 = <0x53>;
  2710. pinctrl-1 = <0x54>;
  2711. pinconfig = <0x1>;
  2712. frametype = <0x0>;
  2713. pcm_lrck_period = <0x20>;
  2714. slot_width_select = <0x20>;
  2715. daudio_master = <0x4>;
  2716. audio_format = <0x1>;
  2717. signal_inversion = <0x1>;
  2718. tdm_config = <0x1>;
  2719. tdm_num = <0x0>;
  2720. mclk_div = <0x0>;
  2721. status = "disable";
  2722. linux,phandle = <0x5a>;
  2723. phandle = <0x5a>;
  2724. };
  2725.  
  2726. ahub_daudio1@0x05097000 {
  2727. compatible = "allwinner,sunxi-ahub-daudio";
  2728. reg = <0x0 0x5097000 0x0 0xadf>;
  2729. clocks = <0x4 0x52>;
  2730. pinconfig = <0x0>;
  2731. frametype = <0x0>;
  2732. pcm_lrck_period = <0x20>;
  2733. slot_width_select = <0x20>;
  2734. daudio_master = <0x4>;
  2735. audio_format = <0x1>;
  2736. signal_inversion = <0x1>;
  2737. tdm_config = <0x1>;
  2738. tdm_num = <0x1>;
  2739. mclk_div = <0x0>;
  2740. status = "okay";
  2741. linux,phandle = <0x5c>;
  2742. phandle = <0x5c>;
  2743. };
  2744.  
  2745. ahub_daudio2@0x05097000 {
  2746. compatible = "allwinner,sunxi-ahub-daudio";
  2747. reg = <0x0 0x5097000 0x0 0xadf>;
  2748. clocks = <0x4 0x52>;
  2749. pinctrl-names = "default", "sleep";
  2750. pinctrl-0 = <0x55>;
  2751. pinctrl-1 = <0x56>;
  2752. pinconfig = <0x1>;
  2753. frametype = <0x0>;
  2754. pcm_lrck_period = <0x20>;
  2755. slot_width_select = <0x20>;
  2756. daudio_master = <0x4>;
  2757. audio_format = <0x1>;
  2758. signal_inversion = <0x1>;
  2759. tdm_config = <0x1>;
  2760. tdm_num = <0x2>;
  2761. mclk_div = <0x0>;
  2762. status = "okay";
  2763. linux,phandle = <0x5e>;
  2764. phandle = <0x5e>;
  2765. };
  2766.  
  2767. ahub_daudio3@0x05097000 {
  2768. compatible = "allwinner,sunxi-ahub-daudio";
  2769. reg = <0x0 0x5097000 0x0 0xadf>;
  2770. clocks = <0x4 0x52>;
  2771. pinctrl-names = "default", "sleep";
  2772. pinctrl-0 = <0x57>;
  2773. pinctrl-1 = <0x58>;
  2774. pinconfig = <0x1>;
  2775. frametype = <0x0>;
  2776. pcm_lrck_period = <0x20>;
  2777. slot_width_select = <0x20>;
  2778. daudio_master = <0x4>;
  2779. audio_format = <0x1>;
  2780. signal_inversion = <0x1>;
  2781. tdm_config = <0x1>;
  2782. tdm_num = <0x3>;
  2783. mclk_div = <0x4>;
  2784. status = "okay";
  2785. linux,phandle = <0x60>;
  2786. phandle = <0x60>;
  2787. };
  2788.  
  2789. sound@0 {
  2790. compatible = "allwinner,sunxi-daudio0-machine";
  2791. sunxi,daudio-controller = <0x59>;
  2792. sunxi,cpudai-controller = <0x5a>;
  2793. status = "disabled";
  2794. device_type = "snddaudio0";
  2795. };
  2796.  
  2797. sound@1 {
  2798. compatible = "allwinner,sunxi-hdmi-machine";
  2799. sunxi,hdmi-controller = <0x5b>;
  2800. sunxi,cpudai-controller = <0x5c>;
  2801. status = "okay";
  2802. device_type = "sndhdmi";
  2803. };
  2804.  
  2805. sound@2 {
  2806. compatible = "allwinner,sunxi-daudio2-machine";
  2807. sunxi,daudio-controller = <0x5d>;
  2808. sunxi,cpudai-controller = <0x5e>;
  2809. status = "okay";
  2810. device_type = "snddaudio2";
  2811. };
  2812.  
  2813. sound@3 {
  2814. compatible = "allwinner,sunxi-daudio3-machine";
  2815. sunxi,daudio-controller = <0x5f>;
  2816. sunxi,cpudai-controller = <0x60>;
  2817. sunxi,snddaudio-codec = "acx00-codec";
  2818. sunxi,snddaudio-codec-dai = "acx00-dai";
  2819. status = "okay";
  2820. device_type = "snddaudio3";
  2821. };
  2822.  
  2823. sound@4 {
  2824. compatible = "allwinner,sunxi-spdif-machine";
  2825. sunxi,spdif-controller = <0x61>;
  2826. status = "disabled";
  2827. device_type = "sndspdif";
  2828. };
  2829.  
  2830. sound@5 {
  2831. compatible = "allwinner,sunxi-dmic-machine";
  2832. sunxi,dmic-controller = <0x62>;
  2833. status = "disabled";
  2834. device_type = "snddmic";
  2835. };
  2836.  
  2837. sound@6 {
  2838. compatible = "allwinner,sunxi-ahub-machine";
  2839. sunxi,cpudai-controller0 = <0x63>;
  2840. sunxi,cpudai-controller1 = <0x64>;
  2841. sunxi,cpudai-controller2 = <0x65>;
  2842. sunxi,audio-codec = <0x66>;
  2843. status = "okay";
  2844. };
  2845.  
  2846. spi@05010000 {
  2847. #address-cells = <0x1>;
  2848. #size-cells = <0x0>;
  2849. compatible = "allwinner,sun50i-spi";
  2850. device_type = "spi0";
  2851. reg = <0x0 0x5010000 0x0 0x1000>;
  2852. interrupts = <0x0 0xa 0x4>;
  2853. clocks = <0x2 0x67>;
  2854. clock-frequency = <0x5f5e100>;
  2855. pinctrl-names = "default", "sleep";
  2856. spi0_cs_number = <0x1>;
  2857. spi0_cs_bitmap = <0x1>;
  2858. status = "okay";
  2859. pinctrl-0 = <0xef 0xf0>;
  2860. pinctrl-1 = <0xf1 0xf2>;
  2861.  
  2862. spi_board0 {
  2863. device_type = "spi_board0";
  2864. compatible = "spidev";
  2865. spi-max-frequency = <0x124f80>;
  2866. reg = <0x0>;
  2867. };
  2868. };
  2869.  
  2870. spi@05011000 {
  2871. #address-cells = <0x1>;
  2872. #size-cells = <0x0>;
  2873. compatible = "allwinner,sun50i-spi";
  2874. device_type = "spi1";
  2875. reg = <0x0 0x5011000 0x0 0x1000>;
  2876. interrupts = <0x0 0xb 0x4>;
  2877. clocks = <0x2 0x6b>;
  2878. clock-frequency = <0x5f5e100>;
  2879. pinctrl-names = "default", "sleep";
  2880. spi1_cs_number = <0x1>;
  2881. spi1_cs_bitmap = <0x1>;
  2882. status = "disabled";
  2883. pinctrl-0 = <0xf3 0xf4>;
  2884. pinctrl-1 = <0xf5 0xf6>;
  2885. };
  2886.  
  2887. pcie@0x05400000 {
  2888. #address-cells = <0x3>;
  2889. #size-cells = <0x2>;
  2890. compatible = "allwinner,sun50i-pcie";
  2891. reg = <0x0 0x5400000 0x0 0x2000 0x0 0x5410000 0x0 0x10000>;
  2892. reg-names = "dbi", "config";
  2893. device_type = "pci";
  2894. ranges = <0x800 0x0 0x5410000 0x0 0x5410000 0x0 0x10000 0x81000000 0x0 0x0 0x0 0x5600000 0x0 0x10000 0x82000000 0x0 0x5500000 0x0 0x5500000 0x0 0x100000>;
  2895. num-lanes = <0x1>;
  2896. interrupts = <0x0 0x7f 0x4 0x0 0x7e 0x4>;
  2897. interrupt-names = "msi";
  2898. clocks = <0x6f 0x70 0x71 0x72>;
  2899. #interrupt-cells = <0x1>;
  2900. interrupt-map-mask = <0x0 0x0 0x0 0x0>;
  2901. interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x7f 0x4>;
  2902. status = "disabled";
  2903. pcie_perst = <0x7e 0x3 0x16 0x1 0xffffffff 0xffffffff 0xffffffff>;
  2904. speed_gen = <0x1>;
  2905. };
  2906.  
  2907. sdmmc@04022000 {
  2908. compatible = "allwinner,sunxi-mmc-v4p6x";
  2909. device_type = "sdc2";
  2910. reg = <0x0 0x4022000 0x0 0x1000>;
  2911. interrupts = <0x0 0x25 0x104>;
  2912. clocks = <0x7 0x73 0x74 0x75 0x76>;
  2913. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2914. pinctrl-names = "default", "sleep";
  2915. pinctrl-1 = <0x78>;
  2916. bus-width = <0x8>;
  2917. max-frequency = <0x8f0d180>;
  2918. sdc_tm4_sm0_freq0 = <0x0>;
  2919. sdc_tm4_sm0_freq1 = <0x0>;
  2920. sdc_tm4_sm1_freq0 = <0x0>;
  2921. sdc_tm4_sm1_freq1 = <0x0>;
  2922. sdc_tm4_sm2_freq0 = <0x0>;
  2923. sdc_tm4_sm2_freq1 = <0x0>;
  2924. sdc_tm4_sm3_freq0 = <0x5000000>;
  2925. sdc_tm4_sm3_freq1 = <0x405>;
  2926. sdc_tm4_sm4_freq0 = <0x50000>;
  2927. sdc_tm4_sm4_freq1 = <0x408>;
  2928. status = "disabled";
  2929. non-removable;
  2930. pinctrl-0 = <0x109>;
  2931. cd-gpios;
  2932. sunxi-power-save-mode;
  2933. sunxi-dis-signal-vol-sw;
  2934. mmc-ddr-1_8v;
  2935. mmc-hs200-1_8v;
  2936. mmc-hs400-1_8v;
  2937. vmmc = "vcc-emmcv";
  2938. vqmmc = "vcc-emmcvq18";
  2939. vdmmc = "none";
  2940. };
  2941.  
  2942. sdmmc@04020000 {
  2943. compatible = "allwinner,sunxi-mmc-v4p1x";
  2944. device_type = "sdc0";
  2945. reg = <0x0 0x4020000 0x0 0x1000>;
  2946. interrupts = <0x0 0x23 0x104>;
  2947. clocks = <0x7 0x73 0x79 0x7a 0x7b>;
  2948. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2949. pinctrl-names = "default", "sleep";
  2950. pinctrl-1 = <0x7d>;
  2951. max-frequency = <0x2faf080>;
  2952. bus-width = <0x4>;
  2953. status = "okay";
  2954. pinctrl-0 = <0x107>;
  2955. cd-gpios = <0x7e 0x5 0x6 0x0 0x1 0x2 0xffffffff>;
  2956. sunxi-power-save-mode;
  2957. sunxi-dis-signal-vol-sw;
  2958. vmmc = "vcc-sdcv";
  2959. vqmmc = "vcc-sdcvq33";
  2960. vdmmc = "vcc-sdcvd";
  2961. ctl-spec-caps = <0x80>;
  2962. };
  2963.  
  2964. sdmmc@04021000 {
  2965. compatible = "allwinner,sunxi-mmc-v4p1x";
  2966. device_type = "sdc1";
  2967. reg = <0x0 0x4021000 0x0 0x1000>;
  2968. interrupts = <0x0 0x24 0x104>;
  2969. clocks = <0x7 0x73 0x7f 0x80 0x81>;
  2970. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2971. pinctrl-names = "default", "sleep";
  2972. pinctrl-1 = <0x83>;
  2973. max-frequency = <0x8f0d180>;
  2974. bus-width = <0x4>;
  2975. sunxi-dly-52M-ddr4 = <0x1 0x0 0x0 0x0 0x2>;
  2976. sunxi-dly-104M = <0x1 0x0 0x0 0x0 0x1>;
  2977. sunxi-dly-208M = <0x1 0x0 0x0 0x0 0x1>;
  2978. status = "okay";
  2979. pinctrl-0 = <0x108>;
  2980. sd-uhs-sdr50;
  2981. sd-uhs-ddr50;
  2982. sd-uhs-sdr104;
  2983. cap-sdio-irq;
  2984. keep-power-in-suspend;
  2985. ignore-pm-notify;
  2986. };
  2987.  
  2988. disp@01000000 {
  2989. compatible = "allwinner,sunxi-disp";
  2990. reg = <0x0 0x1000000 0x0 0x1400000 0x0 0x6510000 0x0 0x100 0x0 0x6511000 0x0 0x800 0x0 0x6515000 0x0 0x800>;
  2991. interrupts = <0x0 0x41 0x104 0x0 0x42 0x104>;
  2992. clocks = <0x84 0x85 0x86 0x87>;
  2993. boot_disp = <0x0>;
  2994. fb_base = <0x0>;
  2995. iommus = <0x19 0x0 0x0>;
  2996. status = "okay";
  2997. device_type = "disp";
  2998. disp_init_enable = <0x1>;
  2999. disp_mode = <0x0>;
  3000. screen0_output_type = <0x3>;
  3001. screen0_output_mode = <0xa>;
  3002. screen0_output_format = <0x1>;
  3003. screen0_output_bits = <0x0>;
  3004. screen0_output_eotf = <0x4>;
  3005. screen0_output_cs = <0x101>;
  3006. screen0_output_dvi_hdmi = <0x2>;
  3007. screen0_output_range = <0x2>;
  3008. screen0_output_scan = <0x0>;
  3009. screen0_output_aspect_ratio = <0x8>;
  3010. screen1_output_type = <0x0>;
  3011. screen1_output_mode = <0x2>;
  3012. screen1_output_format = <0x1>;
  3013. screen1_output_bits = <0x0>;
  3014. screen1_output_eotf = <0x4>;
  3015. screen1_output_cs = <0x104>;
  3016. screen1_output_dvi_hdmi = <0x2>;
  3017. screen1_output_range = <0x2>;
  3018. screen1_output_scan = <0x0>;
  3019. screen1_output_aspect_ratio = <0x8>;
  3020. dev0_output_type = <0x4>;
  3021. dev0_output_mode = <0xa>;
  3022. dev0_screen_id = <0x0>;
  3023. dev0_do_hpd = <0x1>;
  3024. dev1_output_type = <0x0>;
  3025. dev1_output_mode = <0xb>;
  3026. dev1_screen_id = <0x1>;
  3027. dev1_do_hpd = <0x1>;
  3028. dev2_output_type = <0x0>;
  3029. def_output_dev = <0x0>;
  3030. hdmi_mode_check = <0x1>;
  3031. fb0_format = <0x0>;
  3032. fb0_width = <0x0>;
  3033. fb0_height = <0x0>;
  3034. fb1_format = <0x0>;
  3035. fb1_width = <0x0>;
  3036. fb1_height = <0x0>;
  3037. disp_para_zone = <0x1>;
  3038. };
  3039.  
  3040. lcd0@01c0c000 {
  3041. compatible = "allwinner,sunxi-lcd0";
  3042. pinctrl-names = "active", "sleep";
  3043. status = "okay";
  3044. device_type = "lcd0";
  3045. lcd_used = <0x0>;
  3046. lcd_driver_name = "default_lcd";
  3047. lcd_backlight = <0x32>;
  3048. lcd_if = <0x3>;
  3049. lcd_x = <0x500>;
  3050. lcd_y = <0x320>;
  3051. lcd_width = <0x96>;
  3052. lcd_height = <0x5e>;
  3053. lcd_dclk_freq = <0x46>;
  3054. lcd_pwm_used = <0x1>;
  3055. lcd_pwm_ch = <0x0>;
  3056. lcd_pwm_freq = <0xc350>;
  3057. lcd_pwm_pol = <0x1>;
  3058. lcd_pwm_max_limit = <0xff>;
  3059. lcd_hbp = <0x14>;
  3060. lcd_ht = <0x58a>;
  3061. lcd_hspw = <0xa>;
  3062. lcd_vbp = <0xa>;
  3063. lcd_vt = <0x32e>;
  3064. lcd_vspw = <0x5>;
  3065. lcd_lvds_if = <0x0>;
  3066. lcd_lvds_colordepth = <0x1>;
  3067. lcd_lvds_mode = <0x0>;
  3068. lcd_frm = <0x1>;
  3069. lcd_hv_clk_phase = <0x0>;
  3070. lcd_hv_sync_polarity = <0x0>;
  3071. lcd_gamma_en = <0x0>;
  3072. lcd_bright_curve_en = <0x0>;
  3073. lcd_cmap_en = <0x0>;
  3074. lcd_bl_en = <0x7e 0x3 0x17 0x1 0x0 0xffffffff 0x1>;
  3075. lcd_bl_en_power = "none";
  3076. lcd_power = "vcc-lcd-0";
  3077. lcd_fix_power = "vcc-dsi-33";
  3078. pinctrl-0 = <0xfa>;
  3079. lcd_pin_power = "vcc-pd";
  3080. pinctrl-1 = <0xfb>;
  3081. };
  3082.  
  3083. hdmi@06000000 {
  3084. compatible = "allwinner,sunxi-hdmi";
  3085. reg = <0x0 0x6000000 0x0 0x100000>;
  3086. interrupts = <0x0 0x40 0x0>;
  3087. clocks = <0x88 0x89 0x8a 0x8b>;
  3088. pinctrl-names = "ddc_active", "sleep", "cec_active";
  3089. pinctrl-1 = <0x8d>;
  3090. pinctrl-2 = <0x8e>;
  3091. status = "okay";
  3092. device_type = "hdmi";
  3093. hdmi_hdcp_enable = <0x0>;
  3094. hdmi_hdcp22_enable = <0x0>;
  3095. hdmi_cts_compatibility = <0x0>;
  3096. hdmi_cec_support = <0x1>;
  3097. hdmi_skip_bootedid = <0x1>;
  3098. pinctrl-0 = <0xfc>;
  3099. ddc_en_io_ctrl = <0x1>;
  3100. ddc_io_ctrl = <0x7e 0x7 0x2 0x1 0xffffffff 0xffffffff 0x0>;
  3101. };
  3102.  
  3103. tv0@01c94000 {
  3104. compatible = "allwinner,sunxi-tv";
  3105. reg = <0x0 0x1e40000 0x0 0x1000>;
  3106. status = "disabled";
  3107. device_type = "tv0";
  3108. dac_src0 = <0x0>;
  3109. dac_type0 = <0x0>;
  3110. interface = <0x1>;
  3111. };
  3112.  
  3113. tr@01000000 {
  3114. compatible = "allwinner,sun50i-tr";
  3115. reg = <0x0 0x1000000 0x0 0x200bc>;
  3116. interrupts = <0x0 0x60 0x104>;
  3117. clocks = <0x84>;
  3118. status = "okay";
  3119. };
  3120.  
  3121. pwm@0300a000 {
  3122. compatible = "allwinner,sunxi-pwm";
  3123. reg = <0x0 0x300a000 0x0 0x3c>;
  3124. clocks = <0x8f>;
  3125. pwm-number = <0x2>;
  3126. pwm-base = <0x0>;
  3127. pwms = <0x90 0x91>;
  3128. };
  3129.  
  3130. pwm0@0300a000 {
  3131. compatible = "allwinner,sunxi-pwm0";
  3132. pinctrl-names = "active", "sleep";
  3133. reg_base = <0x300a000>;
  3134. reg_busy_offset = <0x0>;
  3135. reg_busy_shift = <0x1c>;
  3136. reg_enable_offset = <0x0>;
  3137. reg_enable_shift = <0x4>;
  3138. reg_clk_gating_offset = <0x0>;
  3139. reg_clk_gating_shift = <0x6>;
  3140. reg_bypass_offset = <0x0>;
  3141. reg_bypass_shift = <0x9>;
  3142. reg_pulse_start_offset = <0x0>;
  3143. reg_pulse_start_shift = <0x8>;
  3144. reg_mode_offset = <0x0>;
  3145. reg_mode_shift = <0x7>;
  3146. reg_polarity_offset = <0x0>;
  3147. reg_polarity_shift = <0x5>;
  3148. reg_period_offset = <0x4>;
  3149. reg_period_shift = <0x10>;
  3150. reg_period_width = <0x10>;
  3151. reg_active_offset = <0x4>;
  3152. reg_active_shift = <0x0>;
  3153. reg_active_width = <0x10>;
  3154. reg_prescal_offset = <0x0>;
  3155. reg_prescal_shift = <0x0>;
  3156. reg_prescal_width = <0x4>;
  3157. linux,phandle = <0x90>;
  3158. phandle = <0x90>;
  3159. device_type = "pwm0";
  3160. pwm_used = <0x1>;
  3161. pinctrl-0 = <0xff>;
  3162. pinctrl-1 = <0x100>;
  3163. };
  3164.  
  3165. pwm1@0300a000 {
  3166. compatible = "allwinner,sunxi-pwm1";
  3167. pinctrl-names = "active", "sleep";
  3168. reg_base = <0x300a000>;
  3169. reg_busy_offset = <0x0>;
  3170. reg_busy_shift = <0x1d>;
  3171. reg_enable_offset = <0x0>;
  3172. reg_enable_shift = <0x13>;
  3173. reg_clk_gating_offset = <0x0>;
  3174. reg_clk_gating_shift = <0x15>;
  3175. reg_bypass_offset = <0x0>;
  3176. reg_bypass_shift = <0x18>;
  3177. reg_pulse_start_offset = <0x0>;
  3178. reg_pulse_start_shift = <0x17>;
  3179. reg_mode_offset = <0x0>;
  3180. reg_mode_shift = <0x16>;
  3181. reg_polarity_offset = <0x0>;
  3182. reg_polarity_shift = <0x14>;
  3183. reg_period_offset = <0x8>;
  3184. reg_period_shift = <0x10>;
  3185. reg_period_width = <0x10>;
  3186. reg_active_offset = <0x8>;
  3187. reg_active_shift = <0x0>;
  3188. reg_active_width = <0x10>;
  3189. reg_prescal_offset = <0x0>;
  3190. reg_prescal_shift = <0xf>;
  3191. reg_prescal_width = <0x4>;
  3192. linux,phandle = <0x91>;
  3193. phandle = <0x91>;
  3194. device_type = "pwm1";
  3195. pwm_used = <0x1>;
  3196. pinctrl-0 = <0x101>;
  3197. pinctrl-1 = <0x102>;
  3198. };
  3199.  
  3200. s_pwm@07020c00 {
  3201. compatible = "allwinner,sunxi-s_pwm";
  3202. reg = <0x0 0x7020c00 0x0 0x3c>;
  3203. clocks = <0x92>;
  3204. pwm-number = <0x1>;
  3205. pwm-base = <0x10>;
  3206. pwms = <0x93>;
  3207. };
  3208.  
  3209. spwm0@07020c00 {
  3210. compatible = "allwinner,sunxi-pwm16";
  3211. pinctrl-names = "active", "sleep";
  3212. reg_base = <0x7020c00>;
  3213. reg_busy_offset = <0x0>;
  3214. reg_busy_shift = <0x1c>;
  3215. reg_enable_offset = <0x0>;
  3216. reg_enable_shift = <0x4>;
  3217. reg_clk_gating_offset = <0x0>;
  3218. reg_clk_gating_shift = <0x6>;
  3219. reg_bypass_offset = <0x0>;
  3220. reg_bypass_shift = <0x9>;
  3221. reg_pulse_start_offset = <0x0>;
  3222. reg_pulse_start_shift = <0x8>;
  3223. reg_mode_offset = <0x0>;
  3224. reg_mode_shift = <0x7>;
  3225. reg_polarity_offset = <0x0>;
  3226. reg_polarity_shift = <0x5>;
  3227. reg_period_offset = <0x4>;
  3228. reg_period_shift = <0x10>;
  3229. reg_period_width = <0x10>;
  3230. reg_active_offset = <0x4>;
  3231. reg_active_shift = <0x0>;
  3232. reg_active_width = <0x10>;
  3233. reg_prescal_offset = <0x0>;
  3234. reg_prescal_shift = <0x0>;
  3235. reg_prescal_width = <0x4>;
  3236. linux,phandle = <0x93>;
  3237. phandle = <0x93>;
  3238. };
  3239.  
  3240. boot_disp {
  3241. compatible = "allwinner,boot_disp";
  3242. device_type = "boot_disp";
  3243. auto_hpd = <0x1>;
  3244. output_disp = <0x0>;
  3245. output_type = <0x3>;
  3246. output_mode = <0xb>;
  3247. hdmi_channel = <0x0>;
  3248. hdmi_mode = <0x4>;
  3249. };
  3250.  
  3251. ac200 {
  3252. compatible = "allwinner,sunxi-ac200";
  3253. clocks = <0x86>;
  3254. pinctrl-names = "active", "sleep", "ccir_clk_active", "ccir_clk_sleep";
  3255. pinctrl-2 = <0x94>;
  3256. pinctrl-3 = <0x95>;
  3257. status = "okay";
  3258. device_type = "ac200";
  3259. tv_used = <0x1>;
  3260. tv_module_name = "tv_ac200";
  3261. tv_twi_used = <0x1>;
  3262. tv_twi_id = <0x3>;
  3263. tv_twi_addr = <0x10>;
  3264. tv_pwm_ch = <0x1>;
  3265. tv_clk_div = <0x5>;
  3266. tv_regulator_name = "vcc-audio-33";
  3267. pinctrl-0 = <0xfd>;
  3268. pinctrl-1 = <0xfe>;
  3269. };
  3270.  
  3271. vind@0 {
  3272. compatible = "allwinner,sunxi-vin-media", "simple-bus";
  3273. #address-cells = <0x2>;
  3274. #size-cells = <0x2>;
  3275. ranges;
  3276. device_id = <0x0>;
  3277. reg = <0x0 0x6620000 0x0 0x1000>;
  3278. clocks = <0x96 0x2 0x97 0x7 0x2>;
  3279. pinctrl-names = "mclk0-default", "mclk0-sleep";
  3280. pinctrl-0 = <0x98>;
  3281. pinctrl-1 = <0x99>;
  3282. status = "disabled";
  3283. device_type = "vind0";
  3284.  
  3285. cci@0x0662e000 {
  3286. compatible = "allwinner,sunxi-csi_cci";
  3287. reg = <0x0 0x662e000 0x0 0x1000>;
  3288. interrupts = <0x0 0x48 0x4>;
  3289. clocks = <0x9a>;
  3290. pinctrl-names = "default", "sleep";
  3291. pinctrl-1 = <0x9c>;
  3292. device_id = <0x0>;
  3293. status = "disabled";
  3294. device_type = "csi_cci0";
  3295. pinctrl-0 = <0x106>;
  3296. };
  3297.  
  3298. csi@0x06621000 {
  3299. device_type = "csi0";
  3300. compatible = "allwinner,sunxi-csi";
  3301. reg = <0x0 0x6621000 0x0 0x1000>;
  3302. interrupts = <0x0 0x46 0x4>;
  3303. pinctrl-names = "default", "sleep";
  3304. pinctrl-1 = <0x9e>;
  3305. device_id = <0x0>;
  3306. iommus = <0x19 0x4 0x1>;
  3307. status = "disabled";
  3308. pinctrl-0 = <0x105>;
  3309. };
  3310.  
  3311. csi@1 {
  3312. device_type = "csi1";
  3313. compatible = "allwinner,sunxi-csi";
  3314. device_id = <0x1>;
  3315. iommus = <0x19 0x4 0x1>;
  3316. status = "disabled";
  3317. };
  3318.  
  3319. mipi@0 {
  3320. compatible = "allwinner,sunxi-mipi";
  3321. device_id = <0x0>;
  3322. status = "disabled";
  3323. };
  3324.  
  3325. mipi@1 {
  3326. compatible = "allwinner,sunxi-mipi";
  3327. device_id = <0x1>;
  3328. status = "disabled";
  3329. };
  3330.  
  3331. isp@0 {
  3332. compatible = "allwinner,sunxi-isp";
  3333. reg = <0x0 0x2100000 0x0 0x800>;
  3334. interrupts = <0x0 0x56 0x4>;
  3335. device_id = <0x0>;
  3336. iommus = <0x19 0x4 0x1>;
  3337. status = "okay";
  3338. linux,phandle = <0xa1>;
  3339. phandle = <0xa1>;
  3340. };
  3341.  
  3342. isp@1 {
  3343. compatible = "allwinner,sunxi-isp";
  3344. reg = <0x0 0x2100800 0x0 0x800>;
  3345. device_id = <0x1>;
  3346. iommus = <0x19 0x4 0x1>;
  3347. status = "disabled";
  3348. linux,phandle = <0xa2>;
  3349. phandle = <0xa2>;
  3350. };
  3351.  
  3352. scaler@0x02101000 {
  3353. compatible = "allwinner,sunxi-scaler";
  3354. reg = <0x0 0x2101000 0x0 0x400>;
  3355. device_id = <0x0>;
  3356. iommus = <0x19 0x4 0x1>;
  3357. status = "okay";
  3358. };
  3359.  
  3360. scaler@0x02101400 {
  3361. compatible = "allwinner,sunxi-scaler";
  3362. reg = <0x0 0x2101400 0x0 0x400>;
  3363. device_id = <0x1>;
  3364. iommus = <0x19 0x4 0x1>;
  3365. status = "okay";
  3366. };
  3367.  
  3368. scaler@2 {
  3369. compatible = "allwinner,sunxi-scaler";
  3370. device_id = <0x2>;
  3371. iommus = <0x19 0x4 0x1>;
  3372. status = "disabled";
  3373. };
  3374.  
  3375. scaler@3 {
  3376. compatible = "allwinner,sunxi-scaler";
  3377. device_id = <0x3>;
  3378. iommus = <0x19 0x4 0x1>;
  3379. status = "disabled";
  3380. };
  3381.  
  3382. actuator@0 {
  3383. device_type = "actuator0";
  3384. compatible = "allwinner,sunxi-actuator";
  3385. actuator0_name = "ad5820_act";
  3386. actuator0_slave = <0x18>;
  3387. actuator0_afvdd_vol = <0x2ab980>;
  3388. status = "disabled";
  3389. linux,phandle = <0xa0>;
  3390. phandle = <0xa0>;
  3391. actuator0_af_pwdn;
  3392. actuator0_afvdd;
  3393. };
  3394.  
  3395. flash@0 {
  3396. device_type = "flash0";
  3397. compatible = "allwinner,sunxi-flash";
  3398. flash0_type = <0x2>;
  3399. device_id = <0x0>;
  3400. status = "disabled";
  3401. linux,phandle = <0x9f>;
  3402. phandle = <0x9f>;
  3403. flash0_en;
  3404. flash0_mode;
  3405. flash0_flvdd;
  3406. flash0_flvdd_vol;
  3407. };
  3408.  
  3409. sensor@0 {
  3410. device_type = "sensor0";
  3411. sensor0_mname = "gc2035";
  3412. sensor0_twi_cci_id = <0x0>;
  3413. sensor0_twi_addr = <0x78>;
  3414. sensor0_pos = "rear";
  3415. sensor0_isp_used = <0x0>;
  3416. sensor0_fmt = <0x0>;
  3417. sensor0_stby_mode = <0x1>;
  3418. sensor0_vflip = <0x0>;
  3419. sensor0_hflip = <0x0>;
  3420. sensor0_iovdd_vol = <0x2ab980>;
  3421. sensor0_avdd_vol = <0x2ab980>;
  3422. sensor0_dvdd_vol = <0x16e360>;
  3423. sensor0_power_en;
  3424. flash_handle = <0x9f>;
  3425. act_handle = <0xa0>;
  3426. status = "disabled";
  3427. linux,phandle = <0xa3>;
  3428. phandle = <0xa3>;
  3429. sensor0_iovdd;
  3430. sensor0_avdd;
  3431. sensor0_dvdd;
  3432. sensor0_reset = <0x7e 0x3 0xe 0x1 0x0 0x3 0x0>;
  3433. sensor0_pwdn = <0x7e 0x3 0xf 0x1 0x0 0x3 0x1>;
  3434. };
  3435.  
  3436. sensor@1 {
  3437. device_type = "sensor1";
  3438. sensor1_mname = "ov5647";
  3439. sensor1_twi_cci_id = <0x0>;
  3440. sensor1_twi_addr = <0x6c>;
  3441. sensor1_pos = "front";
  3442. sensor1_isp_used = <0x0>;
  3443. sensor1_fmt = <0x0>;
  3444. sensor1_stby_mode = <0x1>;
  3445. sensor1_vflip = <0x0>;
  3446. sensor1_hflip = <0x0>;
  3447. sensor1_iovdd_vol = <0x2ab980>;
  3448. sensor1_avdd_vol = <0x2ab980>;
  3449. sensor1_dvdd_vol = <0x1b7740>;
  3450. flash_handle;
  3451. act_handle;
  3452. status = "disabled";
  3453. linux,phandle = <0xa4>;
  3454. phandle = <0xa4>;
  3455. sensor1_iovdd;
  3456. sensor1_avdd;
  3457. sensor1_dvdd;
  3458. sensor1_power_en;
  3459. sensor1_reset = <0x7e 0x3 0xe 0x1 0x0 0x3 0x0>;
  3460. sensor1_pwdn = <0x7e 0x3 0xf 0x1 0x0 0x3 0x1>;
  3461. };
  3462.  
  3463. vinc@0x06623000 {
  3464. device_type = "vinc0";
  3465. compatible = "allwinner,sunxi-vin-core";
  3466. reg = <0x0 0x6623000 0x0 0x100>;
  3467. interrupts = <0x0 0x43 0x4>;
  3468. vinc0_csi_sel = <0x0>;
  3469. vinc0_mipi_sel = <0xff>;
  3470. vinc0_isp_sel = <0x0>;
  3471. vinc0_sensor_sel = <0x0>;
  3472. vinc0_sensor_list = <0x0>;
  3473. isp_handle = <0xa1 0xa2>;
  3474. sensor_handle = <0xa3 0xa4>;
  3475. device_id = <0x0>;
  3476. iommus = <0x19 0x4 0x1>;
  3477. status = "disabled";
  3478. vinc0_rear_sensor_sel = <0x0>;
  3479. vinc0_front_sensor_sel = <0x1>;
  3480. };
  3481.  
  3482. vinc@0x06623100 {
  3483. device_type = "vinc1";
  3484. compatible = "allwinner,sunxi-vin-core";
  3485. reg = <0x0 0x6623100 0x0 0x100>;
  3486. interrupts = <0x0 0x44 0x4>;
  3487. vinc1_csi_sel = <0x0>;
  3488. vinc1_mipi_sel = <0xff>;
  3489. vinc1_isp_sel = <0x0>;
  3490. vinc1_sensor_sel = <0x1>;
  3491. vinc1_sensor_list = <0x0>;
  3492. isp_handle = <0xa1 0xa2>;
  3493. sensor_handle = <0xa3 0xa4>;
  3494. device_id = <0x1>;
  3495. iommus = <0x19 0x4 0x1>;
  3496. status = "disabled";
  3497. vinc1_rear_sensor_sel = <0x0>;
  3498. vinc1_front_sensor_sel = <0x1>;
  3499. };
  3500. };
  3501.  
  3502. vdevice@0 {
  3503. compatible = "allwinner,sun50i-vdevice";
  3504. device_type = "Vdevice";
  3505. pinctrl-names = "default";
  3506. test-gpios = <0x7e 0x1 0x0 0x1 0x2 0x2 0x1>;
  3507. status = "disabled";
  3508. pinctrl-0 = <0x10d>;
  3509. };
  3510.  
  3511. emce@01905000 {
  3512. compatible = "allwinner,sunxi-emce";
  3513. device_name = "emce";
  3514. reg = <0x0 0x1905000 0x0 0x100>;
  3515. clock-frequency = <0x11e1a300>;
  3516. clocks = <0xa6 0x1b>;
  3517. };
  3518.  
  3519. ce@1904000 {
  3520. compatible = "allwinner,sunxi-ce";
  3521. device_name = "ce";
  3522. reg = <0x0 0x1904000 0x0 0xa0 0x0 0x1904800 0x0 0xa0>;
  3523. interrupts = <0x0 0x57 0xff01 0x0 0x58 0xff01>;
  3524. clock-frequency = <0x11e1a300>;
  3525. clocks = <0xa7 0x1b>;
  3526. };
  3527.  
  3528. deinterlace@0x01420000 {
  3529. #address-cells = <0x1>;
  3530. #size-cells = <0x0>;
  3531. compatible = "allwinner,sunxi-deinterlace";
  3532. reg = <0x0 0x1420000 0x0 0x20c>;
  3533. interrupts = <0x0 0x4f 0x4>;
  3534. clocks = <0xa8 0x2>;
  3535. iommus = <0x19 0x2 0x1>;
  3536. status = "okay";
  3537. device_type = "di";
  3538. };
  3539.  
  3540. smartcard@0x05005000 {
  3541. #address-cells = <0x1>;
  3542. #size-cells = <0x0>;
  3543. compatible = "allwinner,sunxi-scr";
  3544. device_type = "scr0";
  3545. reg = <0x0 0x5005000 0x0 0x400>;
  3546. interrupts = <0x0 0x8 0x4>;
  3547. clocks = <0xa9 0xaa>;
  3548. clock-frequency = <0x16e3600>;
  3549. pinctrl-names = "default", "sleep";
  3550. pinctrl-0 = <0xab 0xac>;
  3551. pinctrl-1 = <0xad>;
  3552. status = "disabled";
  3553. };
  3554.  
  3555. smartcard@0x05005400 {
  3556. #address-cells = <0x1>;
  3557. #size-cells = <0x0>;
  3558. compatible = "allwinner,sunxi-scr";
  3559. device_type = "scr1";
  3560. reg = <0x0 0x5005400 0x0 0x400>;
  3561. interrupts = <0x0 0x9 0x4>;
  3562. clocks = <0xae 0xaa>;
  3563. clock-frequency = <0x16e3600>;
  3564. pinctrl-names = "default", "sleep";
  3565. pinctrl-0 = <0xaf 0xb0>;
  3566. pinctrl-1 = <0xb1>;
  3567. status = "disabled";
  3568. };
  3569.  
  3570. pmu@0 {
  3571. interrupts = <0x0 0x60 0x4>;
  3572. status = "okay";
  3573. device_type = "pmu0";
  3574. compatible = "axp806";
  3575. pmu_id = <0x3>;
  3576. pmu_irq_wakeup = <0x1>;
  3577. pmu_hot_shutdown = <0x1>;
  3578.  
  3579. powerkey@0 {
  3580. status = "okay";
  3581. device_type = "powerkey0";
  3582. compatible = "axp806-powerkey";
  3583. pmu_powkey_off_time = <0xbb8>;
  3584. pmu_powkey_off_func = <0x0>;
  3585. pmu_powkey_off_en = <0x1>;
  3586. pmu_powkey_long_time = <0x5dc>;
  3587. pmu_powkey_on_time = <0x3e8>;
  3588. };
  3589.  
  3590. regulator@0 {
  3591. status = "okay";
  3592. device_type = "regulator0";
  3593. compatible = "axp806-regulator";
  3594. regulator_count = <0x10>;
  3595. regulator1 = "axp806_dcdca none vdd-cpua";
  3596. regulator2 = "axp806_dcdcb none";
  3597. regulator3 = "axp806_dcdcc none vdd-gpu";
  3598. regulator4 = "axp806_dcdcd none vdd-sys vdd-hdmi vdd-pcie vdd-usb";
  3599. regulator5 = "axp806_dcdce none vcc-dram";
  3600. regulator6 = "axp806_aldo1 none vcc-pl vcc-led vcc-ir vcc-pg vcc-pm vcc-ts";
  3601. regulator7 = "axp806_aldo2 none ac-ldoin vcc-audio-33 vcc-ephy usb-dvdd vcc-tv";
  3602. regulator8 = "axp806_aldo3 none";
  3603. regulator9 = "axp806_bldo1 none vdd-dram-18 vdd-bias vcc-pll";
  3604. regulator10 = "axp806_bldo2 none vcc-emmc-18 vdd-efuse vcc-hdmi vcc-emmcvq18";
  3605. regulator11 = "axp806_bldo3 none";
  3606. regulator12 = "axp806_bldo4 none";
  3607. regulator13 = "axp806_cldo1 none vcc-io vcc-nand vcc-card vcc-pd vcc-usb vcc-pcie vcc-uart vcc-jtagx vcc-emmc-33 vcc-camera-33 vcc-pcie-slot vcc-emmcv vcc-sdcv vcc-sdcvq33 vcc-sdcvd";
  3608. regulator14 = "axp806_cldo2 none";
  3609. regulator15 = "axp806_cldo3 none vcc-wifi";
  3610. regulator16 = "axp806_sw none";
  3611. };
  3612.  
  3613. axp_gpio@0 {
  3614. gpio-controller;
  3615. #size-cells = <0x0>;
  3616. #gpio-cells = <0x6>;
  3617. status = "okay";
  3618. device_type = "axp_pio";
  3619. linux,phandle = <0xf7>;
  3620. phandle = <0xf7>;
  3621. };
  3622.  
  3623. charger@0 {
  3624. status = "disabled";
  3625. device_type = "charger0";
  3626. pmu_bat_unused = <0x1>;
  3627. pmu_pwroff_vol = <0xce4>;
  3628. power_start = <0x0>;
  3629. };
  3630. };
  3631.  
  3632. nmi@0x01f00c00 {
  3633. #address-cells = <0x1>;
  3634. #size-cells = <0x0>;
  3635. compatible = "allwinner,sunxi-nmi";
  3636. reg = <0x0 0x1f00c00 0x0 0x50>;
  3637. nmi_irq_ctrl = <0xc>;
  3638. nmi_irq_en = <0x40>;
  3639. nmi_irq_status = <0x10>;
  3640. nmi_irq_mask = <0x50>;
  3641. status = "okay";
  3642. };
  3643.  
  3644. nand0@04011000 {
  3645. compatible = "allwinner,sun50iw6-nand";
  3646. device_type = "nand0";
  3647. reg = <0x0 0x4011000 0x0 0x1000>;
  3648. interrupts = <0x0 0x22 0x4>;
  3649. clocks = <0x1b 0xb2 0xb3>;
  3650. pinctrl-names = "default", "sleep";
  3651. pinctrl-1 = <0xb6>;
  3652. nand0_regulator1 = "vcc-nand";
  3653. nand0_regulator2 = "none";
  3654. nand0_cache_level = <0x55aaaa55>;
  3655. nand0_flush_cache_num = <0x55aaaa55>;
  3656. nand0_capacity_level = <0x55aaaa55>;
  3657. nand0_id_number_ctl = <0x55aaaa55>;
  3658. nand0_print_level = <0x55aaaa55>;
  3659. nand0_p0 = <0x55aaaa55>;
  3660. nand0_p1 = <0x55aaaa55>;
  3661. nand0_p2 = <0x55aaaa55>;
  3662. nand0_p3 = <0x55aaaa55>;
  3663. status = "disabled";
  3664. nand0_support_2ch = <0x0>;
  3665. pinctrl-0 = <0xf8 0xf9>;
  3666. };
  3667.  
  3668. ts0@05060000 {
  3669. compatible = "allwinner,sun50i-tsc";
  3670. device_type = "ts0";
  3671. reg = <0x0 0x5060000 0x0 0x1000>;
  3672. interrupts = <0x0 0xe 0x4>;
  3673. clocks = <0x2 0xb7>;
  3674. pinctrl-names = "ts0-default", "ts1-default", "ts2-default", "ts3-default", "ts0-sleep", "ts1-sleep", "ts2-sleep", "ts3-sleep";
  3675. pinctrl-0 = <0xb8>;
  3676. pinctrl-1 = <0xb9>;
  3677. pinctrl-2 = <0xba>;
  3678. pinctrl-3 = <0xbb>;
  3679. pinctrl-4 = <0xbc>;
  3680. pinctrl-5 = <0xbd>;
  3681. pinctrl-6 = <0xbe>;
  3682. pinctrl-7 = <0xbf>;
  3683. ts0config = <0x1>;
  3684. ts1config = <0x0>;
  3685. ts2config = <0x0>;
  3686. ts3config = <0x0>;
  3687. status = "okay";
  3688. };
  3689.  
  3690. thermal_sensor {
  3691. compatible = "allwinner,thermal_sensor";
  3692. reg = <0x0 0x5070400 0x0 0x400>;
  3693. interrupts = <0x0 0xf 0x0>;
  3694. clocks = <0x7 0xc0>;
  3695. sensor_num = <0x2>;
  3696. combine_num = <0x2>;
  3697. alarm_low_temp = <0x69>;
  3698. alarm_high_temp = <0x6e>;
  3699. alarm_temp_hysteresis = <0xf>;
  3700. shut_temp = <0x73>;
  3701. status = "okay";
  3702.  
  3703. ths_combine0 {
  3704. compatible = "allwinner,ths_combine0";
  3705. #thermal-sensor-cells = <0x1>;
  3706. combine_sensor_num = <0x1>;
  3707. combine_sensor_type = "cpu";
  3708. combine_sensor_temp_type = "max";
  3709. combine_sensor_id = <0x0>;
  3710. linux,phandle = <0xc1>;
  3711. phandle = <0xc1>;
  3712. };
  3713.  
  3714. ths_combine1 {
  3715. compatible = "allwinner,ths_combine1";
  3716. #thermal-sensor-cells = <0x1>;
  3717. combine_sensor_num = <0x1>;
  3718. combine_sensor_type = "gpu";
  3719. combine_sensor_temp_type = "max";
  3720. combine_sensor_id = <0x1>;
  3721. linux,phandle = <0xc9>;
  3722. phandle = <0xc9>;
  3723. };
  3724. };
  3725.  
  3726. cpu_budget_cool {
  3727. device_type = "cpu_budget_cool";
  3728. compatible = "allwinner,budget_cooling";
  3729. #cooling-cells = <0x2>;
  3730. status = "okay";
  3731. state_cnt = <0x7>;
  3732. cluster_num = <0x1>;
  3733. state0 = <0x1b7740 0x4>;
  3734. state1 = <0x16b480 0x4>;
  3735. state2 = <0x142440 0x3>;
  3736. state3 = <0x107ac0 0x2>;
  3737. state4 = <0xd8cc0 0x1>;
  3738. state5 = <0xafc80 0x1>;
  3739. state6 = <0x75300 0x1>;
  3740. linux,phandle = <0xc3>;
  3741. phandle = <0xc3>;
  3742. };
  3743.  
  3744. gpu_cooling {
  3745. compatible = "allwinner,gpu_cooling";
  3746. reg = <0x0 0x0 0x0 0x0>;
  3747. #cooling-cells = <0x2>;
  3748. status = "okay";
  3749. state_cnt = <0x4>;
  3750. state0 = <0x0>;
  3751. state1 = <0x1>;
  3752. state2 = <0x2>;
  3753. state3 = <0x3>;
  3754. linux,phandle = <0xcb>;
  3755. phandle = <0xcb>;
  3756. };
  3757.  
  3758. thermal-zones {
  3759.  
  3760. cpu_thermal_zone {
  3761. polling-delay-passive = <0x3e8>;
  3762. polling-delay = <0x3e8>;
  3763. thermal-sensors = <0xc1 0x0>;
  3764.  
  3765. trips {
  3766.  
  3767. t0 {
  3768. temperature = <0x46>;
  3769. type = "passive";
  3770. hysteresis = <0x0>;
  3771. linux,phandle = <0xc2>;
  3772. phandle = <0xc2>;
  3773. };
  3774.  
  3775. t1 {
  3776. temperature = <0x5a>;
  3777. type = "passive";
  3778. hysteresis = <0x0>;
  3779. linux,phandle = <0xc4>;
  3780. phandle = <0xc4>;
  3781. };
  3782.  
  3783. t2 {
  3784. temperature = <0x5f>;
  3785. type = "passive";
  3786. hysteresis = <0x0>;
  3787. linux,phandle = <0xc5>;
  3788. phandle = <0xc5>;
  3789. };
  3790.  
  3791. t3 {
  3792. temperature = <0x64>;
  3793. type = "passive";
  3794. hysteresis = <0x0>;
  3795. linux,phandle = <0xc6>;
  3796. phandle = <0xc6>;
  3797. };
  3798.  
  3799. t4 {
  3800. temperature = <0x69>;
  3801. type = "passive";
  3802. hysteresis = <0x0>;
  3803. linux,phandle = <0xc7>;
  3804. phandle = <0xc7>;
  3805. };
  3806.  
  3807. t5 {
  3808. temperature = <0x6e>;
  3809. type = "passive";
  3810. hysteresis = <0x0>;
  3811. linux,phandle = <0xc8>;
  3812. phandle = <0xc8>;
  3813. };
  3814.  
  3815. t6 {
  3816. temperature = <0x73>;
  3817. type = "critical";
  3818. hysteresis = <0x0>;
  3819. };
  3820. };
  3821.  
  3822. cooling-maps {
  3823.  
  3824. bind0 {
  3825. contribution = <0x0>;
  3826. trip = <0xc2>;
  3827. cooling-device = <0xc3 0x1 0x1>;
  3828. };
  3829.  
  3830. bind1 {
  3831. contribution = <0x0>;
  3832. trip = <0xc4>;
  3833. cooling-device = <0xc3 0x2 0x2>;
  3834. };
  3835.  
  3836. bind2 {
  3837. contribution = <0x0>;
  3838. trip = <0xc5>;
  3839. cooling-device = <0xc3 0x3 0x3>;
  3840. };
  3841.  
  3842. bind3 {
  3843. contribution = <0x0>;
  3844. trip = <0xc6>;
  3845. cooling-device = <0xc3 0x4 0x4>;
  3846. };
  3847.  
  3848. bind4 {
  3849. contribution = <0x0>;
  3850. trip = <0xc7>;
  3851. cooling-device = <0xc3 0x5 0x5>;
  3852. };
  3853.  
  3854. bind5 {
  3855. contribution = <0x0>;
  3856. trip = <0xc8>;
  3857. cooling-device = <0xc3 0x6 0x6>;
  3858. };
  3859. };
  3860. };
  3861.  
  3862. gpu_thermal_zone {
  3863. polling-delay-passive = <0x3e8>;
  3864. polling-delay = <0x7d0>;
  3865. thermal-sensors = <0xc9 0x1>;
  3866.  
  3867. trips {
  3868.  
  3869. t0 {
  3870. temperature = <0x5f>;
  3871. type = "passive";
  3872. hysteresis = <0x0>;
  3873. linux,phandle = <0xca>;
  3874. phandle = <0xca>;
  3875. };
  3876.  
  3877. t1 {
  3878. temperature = <0x64>;
  3879. type = "passive";
  3880. hysteresis = <0x0>;
  3881. linux,phandle = <0xcc>;
  3882. phandle = <0xcc>;
  3883. };
  3884.  
  3885. t2 {
  3886. temperature = <0x69>;
  3887. type = "passive";
  3888. hysteresis = <0x0>;
  3889. linux,phandle = <0xcd>;
  3890. phandle = <0xcd>;
  3891. };
  3892.  
  3893. t3 {
  3894. temperature = <0x73>;
  3895. type = "critical";
  3896. hysteresis = <0x0>;
  3897. };
  3898. };
  3899.  
  3900. cooling-maps {
  3901.  
  3902. bind0 {
  3903. contribution = <0x0>;
  3904. trip = <0xca>;
  3905. cooling-device = <0xcb 0x1 0x1>;
  3906. };
  3907.  
  3908. bind1 {
  3909. contribution = <0x0>;
  3910. trip = <0xcc>;
  3911. cooling-device = <0xcb 0x2 0x2>;
  3912. };
  3913.  
  3914. bind2 {
  3915. contribution = <0x0>;
  3916. trip = <0xcd>;
  3917. cooling-device = <0xcb 0x3 0x3>;
  3918. };
  3919. };
  3920. };
  3921. };
  3922.  
  3923. keyboard {
  3924. compatible = "allwinner,keyboard_1200mv";
  3925. reg = <0x0 0x5070800 0x0 0x400>;
  3926. interrupts = <0x0 0x10 0x0>;
  3927. status = "okay";
  3928. key_cnt = <0x5>;
  3929. key0 = <0x73 0x73>;
  3930. key1 = <0xeb 0x72>;
  3931. key2 = <0x14a 0x8b>;
  3932. key3 = <0x1a4 0x1c>;
  3933. key4 = <0x208 0x66>;
  3934. };
  3935.  
  3936. eth@05020000 {
  3937. compatible = "allwinner,sunxi-gmac";
  3938. reg = <0x0 0x5020000 0x0 0x10000 0x0 0x3000030 0x0 0x4>;
  3939. interrupts = <0x0 0xc 0x4>;
  3940. interrupt-names = "gmacirq";
  3941. clocks = <0xce>;
  3942. clock-names = "gmac";
  3943. pinctrl-names = "default";
  3944. phy-mode = "rgmii";
  3945. tx-delay = <0x0>;
  3946. rx-delay = <0x0>;
  3947. phy-rst;
  3948. gmac-power0 = "vcc-io";
  3949. gmac-power1 = "axp806_aldo3";
  3950. status = "okay";
  3951. device_type = "gmac0";
  3952. pinctrl-0 = <0xde 0xdf>;
  3953. gmac-power2;
  3954. };
  3955.  
  3956. product {
  3957. device_type = "product";
  3958. version = "100";
  3959. machine = "petrel-p1";
  3960. };
  3961.  
  3962. platform {
  3963. device_type = "platform";
  3964. eraseflag = <0x1>;
  3965. };
  3966.  
  3967. target {
  3968. device_type = "target";
  3969. boot_clock = <0x528>;
  3970. storage_type = <0xffffffff>;
  3971. burn_key = <0x0>;
  3972. dragonboard_test = <0x0>;
  3973. power_mode = <0x0>;
  3974. advert_enable = <0x0>;
  3975. };
  3976.  
  3977. secure {
  3978. device_type = "secure";
  3979. dram_region_mbytes = <0x40>;
  3980. drm_region_mbytes = <0x0>;
  3981. drm_region_start_mbytes = <0x0>;
  3982. };
  3983.  
  3984. power_sply {
  3985. device_type = "power_sply";
  3986. dcdca_vol = <0xf4628>;
  3987. aldo2_vol = <0xf4f24>;
  3988. };
  3989.  
  3990. gpio_bias {
  3991. device_type = "gpio_bias";
  3992. pc_bias = "axp806:bldo2:1800";
  3993. pg_bias = "axp806:bldo3:1800";
  3994. };
  3995.  
  3996. ir_boot_recovery {
  3997. device_type = "ir_boot_recovery";
  3998. status = "disabled";
  3999. ir_work_mode = <0x1>;
  4000. ir_press_times = <0x1>;
  4001. ir_detect_time = <0x7d0>;
  4002. ir_recovery_key_code0 = <0x57>;
  4003. ir_addr_code0 = <0x9f00>;
  4004. };
  4005.  
  4006. card_boot {
  4007. device_type = "card_boot";
  4008. logical_start = <0xa000>;
  4009. sprite_gpio0 = <0xd8 0xb 0x4 0x1 0xffffffff 0xffffffff 0x1>;
  4010. next_work = <0x3>;
  4011. };
  4012.  
  4013. key_boot_recovery {
  4014. device_type = "key_boot_recovery";
  4015. status = "okay";
  4016. press_mode_enable = <0x0>;
  4017. key_work_mode = <0x1>;
  4018. short_press_mode = <0x0>;
  4019. long_press_mode = <0x1>;
  4020. key_press_time = <0x7d0>;
  4021. recovery_key = <0xd8 0xb 0x2 0x0 0xffffffff 0xffffffff 0xffffffff>;
  4022. };
  4023.  
  4024. boot_init_gpio {
  4025. device_type = "boot_init_gpio";
  4026. status = "okay";
  4027. gpio0 = <0xd8 0xb 0x4 0x1 0xffffffff 0xffffffff 0x1>;
  4028. gpio1 = <0xd8 0xb 0x7 0x1 0xffffffff 0xffffffff 0x0>;
  4029. gpio2 = <0x7e 0x7 0x2 0x1 0xffffffff 0xffffffff 0x1>;
  4030. };
  4031.  
  4032. pm_para {
  4033. device_type = "pm_para";
  4034. standby_mode = <0x1>;
  4035. };
  4036.  
  4037. card0_boot_para {
  4038. device_type = "card0_boot_para";
  4039. card_ctrl = <0x0>;
  4040. card_high_speed = <0x1>;
  4041. card_line = <0x4>;
  4042. pinctrl-0 = <0xd9>;
  4043. };
  4044.  
  4045. card2_boot_para {
  4046. device_type = "card2_boot_para";
  4047. card_ctrl = <0x2>;
  4048. card_high_speed = <0x1>;
  4049. card_line = <0x8>;
  4050. pinctrl-0 = <0xda>;
  4051. sdc_ex_dly_used = <0x2>;
  4052. sdc_io_1v8 = <0x1>;
  4053. sdc_tm4_hs400_max_freq = <0x64>;
  4054. sdc_tm4_hs200_max_freq = <0x96>;
  4055. };
  4056.  
  4057. twi_para {
  4058. device_type = "twi_para";
  4059. twi_port = <0x0>;
  4060. pinctrl-0 = <0xdb>;
  4061. };
  4062.  
  4063. uart_para {
  4064. device_type = "uart_para";
  4065. uart_debug_port = <0x0>;
  4066. pinctrl-0 = <0xdc>;
  4067. };
  4068.  
  4069. jtag_para {
  4070. device_type = "jtag_para";
  4071. jtag_enable = <0x0>;
  4072. pinctrl-0 = <0xdd>;
  4073. };
  4074.  
  4075. clock {
  4076. device_type = "clock";
  4077. pll4 = <0x12c>;
  4078. pll6 = <0x258>;
  4079. pll8 = <0x168>;
  4080. pll9 = <0x129>;
  4081. pll10 = <0x108>;
  4082. };
  4083.  
  4084. rtp_para {
  4085. device_type = "rtp_para";
  4086. rtp_used = <0x0>;
  4087. rtp_screen_size = <0x5>;
  4088. rtp_regidity_level = <0x5>;
  4089. rtp_press_threshold_enable = <0x0>;
  4090. rtp_press_threshold = <0x1f40>;
  4091. rtp_sensitive_level = <0xf>;
  4092. rtp_exchange_x_y_flag = <0x0>;
  4093. };
  4094.  
  4095. ctp {
  4096. device_type = "ctp";
  4097. compatible = "allwinner,sun50i-ctp-para";
  4098. status = "disabled";
  4099. ctp_twi_id = <0x0>;
  4100. ctp_twi_addr = <0x5d>;
  4101. ctp_screen_max_x = <0x500>;
  4102. ctp_screen_max_y = <0x320>;
  4103. ctp_revert_x_flag = <0x1>;
  4104. ctp_revert_y_flag = <0x1>;
  4105. ctp_exchange_x_y_flag = <0x1>;
  4106. ctp_int_port = <0x7e 0x7 0x4 0x6 0xffffffff 0xffffffff 0xffffffff>;
  4107. ctp_wakeup = <0x7e 0x7 0x8 0x1 0xffffffff 0xffffffff 0x1>;
  4108. ctp_power_ldo = "vcc-ctp";
  4109. ctp_power_ldo_vol = <0xce4>;
  4110. ctp_power_io;
  4111. };
  4112.  
  4113. ctp_list {
  4114. device_type = "ctp_list";
  4115. compatible = "allwinner,sun50i-ctp-list";
  4116. ctp_det_used = <0x0>;
  4117. ft5x_ts = <0x1>;
  4118. gt82x = <0x1>;
  4119. gslX680 = <0x1>;
  4120. gt9xx_ts = <0x0>;
  4121. gt9xxnew_ts = <0x1>;
  4122. gt811 = <0x1>;
  4123. zet622x = <0x1>;
  4124. aw5306_ts = <0x1>;
  4125. };
  4126.  
  4127. tkey_para {
  4128. device_type = "tkey_para";
  4129. tkey_used = <0x0>;
  4130. tkey_twi_id;
  4131. tkey_twi_addr;
  4132. tkey_int;
  4133. };
  4134.  
  4135. motor_para {
  4136. device_type = "motor_para";
  4137. motor_used = <0x1>;
  4138. motor_shake = <0xf7 0xfffe 0x3 0x1 0xffffffff 0xffffffff 0x1>;
  4139. };
  4140.  
  4141. esm {
  4142. device_type = "esm";
  4143. esm_img_size_addr = <0x0>;
  4144. esm_img_buff_addr = <0x0>;
  4145. };
  4146.  
  4147. pwm16 {
  4148. device_type = "pwm16";
  4149. s_pwm0_used = <0x0>;
  4150. pinctrl-0 = <0x103>;
  4151. pinctrl-1 = <0x104>;
  4152. };
  4153.  
  4154. tvout_para {
  4155. device_type = "tvout_para";
  4156. tvout_used;
  4157. tvout_channel_num;
  4158. tv_en;
  4159. };
  4160.  
  4161. tvin_para {
  4162. device_type = "tvin_para";
  4163. tvin_used;
  4164. tvin_channel_num;
  4165. };
  4166.  
  4167. smc {
  4168. device_type = "smc";
  4169. smc_used;
  4170. smc_rst;
  4171. smc_vppen;
  4172. smc_vppp;
  4173. smc_det;
  4174. smc_vccen;
  4175. smc_sck;
  4176. smc_sda;
  4177. };
  4178.  
  4179. gpio_para {
  4180. device_type = "gpio_para";
  4181. compatible = "allwinner,sunxi-init-gpio";
  4182. gpio_used = <0x1>;
  4183. gpio_num = <0x3>;
  4184. gpio_pin_1 = <0xd8 0xb 0x7 0x1 0xffffffff 0xffffffff 0x1>;
  4185. gpio_pin_2 = <0xd8 0xb 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  4186. gpio_pin_3 = <0x7e 0x3 0x6 0x1 0xffffffff 0x3 0x1>;
  4187. normal_led = "gpio_pin_1";
  4188. standby_led = "gpio_pin_2";
  4189. easy_light_used = <0x1>;
  4190. normal_led_light = <0x1>;
  4191. standby_led_light = <0x1>;
  4192. };
  4193.  
  4194. usbc3 {
  4195. device_type = "usbc3";
  4196. status = "okay";
  4197. usb_drv_vbus_gpio;
  4198. usb_host_init_state = <0x1>;
  4199. usb_regulator_io = "nocare";
  4200. usb_wakeup_suspend = <0x0>;
  4201. };
  4202.  
  4203. serial_feature {
  4204. device_type = "serial_feature";
  4205. sn_filename = "sn.txt";
  4206. };
  4207.  
  4208. gsensor {
  4209. device_type = "gsensor";
  4210. compatible = "allwinner,sun50i-gsensor-para";
  4211. status = "disabled";
  4212. gsensor_twi_id = <0x1>;
  4213. gsensor_twi_addr = <0x18>;
  4214. gsensor_int1 = <0x7e 0x0 0x9 0x6 0x1 0xffffffff 0xffffffff>;
  4215. gsensor_int2;
  4216. gsensor_vcc_io = "vcc-deviceio";
  4217. gsensor_vcc_io_val = <0xc1c>;
  4218. };
  4219.  
  4220. gsensor_list_para {
  4221. device_type = "gsensor_list_para";
  4222. compatible = "allwinner,sun50i-gsensor-list-para";
  4223. gsensor_det_used = <0x0>;
  4224. lsm9ds0_acc_mag = <0x1>;
  4225. bma250 = <0x1>;
  4226. mma8452 = <0x1>;
  4227. mma7660 = <0x1>;
  4228. mma865x = <0x1>;
  4229. afa750 = <0x1>;
  4230. lis3de_acc = <0x1>;
  4231. lis3dh_acc = <0x1>;
  4232. kxtik = <0x1>;
  4233. dmard10 = <0x0>;
  4234. dmard06 = <0x1>;
  4235. mxc622x = <0x1>;
  4236. fxos8700 = <0x1>;
  4237. lsm303d = <0x0>;
  4238. };
  4239.  
  4240. 3g_para {
  4241. device_type = "3g_para";
  4242. 3g_used = <0x0>;
  4243. 3g_usbc_num = <0x2>;
  4244. 3g_uart_num = <0x0>;
  4245. bb_vbat = <0xd8 0xb 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4246. bb_host_wake = <0xd8 0xc 0x0 0x1 0xffffffff 0xffffffff 0x0>;
  4247. bb_on = <0xd8 0xc 0x1 0x1 0xffffffff 0xffffffff 0x0>;
  4248. bb_pwr_on = <0xd8 0xc 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4249. bb_wake = <0xd8 0xc 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  4250. bb_rf_dis = <0xd8 0xc 0x5 0x1 0xffffffff 0xffffffff 0x0>;
  4251. bb_rst = <0xd8 0xc 0x6 0x1 0xffffffff 0xffffffff 0x0>;
  4252. 3g_int;
  4253. };
  4254.  
  4255. gy_para {
  4256. device_type = "gy_para";
  4257. compatible = "allwinner,sun50i-gyr_sensors-para";
  4258. gy_used = <0x0>;
  4259. gy_twi_id = <0x2>;
  4260. gy_twi_addr = <0x6a>;
  4261. gy_int1 = <0x7e 0x0 0xa 0x6 0x1 0xffffffff 0xffffffff>;
  4262. gy_int2;
  4263. };
  4264.  
  4265. gy_list_para {
  4266. device_type = "gy_list_para";
  4267. compatible = "allwinner,sun50i-gyr_sensors-list-para";
  4268. gy_det_used = <0x1>;
  4269. lsm9ds0_gyr = <0x1>;
  4270. l3gd20_gyr = <0x0>;
  4271. bmg160_gyr = <0x1>;
  4272. };
  4273.  
  4274. ls_para {
  4275. device_type = "ls_para";
  4276. compatible = "allwinner,sun50i-lsensors-para";
  4277. ls_used = <0x0>;
  4278. ls_twi_id = <0x2>;
  4279. ls_twi_addr = <0x23>;
  4280. ls_int = <0x7e 0x0 0xc 0x6 0x1 0xffffffff 0xffffffff>;
  4281. };
  4282.  
  4283. ls_list_para {
  4284. device_type = "ls_list_para";
  4285. compatible = "allwinner,sun50i-lsensors-list-para";
  4286. ls_det_used = <0x1>;
  4287. ltr_501als = <0x1>;
  4288. jsa1212 = <0x0>;
  4289. jsa1127 = <0x1>;
  4290. };
  4291.  
  4292. compass_para {
  4293. device_type = "compass_para";
  4294. compatible = "allwinner,sun50i-compass-para";
  4295. compass_used = <0x0>;
  4296. compass_twi_id = <0x2>;
  4297. compass_twi_addr = <0xd>;
  4298. compass_int = <0x7e 0x0 0xb 0x6 0x1 0xffffffff 0xffffffff>;
  4299. };
  4300.  
  4301. compass_list_para {
  4302. device_type = "compass_list_para";
  4303. compatible = "allwinner,sun50i-compass-list-para";
  4304. compass_det_used = <0x1>;
  4305. lsm9ds0 = <0x1>;
  4306. lsm303d = <0x0>;
  4307. akm8963 = <0x1>;
  4308. };
  4309.  
  4310. s_rsb0 {
  4311. device_type = "s_rsb0";
  4312. status = "disabled";
  4313. pinctrl-0 = <0x10b>;
  4314. };
  4315.  
  4316. box_standby_led {
  4317. device_type = "box_standby_led";
  4318. gpio0 = <0xd8 0xb 0x7 0x1 0xffffffff 0xffffffff 0x0>;
  4319. gpio1 = <0xd8 0xb 0x4 0x1 0xffffffff 0xffffffff 0x1>;
  4320. };
  4321.  
  4322. gpio_power_key {
  4323. device_type = "gpio_power_key";
  4324. compatible = "allwinner,sunxi-gpio-power-key";
  4325. status = "disabled";
  4326. key_io = <0xd8 0xb 0x5 0x0 0xffffffff 0xffffffff 0x0>;
  4327. trigger_mode = <0x1>;
  4328. };
  4329. };
  4330.  
  4331. aliases {
  4332. serial0 = "/soc@03000000/uart@05000000", "/soc@03000000/uart@05000000";
  4333. serial1 = "/soc@03000000/uart@05000400", "/soc@03000000/uart@05000400";
  4334. serial2 = "/soc@03000000/uart@05000800", "/soc@03000000/uart@05000800";
  4335. serial3 = "/soc@03000000/uart@05000c00", "/soc@03000000/uart@05000c00";
  4336. twi0 = "/soc@03000000/twi@0x05002000", "/soc@03000000/twi@0x05002000";
  4337. twi1 = "/soc@03000000/twi@0x05002400", "/soc@03000000/twi@0x05002400";
  4338. twi2 = "/soc@03000000/twi@0x05002800", "/soc@03000000/twi@0x05002800";
  4339. twi3 = "/soc@03000000/twi@0x05002c00", "/soc@03000000/twi@0x05002c00";
  4340. spi0 = "/soc@03000000/spi@05010000", "/soc@03000000/spi@05010000";
  4341. spi1 = "/soc@03000000/spi@05011000", "/soc@03000000/spi@05011000";
  4342. pcie = "/soc@03000000/pcie@0x05400000", "/soc@03000000/pcie@0x05400000";
  4343. scr0 = "/soc@03000000/smartcard@0x05005000", "/soc@03000000/smartcard@0x05005000";
  4344. scr1 = "/soc@03000000/smartcard@0x05005400", "/soc@03000000/smartcard@0x05005400";
  4345. gmac0 = "/soc@03000000/eth@05020000", "/soc@03000000/eth@05020000";
  4346. global_timer0 = "/soc@03000000/timer@03009000", "/soc@03000000/timer@03009000";
  4347. mmc0 = "/soc@03000000/sdmmc@04020000", "/soc@03000000/sdmmc@04020000";
  4348. mmc2 = "/soc@03000000/sdmmc@04022000", "/soc@03000000/sdmmc@04022000";
  4349. nand0 = "/soc@03000000/nand0@04011000", "/soc@03000000/nand0@04011000";
  4350. disp = "/soc@03000000/disp@01000000", "/soc@03000000/disp@01000000";
  4351. lcd0 = "/soc@03000000/lcd0@01c0c000", "/soc@03000000/lcd0@01c0c000";
  4352. hdmi = "/soc@03000000/hdmi@06000000", "/soc@03000000/hdmi@06000000";
  4353. pwm = "/soc@03000000/pwm@0300a000", "/soc@03000000/pwm@0300a000";
  4354. pwm0 = "/soc@03000000/pwm0@0300a000", "/soc@03000000/pwm0@0300a000";
  4355. pwm1 = "/soc@03000000/pwm1@0300a000", "/soc@03000000/pwm1@0300a000";
  4356. tv0 = "/soc@03000000/tv0@01c94000", "/soc@03000000/tv0@01c94000";
  4357. s_pwm = "/soc@03000000/s_pwm@07020c00", "/soc@03000000/s_pwm@07020c00";
  4358. spwm0 = "/soc@03000000/spwm0@07020c00", "/soc@03000000/spwm0@07020c00";
  4359. boot_disp = "/soc@03000000/boot_disp", "/soc@03000000/boot_disp";
  4360. charger0 = "/soc@03000000/pmu@0/charger@0", "/soc@03000000/pmu@0/charger@0";
  4361. regulator0 = "/soc@03000000/pmu@0/regulator@0", "/soc@03000000/pmu@0/regulator@0";
  4362. };
  4363.  
  4364. chosen {
  4365. bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  4366. linux,initrd-start = <0x0 0x0>;
  4367. linux,initrd-end = <0x0 0x0>;
  4368. };
  4369.  
  4370. cpus {
  4371. #address-cells = <0x2>;
  4372. #size-cells = <0x0>;
  4373.  
  4374. cpu@0 {
  4375. device_type = "cpu";
  4376. compatible = "arm,cortex-a53", "arm,armv8";
  4377. reg = <0x0 0x0>;
  4378. enable-method = "psci";
  4379. cpufreq_tbl = <0x75300 0xafc80 0xc7380 0xd8cc0 0x107ac0 0x142440 0x16b480 0x1b7740>;
  4380. clock-latency = <0x1e8480>;
  4381. clock-frequency = <0x4ead9a00>;
  4382. cpu-idle-states = <0xd0 0xd1 0xd2>;
  4383. };
  4384.  
  4385. cpu@1 {
  4386. device_type = "cpu";
  4387. compatible = "arm,cortex-a53", "arm,armv8";
  4388. reg = <0x0 0x1>;
  4389. enable-method = "psci";
  4390. clock-frequency = <0x4ead9a00>;
  4391. cpu-idle-states = <0xd0 0xd1 0xd2>;
  4392. };
  4393.  
  4394. cpu@2 {
  4395. device_type = "cpu";
  4396. compatible = "arm,cortex-a53", "arm,armv8";
  4397. reg = <0x0 0x2>;
  4398. enable-method = "psci";
  4399. clock-frequency = <0x4ead9a00>;
  4400. cpu-idle-states = <0xd0 0xd1 0xd2>;
  4401. };
  4402.  
  4403. cpu@3 {
  4404. device_type = "cpu";
  4405. compatible = "arm,cortex-a53", "arm,armv8";
  4406. reg = <0x0 0x3>;
  4407. enable-method = "psci";
  4408. clock-frequency = <0x4ead9a00>;
  4409. cpu-idle-states = <0xd0 0xd1 0xd2>;
  4410. };
  4411.  
  4412. idle-states {
  4413. entry-method = "arm,psci";
  4414.  
  4415. cpu-sleep-0 {
  4416. compatible = "arm,idle-state";
  4417. arm,psci-suspend-param = <0x10000>;
  4418. entry-latency-us = <0xfa0>;
  4419. exit-latency-us = <0x2710>;
  4420. min-residency-us = <0x3a98>;
  4421. linux,phandle = <0xd0>;
  4422. phandle = <0xd0>;
  4423. };
  4424.  
  4425. cluster-sleep-0 {
  4426. compatible = "arm,idle-state";
  4427. arm,psci-suspend-param = <0x1010000>;
  4428. entry-latency-us = <0xc350>;
  4429. exit-latency-us = <0x186a0>;
  4430. min-residency-us = <0x3d090>;
  4431. linux,phandle = <0xd1>;
  4432. phandle = <0xd1>;
  4433. };
  4434.  
  4435. sys-sleep-0 {
  4436. compatible = "arm,idle-state";
  4437. arm,psci-suspend-param = <0x2010000>;
  4438. entry-latency-us = <0x186a0>;
  4439. exit-latency-us = <0x1e8480>;
  4440. min-residency-us = <0x44aa20>;
  4441. linux,phandle = <0xd2>;
  4442. phandle = <0xd2>;
  4443. };
  4444. };
  4445. };
  4446.  
  4447. psci {
  4448. compatible = "arm,psci-0.2";
  4449. method = "smc";
  4450. psci_version = <0x84000000>;
  4451. cpu_suspend = <0xc4000001>;
  4452. cpu_off = <0x84000002>;
  4453. cpu_on = <0xc4000003>;
  4454. affinity_info = <0xc4000004>;
  4455. migrate = <0xc4000005>;
  4456. migrate_info_type = <0x84000006>;
  4457. migrate_info_up_cpu = <0xc4000007>;
  4458. system_off = <0x84000008>;
  4459. system_reset = <0x84000009>;
  4460. };
  4461.  
  4462. n_brom {
  4463. compatible = "allwinner,n-brom";
  4464. reg = <0x0 0x0 0x0 0xa000>;
  4465. };
  4466.  
  4467. s_brom {
  4468. compatible = "allwinner,s-brom";
  4469. reg = <0x0 0x0 0x0 0x10000>;
  4470. };
  4471.  
  4472. sram_ctrl {
  4473. device_type = "sram_ctrl";
  4474. compatible = "allwinner,sram_ctrl";
  4475. reg = <0x0 0x3000000 0x0 0x100>;
  4476. };
  4477.  
  4478. sram_a1 {
  4479. compatible = "allwinner,sram_a1";
  4480. reg = <0x0 0x20000 0x0 0x8000>;
  4481. };
  4482.  
  4483. sram_a2 {
  4484. compatible = "allwinner,sram_a2";
  4485. reg = <0x0 0x100000 0x0 0x14000>;
  4486. };
  4487.  
  4488. prcm {
  4489. compatible = "allwinner,prcm";
  4490. reg = <0x0 0x1f01400 0x0 0x400>;
  4491. };
  4492.  
  4493. cpuscfg {
  4494. compatible = "allwinner,cpuscfg";
  4495. reg = <0x0 0x1f01c00 0x0 0x400>;
  4496. };
  4497.  
  4498. ion {
  4499. compatible = "allwinner,sunxi-ion";
  4500.  
  4501. system {
  4502. type = <0x0>;
  4503. };
  4504.  
  4505. system_contig {
  4506. type = <0x1>;
  4507. };
  4508.  
  4509. cma {
  4510. type = <0x4>;
  4511. };
  4512.  
  4513. secure {
  4514. type = <0x6>;
  4515. };
  4516. };
  4517.  
  4518. dram {
  4519. compatible = "allwinner,dram";
  4520. clocks = <0xd3>;
  4521. clock-names = "pll_ddr";
  4522. dram_clk = <0x384>;
  4523. dram_type = <0x7>;
  4524. dram_zq = <0x3b3bfb>;
  4525. dram_odt_en = <0x31>;
  4526. dram_para1 = <0x30fa>;
  4527. dram_para2 = <0x4000000>;
  4528. dram_mr0 = <0x1c70>;
  4529. dram_mr1 = <0x40>;
  4530. dram_mr2 = <0x18>;
  4531. dram_mr3 = <0x1>;
  4532. dram_tpr0 = <0x48a192>;
  4533. dram_tpr1 = <0x1b1a94b>;
  4534. dram_tpr2 = <0x61043>;
  4535. dram_tpr3 = <0x78787896>;
  4536. dram_tpr4 = <0x0>;
  4537. dram_tpr5 = <0x0>;
  4538. dram_tpr6 = "\t\t\t";
  4539. dram_tpr7 = <0x4d462a3e>;
  4540. dram_tpr8 = <0x0>;
  4541. dram_tpr9 = <0x0>;
  4542. dram_tpr10 = <0x0>;
  4543. dram_tpr11 = <0x440000>;
  4544. dram_tpr12 = <0x0>;
  4545. dram_tpr13 = <0x0>;
  4546. device_type = "dram";
  4547. dram_mr4 = <0x0>;
  4548. dram_mr5 = <0x400>;
  4549. dram_mr6 = <0x848>;
  4550. };
  4551.  
  4552. memory@40000000 {
  4553. device_type = "memory";
  4554. reg = <0x0 0x40000000 0x0 0x20000000>;
  4555. };
  4556.  
  4557. interrupt-controller@03020000 {
  4558. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  4559. #interrupt-cells = <0x3>;
  4560. #address-cells = <0x0>;
  4561. device_type = "gic";
  4562. interrupt-controller;
  4563. reg = <0x0 0x3021000 0x0 0x1000 0x0 0x3022000 0x0 0x2000 0x0 0x3024000 0x0 0x2000 0x0 0x3026000 0x0 0x2000>;
  4564. interrupts = <0x1 0x9 0xf04>;
  4565. linux,phandle = <0x1>;
  4566. phandle = <0x1>;
  4567. };
  4568.  
  4569. sunxi-sid@03006000 {
  4570. compatible = "allwinner,sunxi-sid";
  4571. device_type = "sid";
  4572. reg = <0x0 0x3006000 0x0 0x1000>;
  4573. };
  4574.  
  4575. sunxi-chipid@03006200 {
  4576. compatible = "allwinner,sunxi-chipid";
  4577. device_type = "chipid";
  4578. reg = <0x0 0x3006200 0x0 0x200>;
  4579. };
  4580.  
  4581. timer {
  4582. compatible = "arm,armv8-timer";
  4583. interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>;
  4584. clock-frequency = <0x16e3600>;
  4585. };
  4586.  
  4587. pmu {
  4588. compatible = "arm,armv8-pmuv3";
  4589. interrupts = <0x0 0x8c 0x4 0x0 0x8d 0x4 0x0 0x8e 0x4 0x0 0x8f 0x4>;
  4590. };
  4591.  
  4592. dvfs_table {
  4593. compatible = "allwinner,dvfs_table";
  4594. multi-vf-table;
  4595.  
  4596. dvfs_table_0 {
  4597. max_freq = <0x6b49d200>;
  4598. min_freq = <0x1c9c3800>;
  4599. lv_count = <0x8>;
  4600. lv1_freq = <0x6b49d200>;
  4601. lv1_volt = <0x488>;
  4602. lv2_freq = <0x58b11400>;
  4603. lv2_volt = <0x424>;
  4604. lv3_freq = <0x4ead9a00>;
  4605. lv3_volt = <0x3e8>;
  4606. lv4_freq = "@_~";
  4607. lv4_volt = <0x3ac>;
  4608. lv5_freq = <0x34edce00>;
  4609. lv5_volt = <0x370>;
  4610. lv6_freq = <0x0>;
  4611. lv6_volt = <0x370>;
  4612. lv7_freq = <0x0>;
  4613. lv7_volt = <0x370>;
  4614. lv8_freq = <0x0>;
  4615. lv8_volt = <0x370>;
  4616. device_type = "dvfs_table_0";
  4617. };
  4618.  
  4619. dvfs_table_1 {
  4620. max_freq = <0x6b49d200>;
  4621. min_freq = <0x1c9c3800>;
  4622. lv_count = <0x8>;
  4623. lv1_freq = <0x6b49d200>;
  4624. lv1_volt = <0x44c>;
  4625. lv2_freq = <0x58b11400>;
  4626. lv2_volt = <0x3e8>;
  4627. lv3_freq = <0x4ead9a00>;
  4628. lv3_volt = <0x3ac>;
  4629. lv4_freq = "@_~";
  4630. lv4_volt = <0x370>;
  4631. lv5_freq = <0x34edce00>;
  4632. lv5_volt = <0x334>;
  4633. lv6_freq = <0x0>;
  4634. lv6_volt = <0x334>;
  4635. lv7_freq = <0x0>;
  4636. lv7_volt = <0x334>;
  4637. lv8_freq = <0x0>;
  4638. lv8_volt = <0x334>;
  4639. device_type = "dvfs_table_1";
  4640. };
  4641.  
  4642. dvfs_table_2 {
  4643. max_freq = <0x6b49d200>;
  4644. min_freq = <0x1c9c3800>;
  4645. lv_count = <0x8>;
  4646. lv1_freq = <0x6b49d200>;
  4647. lv1_volt = <0x44c>;
  4648. lv2_freq = <0x58b11400>;
  4649. lv2_volt = <0x3e8>;
  4650. lv3_freq = <0x4ead9a00>;
  4651. lv3_volt = <0x3ac>;
  4652. lv4_freq = "@_~";
  4653. lv4_volt = <0x370>;
  4654. lv5_freq = <0x34edce00>;
  4655. lv5_volt = <0x334>;
  4656. lv6_freq = <0x0>;
  4657. lv6_volt = <0x334>;
  4658. lv7_freq = <0x0>;
  4659. lv7_volt = <0x334>;
  4660. lv8_freq = <0x0>;
  4661. lv8_volt = <0x334>;
  4662. device_type = "dvfs_table_2";
  4663. };
  4664. };
  4665.  
  4666. dramfreq {
  4667. compatible = "allwinner,sunxi-dramfreq";
  4668. reg = <0x0 0x4002000 0x0 0x1000 0x0 0x4003000 0x0 0x3000 0x0 0x3001000 0x0 0x1000>;
  4669. interrupts = <0x0 0x21 0x4>;
  4670. clocks = <0xd3>;
  4671. status = "okay";
  4672. };
  4673.  
  4674. uboot {
  4675. };
  4676.  
  4677. iommu@030f0000 {
  4678. compatible = "allwinner,sunxi-iommu";
  4679. reg = <0x0 0x30f0000 0x0 0x1000>;
  4680. interrupts = <0x0 0x39 0x4>;
  4681. interrupt-names = "iommu-irq";
  4682. clocks = <0xd4>;
  4683. clock-names = "iommu";
  4684. #iommu-cells = <0x2>;
  4685. status = "okay";
  4686. linux,phandle = <0x19>;
  4687. phandle = <0x19>;
  4688. };
  4689.  
  4690. gpu@0x01800000 {
  4691. device_type = "gpu";
  4692. compatible = "arm,mali-t720", "arm,mali-midgard";
  4693. reg = <0x0 0x1800000 0x0 0x4000>;
  4694. interrupts = <0x0 0x53 0x4 0x0 0x54 0x4 0x0 0x55 0x4>;
  4695. interrupt-names = "GPU", "JOB", "MMU";
  4696. clocks = <0xd5 0xd6>;
  4697. clock-names = "clk_parent", "clk_mali";
  4698. operating-points = <0xb8920 0xfde80 0x98580 0xe7ef0 0x8ca00 0xe30d0 0x83d60 0xde2b0 0x7b0c0 0xd9490 0x6f540 0xd4670 0x69780 0xd1f60 0x668a0 0xcf850 0x639c0 0xcd140 0x5dc00 0xcaa30 0x57e40 0xc8320 0x52080 0xc5c10 0x4c2c0 0xc5c10 0x40740 0xc5c10 0x34bc0 0xc5c10>;
  4699. gpu_idle = <0x0>;
  4700. dvfs_status = <0x1>;
  4701. temp_ctrl_status = <0x1>;
  4702. scene_ctrl_status = <0x1>;
  4703. max_normal_level = <0xd>;
  4704. };
  4705.  
  4706. wlan {
  4707. compatible = "allwinner,sunxi-wlan";
  4708. wlan_busnum = <0x1>;
  4709. wlan_usbnum = <0x3>;
  4710. wlan_power;
  4711. wlan_io_regulator = "axp806_bldo3";
  4712. wlan_en;
  4713. status = "disabled";
  4714. device_type = "wlan";
  4715. wlan_regon = <0xd8 0xc 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4716. wlan_hostwake = <0xd8 0xc 0x0 0x0 0xffffffff 0xffffffff 0x0>;
  4717. };
  4718.  
  4719. bt {
  4720. compatible = "allwinner,sunxi-bt";
  4721. clocks = <0xd7>;
  4722. bt_power = "vcc-wifi";
  4723. bt_io_regulator = "vcc-wifi-io";
  4724. status = "disabled";
  4725. device_type = "bt";
  4726. bt_rst_n = <0xd8 0xc 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  4727. };
  4728.  
  4729. btlpm {
  4730. compatible = "allwinner,sunxi-btlpm";
  4731. uart_index = <0x1>;
  4732. status = "disabled";
  4733. device_type = "btlpm";
  4734. bt_hostwake_enable = <0x1>;
  4735. bt_wake = <0xd8 0xc 0x2 0x1 0xffffffff 0xffffffff 0x1>;
  4736. bt_hostwake = <0xd8 0xc 0x1 0x0 0xffffffff 0xffffffff 0x0>;
  4737. };
  4738. };
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