Lab7

module lab7(input L, R, H,F, clk, rst,output LA, LB, LC,LD, RA, RB, RC,RD);
wire scan_clk;
reg[23:0] div;
reg [3:0] state;
parameter IDLE=0,R1=1,R2=2,R3=3,R4=4,L1=5,L2=6,L3=7,L4=8,F1=9,F2=10,F3=11,F4=12,ALL=13;

always @(posedge clk, negedge rst)
        begin
            if(!rst) begin
                div <= 24'b0;
            end
            else begin
                div <= div + 1;
            end
        end

    assign scan_clk = div[23];// 0.67s

always@(posedge scan_clk)
begin
    if(!rst)
       state<=IDLE;
    case (state)

    IDLE:begin
        if(H|R&L)
           state<=ALL;
        else if(~H&F&~R&~L)
           state<=F1;
        else if(~H&~F&R&~L)
           state<=R1;
        else if(~H&~F&~R&L)
           state<=L1;
        else
        state<=IDLE;
    end
    R1:
    begin
        if(H) state<=ALL;
        else if(~H&~F&R&~L)state<=R2;else state<=IDLE;
    end
    R2:
    begin
        if(H) state<=ALL;
        else if(~H&~F&R&~L)state<=R3;else state<=IDLE;
    end
    R3:
    begin
        if(H) state<=ALL;
        else if(~H&~F&R&~L)state<=R4;else state<=IDLE;
    end
    R4:
    begin
        if(H) state<=ALL;
        else state<=IDLE;
    end
    L1:
    begin
        if(H) state<=ALL;
        else if(~H&~F&~R&L)state<=L2;else state<=IDLE;
    end
    L2:
    begin
        if(H) state<=ALL;
        else if(~H&~F&~R&L)state<=L3;else state<=IDLE;
    end
    L3:
    begin
        if(H) state<=ALL;
        else if(~H&~F&~R&L)state<=L4;else state<=IDLE;
    end
    L4:
    begin
        if(H) state<=ALL;
        else state<=IDLE;
    end
    F1:
    begin
        if(H) state<=ALL;
        else if(~H&F&~R&~L)state<=F2;else state<=IDLE;
    end
    F2:
    begin
        if(H) state<=ALL;
        else if(~H&F&~R&~L)state<=F3;else state<=IDLE;
    end
    F3:
    begin
        if(H) state<=ALL;
        else if(~H&F&~R&~L)state<=ALL;else state<=IDLE;
    end
    F4:
    begin
        if(H) state<=ALL;
        else state<=IDLE;
    end
    ALL:state<=IDLE;
    default:state<=IDLE;
    endcase
end
    assign RA=~((state==R1)|(state==R2)|(state==R3)|(state==R4)|(state==ALL)|
               (state==F1)|(state==F2)|(state==F3)|(state==F4));
    assign RB=~((state==R2)|(state==R3)|(state==R4)|(state==ALL)|
               (state==F2)|(state==F3)|(state==F4));
    assign RC=~((state==R3)|(state==R4)|(state==ALL)|(state==F3)|(state==F4));

    assign RD=~((state==R4)|(state==ALL)|(state==F4));

    assign LA=~((state==L1)|(state==L2)|(state==L3)|(state==L4)|(state==ALL)|
               (state==F1)|(state==F2)|(state==F3)|(state==F4));
    assign LB=~((state==L2)|(state==L3)|(state==L4)|(state==ALL)|
               (state==F2)|(state==F3)|(state==F4));
    assign LC=~((state==L3)|(state==L4)|(state==ALL)|(state==F3)|(state==F4));

    assign LD=~((state==L4)|(state==ALL)|(state==F4));




endmodule