ECE 362 LAB05

;***********************************************************************
; ECE 362 - Logic Analyzer Experiment
;
; Skeleton file for Step 3
;***********************************************************************
;
; Completed by: < your name >
;               < your lab partners name >
;               < your class number >
;               < your lab division >
;
;***********************************************************************
;
; Exercise 3 for Logic Analyzer Experiment
;
; Program: Square Wave Generator
;
; Purpose: Produces a square wave on Pin 0 of Port A
;
; Starting Address: 0800
;
; Note: This program is an infinite loop
;
;***********************************************************************

ddra    equ $0002
porta   equ $0000

    org $0800
        lds     #$0C00
    movb    #$FF,ddra       ; Initialize Port A for Output
    movb    #$00,porta      ; Set PA0 = 0
loop    bsr delay           ; Wait 6 ms
    com porta           ; Toggle PA0
    bra loop

;***********************************************************************
;
; Subroutine
;
; delay -- Produce a delay of 6 ms
;
; Note: The boards used in lab for this experiment run at 12.5 MHz.

delay              ; 5 + 10x + 5 = 75000
    ldx #$0000 ; 2 cy
    nop        ;+3 cy
    nop
    nop
loopo           ; 7498 loops for 74980 cy
    orcc #%11110000 ; 1 cy
    cpx #$1D4A  ; 2 cy
    beq done    ; 1 cy
    leax 1,x    ; 2 cy
    nop         ; 1 cy
    bra loopo   ; 3 cy
done
    nop     ; +4 cy
    nop
    nop
    nop
    rts         ; 5 cy

    end   ;5 + (10x) + 9 (+1) = 75,000