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  1. -----------------------------------------------------------------------------------------------------
  2. | Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
  3. | Date : Tue Feb 2 07:30:32 2021
  4. | Host : glsvmlin.ini.cmu.edu running 64-bit unknown
  5. | Command : report_utilization -hierarchical -file nexys4ddr_utilization_hierarchical_place.rpt
  6. | Design : nexys4ddr
  7. | Device : 7a100tcsg324-1
  8. | Design State : Fully Placed
  9. -----------------------------------------------------------------------------------------------------
  10.  
  11. Utilization Design Information
  12.  
  13. Table of Contents
  14. -----------------
  15. 1. Utilization by Hierarchy
  16.  
  17. 1. Utilization by Hierarchy
  18. ---------------------------
  19.  
  20. +------------------------------------------------------------+-------------------------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
  21. | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
  22. +------------------------------------------------------------+-------------------------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
  23. | nexys4ddr | (top) | 24348 | 21193 | 3150 | 5 | 12895 | 61 | 7 | 0 |
  24. | (nexys4ddr) | (top) | 7527 | 6493 | 1032 | 2 | 6243 | 60 | 3 | 0 |
  25. | ExampleRocketSystem | ExampleRocketSystem | 16968 | 14847 | 2118 | 3 | 6652 | 1 | 4 | 0 |
  26. | (ExampleRocketSystem) | ExampleRocketSystem | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 |
  27. | clint | CLINT | 34 | 34 | 0 | 0 | 129 | 0 | 0 | 0 |
  28. | debug_1 | TLDebugModule | 119 | 119 | 0 | 0 | 0 | 0 | 0 | 0 |
  29. | dmInner | TLDebugModuleInnerAsync | 119 | 119 | 0 | 0 | 0 | 0 | 0 | 0 |
  30. | dmInner | TLDebugModuleInner | 119 | 119 | 0 | 0 | 0 | 0 | 0 | 0 |
  31. | ibus_intsink | IntSyncAsyncCrossingSink | 5 | 2 | 0 | 3 | 3 | 0 | 0 | 0 |
  32. | chain | SynchronizerShiftReg_w4_d3 | 5 | 2 | 0 | 3 | 3 | 0 | 0 | 0 |
  33. | output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
  34. | output_chain_1 | NonSyncResetSynchronizerPrimitiveShiftReg_d3_63 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
  35. | output_chain_2 | NonSyncResetSynchronizerPrimitiveShiftReg_d3_64 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
  36. | intsource | IntSyncCrossingSource_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
  37. | reg_ | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
  38. | intsource_1 | IntSyncCrossingSource_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  39. | reg_ | AsyncResetRegVec_w1_i0_62 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  40. | intsource_2 | IntSyncCrossingSource_1_0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  41. | reg_ | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  42. | intsource_3 | IntSyncCrossingSource_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 |
  43. | reg_ | AsyncResetRegVec_w4_i0 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 |
  44. | plicDomainWrapper | ClockSinkDomain | 110 | 110 | 0 | 0 | 90 | 0 | 0 | 0 |
  45. | plic | TLPLIC | 110 | 110 | 0 | 0 | 90 | 0 | 0 | 0 |
  46. | (plic) | TLPLIC | 41 | 41 | 0 | 0 | 39 | 0 | 0 | 0 |
  47. | gateways_gateway | LevelGateway | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
  48. | gateways_gateway_1 | LevelGateway_60 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  49. | gateways_gateway_2 | LevelGateway_61 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  50. | out_back | Queue_37 | 68 | 68 | 0 | 0 | 48 | 0 | 0 | 0 |
  51. | subsystem_cbus | PeripheryBus_1 | 1788 | 1612 | 176 | 0 | 444 | 0 | 0 | 0 |
  52. | atomics | TLAtomicAutomata_1 | 419 | 419 | 0 | 0 | 204 | 0 | 0 | 0 |
  53. | buffer | TLBuffer_4 | 387 | 243 | 144 | 0 | 6 | 0 | 0 | 0 |
  54. | bundleIn_0_d_q | Queue_22_59 | 130 | 70 | 60 | 0 | 3 | 0 | 0 | 0 |
  55. | bundleOut_0_a_q | Queue_21 | 257 | 173 | 84 | 0 | 3 | 0 | 0 | 0 |
  56. | coupler_to_bootrom | TLInterconnectCoupler_11 | 481 | 481 | 0 | 0 | 31 | 0 | 0 | 0 |
  57. | fragmenter | TLFragmenter_3 | 481 | 481 | 0 | 0 | 31 | 0 | 0 | 0 |
  58. | (fragmenter) | TLFragmenter_3 | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 |
  59. | repeater | Repeater_3 | 480 | 480 | 0 | 0 | 22 | 0 | 0 | 0 |
  60. | coupler_to_clint | TLInterconnectCoupler_8 | 128 | 128 | 0 | 0 | 34 | 0 | 0 | 0 |
  61. | fragmenter | TLFragmenter_1 | 128 | 128 | 0 | 0 | 34 | 0 | 0 | 0 |
  62. | (fragmenter) | TLFragmenter_1 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 |
  63. | repeater | Repeater_1 | 125 | 125 | 0 | 0 | 25 | 0 | 0 | 0 |
  64. | coupler_to_debug | TLInterconnectCoupler_9 | 116 | 116 | 0 | 0 | 30 | 0 | 0 | 0 |
  65. | fragmenter | TLFragmenter_2 | 116 | 116 | 0 | 0 | 30 | 0 | 0 | 0 |
  66. | (fragmenter) | TLFragmenter_2 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 |
  67. | repeater | Repeater_2 | 113 | 113 | 0 | 0 | 21 | 0 | 0 | 0 |
  68. | coupler_to_plic | TLInterconnectCoupler_7 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 |
  69. | fragmenter | TLFragmenter | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 |
  70. | (fragmenter) | TLFragmenter | 7 | 7 | 0 | 0 | 9 | 0 | 0 | 0 |
  71. | repeater | Repeater | 25 | 25 | 0 | 0 | 35 | 0 | 0 | 0 |
  72. | fixer | TLFIFOFixer_3 | 22 | 22 | 0 | 0 | 40 | 0 | 0 | 0 |
  73. | out_xbar | TLXbar_5 | 99 | 99 | 0 | 0 | 18 | 0 | 0 | 0 |
  74. | wrapped_error_device | ErrorDeviceWrapper | 104 | 72 | 32 | 0 | 37 | 0 | 0 | 0 |
  75. | buffer | TLBuffer_5 | 63 | 31 | 32 | 0 | 6 | 0 | 0 | 0 |
  76. | bundleIn_0_d_q | Queue_22 | 46 | 26 | 20 | 0 | 3 | 0 | 0 | 0 |
  77. | bundleOut_0_a_q | Queue_24 | 17 | 5 | 12 | 0 | 3 | 0 | 0 | 0 |
  78. | error | TLError | 41 | 41 | 0 | 0 | 31 | 0 | 0 | 0 |
  79. | (error) | TLError | 9 | 9 | 0 | 0 | 18 | 0 | 0 | 0 |
  80. | a | Queue_23 | 32 | 32 | 0 | 0 | 13 | 0 | 0 | 0 |
  81. | subsystem_fbus_buffer | TLBuffer_2 | 253 | 101 | 152 | 0 | 6 | 0 | 0 | 0 |
  82. | bundleIn_0_d_q | Queue_13_57 | 65 | 7 | 58 | 0 | 3 | 0 | 0 | 0 |
  83. | bundleOut_0_a_q | Queue_12_58 | 188 | 94 | 94 | 0 | 3 | 0 | 0 | 0 |
  84. | subsystem_fbus_coupler_from_port_named_slave_port_axi4 | TLInterconnectCoupler_5 | 971 | 795 | 176 | 0 | 280 | 0 | 0 | 0 |
  85. | axi42tl | AXI4ToTL | 294 | 294 | 0 | 0 | 103 | 0 | 0 | 0 |
  86. | (axi42tl) | AXI4ToTL | 48 | 48 | 0 | 0 | 32 | 0 | 0 | 0 |
  87. | deq | Queue_16 | 195 | 195 | 0 | 0 | 68 | 0 | 0 | 0 |
  88. | q_b_deq | Queue_17 | 51 | 51 | 0 | 0 | 3 | 0 | 0 | 0 |
  89. | axi4frag | AXI4Fragmenter | 330 | 330 | 0 | 0 | 139 | 0 | 0 | 0 |
  90. | (axi4frag) | AXI4Fragmenter | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 |
  91. | deq | Queue_18 | 75 | 75 | 0 | 0 | 30 | 0 | 0 | 0 |
  92. | deq_1 | Queue_18_55 | 112 | 112 | 0 | 0 | 30 | 0 | 0 | 0 |
  93. | in_w_deq | Queue_10_56 | 143 | 143 | 0 | 0 | 67 | 0 | 0 | 0 |
  94. | axi4yank | AXI4UserYanker_1 | 56 | 32 | 24 | 0 | 14 | 0 | 0 | 0 |
  95. | QueueCompatibility | QueueCompatibility_10_51 | 12 | 6 | 6 | 0 | 5 | 0 | 0 | 0 |
  96. | QueueCompatibility_1 | QueueCompatibility_10_52 | 15 | 9 | 6 | 0 | 2 | 0 | 0 | 0 |
  97. | QueueCompatibility_2 | QueueCompatibility_10_53 | 13 | 7 | 6 | 0 | 5 | 0 | 0 | 0 |
  98. | QueueCompatibility_3 | QueueCompatibility_10_54 | 16 | 10 | 6 | 0 | 2 | 0 | 0 | 0 |
  99. | buffer | TLBuffer_3 | 283 | 131 | 152 | 0 | 6 | 0 | 0 | 0 |
  100. | bundleIn_0_d_q | Queue_13 | 98 | 40 | 58 | 0 | 3 | 0 | 0 | 0 |
  101. | bundleOut_0_a_q | Queue_12 | 185 | 91 | 94 | 0 | 3 | 0 | 0 | 0 |
  102. | fixer | TLFIFOFixer_2 | 12 | 12 | 0 | 0 | 18 | 0 | 0 | 0 |
  103. | subsystem_l2_wrapper | CoherenceManagerWrapper | 694 | 486 | 208 | 0 | 280 | 0 | 0 | 0 |
  104. | (subsystem_l2_wrapper) | CoherenceManagerWrapper | 15 | 15 | 0 | 0 | 0 | 0 | 0 | 0 |
  105. | broadcast_1 | TLBroadcast | 679 | 471 | 208 | 0 | 280 | 0 | 0 | 0 |
  106. | (broadcast_1) | TLBroadcast | 50 | 50 | 0 | 0 | 52 | 0 | 0 | 0 |
  107. | TLBroadcastTracker | TLBroadcastTracker | 91 | 39 | 52 | 0 | 57 | 0 | 0 | 0 |
  108. | (TLBroadcastTracker) | TLBroadcastTracker | 13 | 13 | 0 | 0 | 50 | 0 | 0 | 0 |
  109. | o_data | Queue_28_50 | 78 | 26 | 52 | 0 | 7 | 0 | 0 | 0 |
  110. | TLBroadcastTracker_1 | TLBroadcastTracker_1 | 217 | 165 | 52 | 0 | 57 | 0 | 0 | 0 |
  111. | (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 19 | 19 | 0 | 0 | 50 | 0 | 0 | 0 |
  112. | o_data | Queue_28_49 | 198 | 146 | 52 | 0 | 7 | 0 | 0 | 0 |
  113. | TLBroadcastTracker_2 | TLBroadcastTracker_2 | 227 | 175 | 52 | 0 | 57 | 0 | 0 | 0 |
  114. | (TLBroadcastTracker_2) | TLBroadcastTracker_2 | 21 | 21 | 0 | 0 | 50 | 0 | 0 | 0 |
  115. | o_data | Queue_28_48 | 206 | 154 | 52 | 0 | 7 | 0 | 0 | 0 |
  116. | TLBroadcastTracker_3 | TLBroadcastTracker_3 | 95 | 43 | 52 | 0 | 57 | 0 | 0 | 0 |
  117. | (TLBroadcastTracker_3) | TLBroadcastTracker_3 | 22 | 22 | 0 | 0 | 50 | 0 | 0 | 0 |
  118. | o_data | Queue_28 | 73 | 21 | 52 | 0 | 7 | 0 | 0 | 0 |
  119. | subsystem_mbus | MemoryBus | 1912 | 1400 | 512 | 0 | 487 | 0 | 0 | 0 |
  120. | (subsystem_mbus) | MemoryBus | 36 | 36 | 0 | 0 | 0 | 0 | 0 | 0 |
  121. | coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_12 | 1876 | 1364 | 512 | 0 | 487 | 0 | 0 | 0 |
  122. | axi4yank | AXI4UserYanker_2 | 909 | 397 | 512 | 0 | 224 | 0 | 0 | 0 |
  123. | QueueCompatibility | QueueCompatibility_14 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  124. | QueueCompatibility_1 | QueueCompatibility_14_17 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  125. | QueueCompatibility_10 | QueueCompatibility_14_18 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  126. | QueueCompatibility_11 | QueueCompatibility_14_19 | 40 | 24 | 16 | 0 | 7 | 0 | 0 | 0 |
  127. | QueueCompatibility_12 | QueueCompatibility_14_20 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  128. | QueueCompatibility_13 | QueueCompatibility_14_21 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  129. | QueueCompatibility_14 | QueueCompatibility_14_22 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  130. | QueueCompatibility_15 | QueueCompatibility_14_23 | 43 | 27 | 16 | 0 | 7 | 0 | 0 | 0 |
  131. | QueueCompatibility_16 | QueueCompatibility_14_24 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  132. | QueueCompatibility_17 | QueueCompatibility_14_25 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  133. | QueueCompatibility_18 | QueueCompatibility_14_26 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  134. | QueueCompatibility_19 | QueueCompatibility_14_27 | 40 | 24 | 16 | 0 | 7 | 0 | 0 | 0 |
  135. | QueueCompatibility_2 | QueueCompatibility_14_28 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  136. | QueueCompatibility_20 | QueueCompatibility_14_29 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  137. | QueueCompatibility_21 | QueueCompatibility_14_30 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  138. | QueueCompatibility_22 | QueueCompatibility_14_31 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  139. | QueueCompatibility_23 | QueueCompatibility_14_32 | 38 | 22 | 16 | 0 | 7 | 0 | 0 | 0 |
  140. | QueueCompatibility_24 | QueueCompatibility_14_33 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  141. | QueueCompatibility_25 | QueueCompatibility_14_34 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  142. | QueueCompatibility_26 | QueueCompatibility_14_35 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  143. | QueueCompatibility_27 | QueueCompatibility_14_36 | 72 | 56 | 16 | 0 | 7 | 0 | 0 | 0 |
  144. | QueueCompatibility_28 | QueueCompatibility_14_37 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  145. | QueueCompatibility_29 | QueueCompatibility_14_38 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  146. | QueueCompatibility_3 | QueueCompatibility_14_39 | 41 | 25 | 16 | 0 | 7 | 0 | 0 | 0 |
  147. | QueueCompatibility_30 | QueueCompatibility_14_40 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  148. | QueueCompatibility_31 | QueueCompatibility_14_41 | 39 | 23 | 16 | 0 | 7 | 0 | 0 | 0 |
  149. | QueueCompatibility_4 | QueueCompatibility_14_42 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  150. | QueueCompatibility_5 | QueueCompatibility_14_43 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  151. | QueueCompatibility_6 | QueueCompatibility_14_44 | 23 | 7 | 16 | 0 | 7 | 0 | 0 | 0 |
  152. | QueueCompatibility_7 | QueueCompatibility_14_45 | 38 | 22 | 16 | 0 | 7 | 0 | 0 | 0 |
  153. | QueueCompatibility_8 | QueueCompatibility_14_46 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  154. | QueueCompatibility_9 | QueueCompatibility_14_47 | 24 | 8 | 16 | 0 | 7 | 0 | 0 | 0 |
  155. | tl2axi4 | TLToAXI4_1 | 967 | 967 | 0 | 0 | 263 | 0 | 0 | 0 |
  156. | (tl2axi4) | TLToAXI4_1 | 150 | 150 | 0 | 0 | 133 | 0 | 0 | 0 |
  157. | deq | Queue_10_16 | 518 | 518 | 0 | 0 | 74 | 0 | 0 | 0 |
  158. | queue_arw_deq | Queue_27 | 302 | 302 | 0 | 0 | 56 | 0 | 0 | 0 |
  159. | subsystem_sbus | SystemBus | 2437 | 1897 | 540 | 0 | 423 | 0 | 0 | 0 |
  160. | coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_4 | 1697 | 1157 | 540 | 0 | 316 | 0 | 0 | 0 |
  161. | axi4buf | AXI4Buffer | 903 | 685 | 218 | 0 | 15 | 0 | 0 | 0 |
  162. | bundleIn_0_b_deq | Queue_2 | 46 | 40 | 6 | 0 | 3 | 0 | 0 | 0 |
  163. | bundleIn_0_r_deq | Queue_4 | 162 | 112 | 50 | 0 | 3 | 0 | 0 | 0 |
  164. | bundleOut_0_ar_deq | Queue | 221 | 167 | 54 | 0 | 3 | 0 | 0 | 0 |
  165. | bundleOut_0_aw_deq | Queue_15 | 200 | 146 | 54 | 0 | 3 | 0 | 0 | 0 |
  166. | bundleOut_0_w_deq | Queue_1 | 290 | 236 | 54 | 0 | 3 | 0 | 0 | 0 |
  167. | axi4deint | AXI4Deinterleaver | 539 | 249 | 290 | 0 | 59 | 0 | 0 | 0 |
  168. | (axi4deint) | AXI4Deinterleaver | 12 | 12 | 0 | 0 | 24 | 0 | 0 | 0 |
  169. | qs_queue_0 | Queue_5 | 68 | 10 | 58 | 0 | 7 | 0 | 0 | 0 |
  170. | qs_queue_1 | Queue_5_11 | 185 | 127 | 58 | 0 | 7 | 0 | 0 | 0 |
  171. | qs_queue_2 | Queue_5_12 | 143 | 85 | 58 | 0 | 7 | 0 | 0 | 0 |
  172. | qs_queue_3 | Queue_5_13 | 65 | 7 | 58 | 0 | 7 | 0 | 0 | 0 |
  173. | qs_queue_4 | Queue_5_14 | 66 | 8 | 58 | 0 | 7 | 0 | 0 | 0 |
  174. | axi4yank | AXI4UserYanker | 77 | 45 | 32 | 0 | 88 | 0 | 0 | 0 |
  175. | QueueCompatibility | QueueCompatibility | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 |
  176. | QueueCompatibility_1 | QueueCompatibility_1 | 17 | 9 | 8 | 0 | 7 | 0 | 0 | 0 |
  177. | QueueCompatibility_2 | QueueCompatibility_1_3 | 19 | 11 | 8 | 0 | 7 | 0 | 0 | 0 |
  178. | QueueCompatibility_3 | QueueCompatibility_4 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 |
  179. | QueueCompatibility_4 | QueueCompatibility_5 | 1 | 1 | 0 | 0 | 10 | 0 | 0 | 0 |
  180. | QueueCompatibility_5 | QueueCompatibility_6 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 |
  181. | QueueCompatibility_6 | QueueCompatibility_1_7 | 16 | 8 | 8 | 0 | 7 | 0 | 0 | 0 |
  182. | QueueCompatibility_7 | QueueCompatibility_1_8 | 24 | 16 | 8 | 0 | 7 | 0 | 0 | 0 |
  183. | QueueCompatibility_8 | QueueCompatibility_9 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 |
  184. | QueueCompatibility_9 | QueueCompatibility_10 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 |
  185. | tl2axi4 | TLToAXI4 | 178 | 178 | 0 | 0 | 154 | 0 | 0 | 0 |
  186. | (tl2axi4) | TLToAXI4 | 21 | 21 | 0 | 0 | 22 | 0 | 0 | 0 |
  187. | deq | Queue_10 | 85 | 85 | 0 | 0 | 74 | 0 | 0 | 0 |
  188. | queue_arw_deq | Queue_11 | 72 | 72 | 0 | 0 | 58 | 0 | 0 | 0 |
  189. | fixer | TLFIFOFixer | 29 | 29 | 0 | 0 | 38 | 0 | 0 | 0 |
  190. | system_bus_xbar | TLXbar | 711 | 711 | 0 | 0 | 69 | 0 | 0 | 0 |
  191. | tile_prci_domain | TilePRCIDomain | 8648 | 8294 | 354 | 0 | 4496 | 1 | 4 | 0 |
  192. | buffer_1 | TLBuffer_9 | 493 | 227 | 266 | 0 | 15 | 0 | 0 | 0 |
  193. | bundleIn_0_b_q | Queue_34 | 37 | 5 | 32 | 0 | 3 | 0 | 0 | 0 |
  194. | bundleIn_0_d_q | Queue_33 | 193 | 133 | 60 | 0 | 3 | 0 | 0 | 0 |
  195. | bundleOut_0_a_q | Queue_32 | 119 | 29 | 90 | 0 | 3 | 0 | 0 | 0 |
  196. | bundleOut_0_c_q | Queue_35 | 134 | 52 | 82 | 0 | 3 | 0 | 0 | 0 |
  197. | bundleOut_0_e_q | Queue_36 | 10 | 8 | 2 | 0 | 3 | 0 | 0 | 0 |
  198. | tile_reset_domain_tile | RocketTile | 8155 | 8067 | 88 | 0 | 4481 | 1 | 4 | 0 |
  199. | core | Rocket | 4473 | 4385 | 88 | 0 | 1926 | 0 | 0 | 0 |
  200. | (core) | Rocket | 1169 | 1081 | 88 | 0 | 633 | 0 | 0 | 0 |
  201. | csr | CSRFile | 2231 | 2231 | 0 | 0 | 1020 | 0 | 0 | 0 |
  202. | div | MulDiv | 1055 | 1055 | 0 | 0 | 214 | 0 | 0 | 0 |
  203. | ibuf | IBuf | 18 | 18 | 0 | 0 | 59 | 0 | 0 | 0 |
  204. | dcache | DCache | 1502 | 1502 | 0 | 0 | 972 | 1 | 1 | 0 |
  205. | (dcache) | DCache | 1275 | 1275 | 0 | 0 | 972 | 0 | 0 | 0 |
  206. | data | DCacheDataArray | 152 | 152 | 0 | 0 | 0 | 1 | 0 | 0 |
  207. | data_arrays_0 | data_arrays_0 | 152 | 152 | 0 | 0 | 0 | 1 | 0 | 0 |
  208. | data_arrays_0_ext | data_arrays_0_ext | 152 | 152 | 0 | 0 | 0 | 1 | 0 | 0 |
  209. | tag_array | tag_array | 75 | 75 | 0 | 0 | 0 | 0 | 1 | 0 |
  210. | tag_array_ext | tag_array_ext | 75 | 75 | 0 | 0 | 0 | 0 | 1 | 0 |
  211. | dcacheArb | HellaCacheArbiter | 19 | 19 | 0 | 0 | 2 | 0 | 0 | 0 |
  212. | frontend | Frontend | 1506 | 1506 | 0 | 0 | 1008 | 0 | 3 | 0 |
  213. | (frontend) | Frontend | 1 | 1 | 0 | 0 | 88 | 0 | 0 | 0 |
  214. | fq | ShiftQueue | 812 | 812 | 0 | 0 | 375 | 0 | 0 | 0 |
  215. | icache | ICache | 178 | 178 | 0 | 0 | 139 | 0 | 3 | 0 |
  216. | (icache) | ICache | 111 | 111 | 0 | 0 | 139 | 0 | 0 | 0 |
  217. | data_arrays_0 | data_arrays_0_0 | 9 | 9 | 0 | 0 | 0 | 0 | 1 | 0 |
  218. | data_arrays_0_0_ext | data_arrays_0_0_ext_2 | 9 | 9 | 0 | 0 | 0 | 0 | 1 | 0 |
  219. | data_arrays_1 | data_arrays_0_0_1 | 30 | 30 | 0 | 0 | 0 | 0 | 1 | 0 |
  220. | data_arrays_0_0_ext | data_arrays_0_0_ext | 30 | 30 | 0 | 0 | 0 | 0 | 1 | 0 |
  221. | tag_array | tag_array_0 | 28 | 28 | 0 | 0 | 0 | 0 | 1 | 0 |
  222. | tag_array_0_ext | tag_array_0_ext | 28 | 28 | 0 | 0 | 0 | 0 | 1 | 0 |
  223. | tlb | TLB_1 | 515 | 515 | 0 | 0 | 406 | 0 | 0 | 0 |
  224. | (tlb) | TLB_1 | 515 | 515 | 0 | 0 | 406 | 0 | 0 | 0 |
  225. | pmp | PMPChecker_2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
  226. | ptw | PTW | 864 | 864 | 0 | 0 | 561 | 0 | 0 | 0 |
  227. | tlMasterXbar | TLXbar_7 | 29 | 29 | 0 | 0 | 12 | 0 | 0 | 0 |
  228. +------------------------------------------------------------+-------------------------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
  229. * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
  230.  
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