module dsw_4_12 (iDSW4, oDSW12);

input [3:0] iDSW4;
output [11:0] oDSW12;
reg [11:0] temp;

assign oDSW12 = temp;

always @ * begin
    case (iDSW4)
      4'b0000: temp = 12'b0000_0000_0000; //0
      4'b0001: temp = 12'b0000_1111_1111; //1
      4'b0010: temp = 12'b0001_1111_1110; //2
      4'b0011: temp = 12'b0010_1111_1101; //3
      4'b0100: temp = 12'b0011_1111_1100; //4
      4'b0101: temp = 12'b0100_1111_1011; //5
      4'b0110: temp = 12'b0101_1111_1010; //6
      4'b0111: temp = 12'b0110_1111_1001; //7
      4'b1000: temp = 12'b0111_1111_1000; //8
      4'b1001: temp = 12'b1000_1111_0111; //9
      4'b1010: temp = 12'b1001_1111_0110; //10
      4'b1011: temp = 12'b1010_1111_0101; //11
      4'b1100: temp = 12'b1011_1111_0100; //12
      4'b1101: temp = 12'b1100_1111_0011; //13
      4'b1110: temp = 12'b1101_1111_0010; //14
      4'b1111: temp = 12'b1110_1111_0001; //15
    endcase
end

endmodule