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Harmony5757

BCD Counter TestBench

May 11th, 2025
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SystemVerilog 0.68 KB | Source Code | 0 0
  1. `timescale 1ns / 1ps
  2. module bcdCounterTB(
  3.  
  4.     );
  5.    
  6.     logic clk, reset;
  7.     logic [3:0] counter, counter2;
  8.     logic [6:0] seg7, seg7_2;
  9.    
  10.     bcdCounter #(3, 4) dut(.clk(clk),
  11.                            .reset(reset),
  12.                            .counter(counter),
  13.                            .counter2(counter2),
  14.                            .seg7(seg7),
  15.                            .seg7_2(seg7_2)
  16.                            );
  17.    
  18.     initial
  19.         begin
  20.             clk = 0; reset = 1; #5; reset = 0;
  21.             forever #5 clk = !clk;
  22.         end
  23.     initial
  24.         begin
  25.             repeat(50) @(posedge clk);
  26.             $finish();
  27.         end
  28. endmodule
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