library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port (
     A		:out std_logic;					-- Output impulse
     Di		:in  std_logic_vector (10 downto 0);		-- Input time delta
     clk	:in  std_logic;    				-- Input clock
     reset	:in  std_logic     				-- Input reset
   );
end entity;

architecture counter_architecture of counter is
	signal count	 	:INTEGER := 0;			-- counter
	begin
		process (clk, reset) begin
			if (reset = '1') then
				count <= 0;			-- reset
			elsif (rising_edge(clk)) then
				if (count < Di) then
					if (count < 100) then	-- sound for 1s
						A <= '1';	-- sound
					else
						A <= '0';	-- no sound
					end if;
					count <= count + 1;	-- increment count
				else
					count <= 0;		-- start over
				end if;
			end if;
		end process;
end architecture;