CONTROL

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY control IS
	PORT (
		clk : IN std_logic;
		IR : IN signed(15 DOWNTO 0);
		reset, C, Z, S, INT : IN std_logic;
		Salu, Sbb, Sbc, Sba : OUT bit_vector(3 DOWNTO 0);
		Sid : OUT bit_vector(2 DOWNTO 0);
		Sa : OUT bit_vector(1 DOWNTO 0);
		LDF, Smar, Smbr, WR, RD, INTA, MIO : OUT BIT
	);
END ENTITY;
ARCHITECTURE rtl OF control IS
	TYPE state_type IS (fetch, dec, wait_1, call_1, call_2, call_3, call_4,
	RET_1, RET_2, RET_3, push, pop_1, pop_2, neg, inc, dec_1, not_1, shr, shl,
	m29, mov_r, mov_rm, add, sub, and_1, or_1, xor_1, in_r, out_io, jump_1, jump_2,
	long_jump, r_st16,  r_adr32, m9,
	mov_arg1_arg2, add_arg1_arg2, sub_arg1_arg2, gethx_arg1_arg2,getlx_arg1_arg2,
	shl_arg1_arg2, shr_arg1_arg2, jmp_etykieta);
	SIGNAL state : state_type;
BEGIN
	PROCESS (clk, reset)
	BEGIN
		IF reset = '1' THEN
			state <= fetch;
		ELSIF (clk'EVENT AND clk = '1') THEN
			CASE state IS
				WHEN fetch =>
					state <= dec;
				WHEN dec =>
					CASE IR(15 DOWNTO 13) IS
						WHEN "000" =>
							CASE IR(12 DOWNTO 11) IS
								WHEN "00" =>
									IF (INT = '0') THEN
										state <= fetch;
									ELSE
										state <= m9;
									END IF;
								WHEN "01" => state <= wait_1;
								WHEN "10" => state <= call_1;
								WHEN "11" => state <= RET_1;
								WHEN others => state <= fetch;
						END CASE;
						WHEN "001" =>
							CASE IR(12 DOWNTO 8) IS
								WHEN "00000" => state <= push;
								WHEN "00001" => state <= pop_1;
								WHEN "00010" => state <= neg;
								WHEN "00011" => state <= inc;
								WHEN "00100" => state <= dec_1;
								WHEN "00101" => state <= not_1;
								WHEN "00110" => state <= shr;
								WHEN "00111" => state <= shl;
								WHEN "01000" => state <= m29;
								WHEN "01001" => state <= mov_r;
								WHEN "01010" => state <= mov_rm;
								WHEN "01011" => state <= add;
								WHEN "01100" => state <= sub;
								WHEN "01101" => state <= and_1;
								WHEN "01110" => state <= or_1;
								WHEN "01111" => state <= xor_1;
								WHEN "10000" => state <= in_r;
								WHEN "10001" => state <= out_io;
								WHEN OTHERS => state <= fetch;
						END CASE;
						WHEN "010" => state <= jump_1;
						WHEN "011" => state <= jump_2;

					WHEN "100" =>
						case IR(12 downto 8) is
							when "000000" => state <= mov_arg1_arg2;
							when "000001" => state <= add_arg1_arg2;
							when "000010" => state <= sub_arg1_arg2;
							when "000011" => state <= gethx_arg1_arg2;
							when "000100" => state <= getlx_arg1_arg2;
							when "000101" => state <= shl_arg1_arg2;
							when "000110" => state <= shr_arg1_arg2;
							when "000111" => state <= jmp_etykieta;
							WHEN OTHERS => state <= fetch;
							END CASE;
						when "101" => state <= r_adr32;
						when others => state <= fetch;
						end case;

				WHEN wait_1 =>
					IF INT = '1' THEN
						state <= m9;
					ELSE state <= wait_1;
					END IF;
				WHEN call_1 => state <= call_2;
				WHEN call_2 => state <= call_3;
				WHEN call_3 => state <= call_4;
				WHEN call_4 =>
					IF INT = '1' THEN
						state <= m9;
					ELSE state <= fetch;
					END IF;
				when others => state <= fetch;
			END CASE;
		END IF;
	END PROCESS;

	PROCESS (state) BEGIN
	CASE state IS
		WHEN fetch =>
			Sa <= "01"; Sbb <= "0000"; Sba <= "0000"; Sid <= "001"; Sbc <= "0000";
			MIO <= '1'; Smar <= '1'; Smbr <= '0'; WR <= '0'; RD <= '1'; Salu <="0000"; LDF <= '0'; INTA <= '0';
		WHEN dec =>
			Sa <= "00"; Sbb <= "0000"; Sba <= "0000"; Sid <= "000"; Sbc <= "0000";
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '0'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';
		WHEN wait_1 =>
			Sa <= "00"; Sbb <= "0000"; Sba <= "0000"; Sid <= "000"; Sbc <= "0000";
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '0'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';
		WHEN call_1 =>
			Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <= "011"; Sbc <= "0000";
			MIO <= '1'; Smar <= '1'; Smbr <= '1'; WR <= '1'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';

		WHEN mov_arg1_arg2 =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0000"; LDF <= '1'; INTA <= '0';

		WHEN add_arg1_arg2 =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0001"; LDF <= '1'; INTA <= '0';

		WHEN sub_arg1_arg2 =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0010"; LDF <= '1'; INTA <= '0';



		WHEN gethx_arg1_arg2 =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0011"; LDF <= '1'; INTA <= '0';

		WHEN getlx_arg1_arg2 =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0100"; LDF <= '1'; INTA <= '0';

		WHEN shl_arg1_arg2 =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0101"; LDF <= '1'; INTA <= '0';

		WHEN shr_arg1_arg2 =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0110"; LDF <= '1'; INTA <= '0';

		WHEN jmp_etykieta =>
			Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
			Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0111"; LDF <= '1'; INTA <= '0';





		WHEN OTHERS =>
			Sa <= "00"; Sbb <= "0000"; Sba <= "0000"; Sid <= "000"; Sbc <= "0000";
			MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '0'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';
		END CASE;
	END PROCESS;
END rtl;