`timescale 1ns / 1ps

module test_simple_gates();

reg  [3:0] t_sw;
wire [1:0] t_led;
integer I = 0;

artix7 DUT
(
    .sw (t_sw),
    .led(t_led)
);

initial begin

        $display("%0t: Starting TPG.", $time);

        for (i = 0; i <= 15; i=i+1) begin
            #10 t_sw = i;
            #1
            if ( ( (t_sw[0] || t_sw[1]) == t_led[0] ) && ( (t_sw[2] && t_sw[3]) == t_led[1] ) )
               $display("%0t Test PASSED for pattern %b", $time, t_sw);
            else
               $display("%0t Test FAILED for pattern %b - result is %b", $time, t_sw, t_led);
        end

        #10 $display("%0t: Finished TPG.", $time);

        $stop;

    end

endmodule