Advertisement
Guest User

Untitled

a guest
May 18th, 2014
13
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. /*
  2.  * Copyright (c) 2014, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and non-source forms, with or without
  6.  * modification, are permitted provided that the following conditions are met:
  7.  *     * Redistributions of source code must retain the above copyright
  8.  *       notice, this list of conditions and the following disclaimer.
  9.  *     * Redistributions in non-source form must reproduce the above copyright
  10.  *       notice, this list of conditions and the following disclaimer in the
  11.  *       documentation and/or other materials provided with the distribution.
  12.  *
  13.  * THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  14.  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  15.  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  16.  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
  17.  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  18.  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  19.  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20.  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  21.  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  23.  * WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24.  */
  25.  
  26. module ipi #(
  27.     parameter NUM_CORES = 2
  28. )(
  29.     // Wishbone slave interface
  30.     input              wb_clk,
  31.     input              wb_rst,
  32.     input [17:0]           wb_adr_i,
  33.     input [31:0]           wb_dat_i,
  34.     input [3:0]            wb_sel_i,
  35.     input              wb_we_i,
  36.     input              wb_cyc_i,
  37.     input              wb_stb_i,
  38.     input [2:0]            wb_cti_i,
  39.     input [1:0]            wb_bte_i,
  40.     output [31:0]          wb_dat_o,
  41.     output reg         wb_ack_o,
  42.     output             wb_err_o,
  43.     output             wb_rty_o,
  44.  
  45.     // Per-core Interrupt output
  46.     output reg [NUM_CORES-1:0] irq
  47. );
  48.  
  49. localparam
  50.     CONTROL = 0,
  51.     STATUS  = 1;
  52.  
  53. localparam
  54.     CTRL_IRQ_ACK    = 31,
  55.     CTRL_IRQ_GEN    = 30;
  56.  
  57. // Control register
  58. // +---------+---------+----------+---------+
  59. // | 31      | 30      | 29 .. 16 | 15 .. 0 |
  60. // ----------+---------+----------+----------
  61. // | IRQ ACK | IRQ GEN | DST CORE | DATA    |
  62. // +---------+---------+----------+---------+
  63. reg [31:0] control [NUM_CORES-1:0];
  64.  
  65. // Status register
  66. // +----------+----------+---------+
  67. // | 31 .. 30 | 29 .. 16 | 15 .. 0 |
  68. // -----------+----------+---------+
  69. // | Reserved | SRC CORE | DATA    |
  70. // +----------+----------+---------+
  71. reg [31:0] status [NUM_CORES-1:0];
  72.  
  73. // Write logic
  74. always @(posedge wb_clk) begin
  75.     if (wb_ack_o & wb_we_i & (wb_adr_i[3:2] == CONTROL)) begin
  76.         control[wb_adr_i[17:4]] <= wb_dat_i;
  77.  
  78.         if (wb_dat_i[CTRL_IRQ_GEN]) begin
  79.             irq[wb_dat_i[29:16]] <= 1;
  80.             status[wb_dat_i[29:16]][15:0] <= wb_dat_i[15:0];
  81.             status[wb_dat_i[29:16]][29:16] <= wb_adr_i[17:4];
  82.         end
  83.  
  84.         if (wb_dat_i[CTRL_IRQ_ACK])
  85.             irq[wb_adr_i[17:4]] <= 0;
  86.     end
  87. end
  88.  
  89. // Read logic
  90. always @(posedge wb_clk) begin
  91.     if (wb_cyc_i & wb_stb_i & !wb_we_i)
  92.         case (wb_adr_i[3:2])
  93.         CONTROL: begin
  94.             wb_dat_o <= control[wb_adr_i[17:4]];
  95.         end
  96.         STATUS: begin
  97.             wb_dat_o <= status[wb_adr_i[17:4]];
  98.         end
  99.         endcase
  100.     end
  101. end
  102.  
  103. // Ack logic
  104. always @(posedge wb_clk)
  105.     wb_ack_o <= wb_cyc_i & wb_stb_i & !wb_ack_o;
  106.  
  107. assign wb_err_o = 0;
  108. assign wb_rty_o = 0;
  109.  
  110.  
  111. endmodule
Advertisement
RAW Paste Data Copied
Advertisement