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- ===================================================================
- MT7621 stage1 code done
- CPU=50000000 HZ BUS=16666666 HZ
- ===================================================================
- U-Boot 1.1.3 (Jul 2 2014 - 21:19:36)
- SVN revision: 1076
- Target board: WRG-AC13
- Board: Ralink APSoC DRAM: 128 MB
- Config XHCI 40M PLL
- ******************************
- Software System Reset Occurred
- ******************************
- flash manufacture id: c2, device id 20 18
- find flash: MX25L12805D
- ============================================
- Ralink UBoot Version: 4.2.0.6
- --------------------------------------------
- ASIC MT7621A DualCore (MAC to MT7530 Mode)
- DRAM_CONF_FROM: Auto-Detection
- DRAM_TYPE: DDR3
- DRAM bus: 16 bit
- Xtal Mode=3 OCP Ratio=1/3
- Flash component: SPI Flash
- Date:Jul 2 2014 Time:21:19:36
- ============================================
- icache: sets:256, ways:4, linesz:32 ,total:32768
- dcache: sets:256, ways:4, linesz:32 ,total:32768
- ## Switch HW reset
- #Reset_MT7530
- ## Powering down port 1 ~ 4
- Please choose the operation:
- 1: Load system code to SDRAM via TFTP.
- 2: Load system code then write to Flash via TFTP.
- 3: Boot system code via Flash (default).
- 4: Entr boot command line interface.
- 7: Load Boot Loader code then write to Flash via Serial.
- 9: Load Boot Loader code then write to Flash via TFTP.
- You choosed 3
- 0
- 3: System Boot system code via Flash.
- ## Booting image at bfc50000 ...
- addr:80500000
- We have SEAMA, Image Size = 0
- Verifying Checksum ...
- Bad Header Checksum.
- Entering HTTP server.
- KSEG1ADDR(NetTxPacket) = 0xA7FE5A80
- NetLoop,call eth_halt !
- NetLoop,call eth_init !
- Waitting for RX_DMA_BUSY status Start... done
- ETH_STATE_ACTIVE!!
- Start HTTP server on port 80, 192.168.0.1
- Running ...
- Abort
- ===================================================================
- MT7621 stage1 code 10:41:05 (ASIC)
- CPU=50000000 HZ BUS=16666666 HZ
- ==================================================================
- Change MPLL source from XTAL to CR...
- do MEMPLL setting..
- MEMPLL Config : 0x11000000
- 3PLL mode + External loopback
- === XTAL-40Mhz === DDR-1200Mhz ===
- PLL3 FB_DL: 0x4, 1/0 = 724/300 11000000
- PLL2 FB_DL: 0x12, 1/0 = 571/453 49000000
- PLL4 FB_DL: 0x15, 1/0 = 584/440 55000000
- do DDR setting..[00320000]
- Apply DDR3 Setting...(use default AC)
- 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
- --------------------------------------------------------------------------------
- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
- 000E:| 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
- 000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0
- 0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
- 0011:| 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
- 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- rank 0 coarse = 16
- rank 0 fine = 32
- B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
- opt_dle value:9
- DRAMC_R0DELDLY[018]=00001C1D
- ==================================================================
- RX DQS perbit delay software calibration
- ==================================================================
- 1.0-15 bit dq delay value
- ==================================================================
- bit| 0 1 2 3 4 5 6 7 8 9
- --------------------------------------
- 0 | 13 11 11 13 9 11 10 9 9 8
- 10 | 11 11 10 13 10 11
- --------------------------------------
- ==================================================================
- 2.dqs window
- x=pass dqs delay value (min~max)center
- y=0-7bit DQ of every group
- input delay:DQS0 =29 DQS1 = 28
- ==================================================================
- bit DQS0 bit DQS1
- 0 (2~56)29 8 (1~55)28
- 1 (1~55)28 9 (1~54)27
- 2 (1~55)28 10 (1~56)28
- 3 (1~55)28 11 (1~52)26
- 4 (1~54)27 12 (1~53)27
- 5 (1~56)28 13 (1~54)27
- 6 (1~55)28 14 (1~56)28
- 7 (1~56)28 15 (1~55)28
- ==================================================================
- 3.dq delay value last
- ==================================================================
- bit| 0 1 2 3 4 5 6 7 8 9
- --------------------------------------
- 0 | 13 12 12 14 11 12 11 10 9 9
- 10 | 11 13 11 14 10 11
- ==================================================================
- ==================================================================
- TX perbyte calibration
- ==================================================================
- DQS loop = 15, cmp_err_1 = ffff0000
- dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
- dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
- DQ loop=15, cmp_err_1 = ffff00bc
- dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=1
- DQ loop=14, cmp_err_1 = ffff0080
- DQ loop=13, cmp_err_1 = ffff0080
- DQ loop=12, cmp_err_1 = ffff0000
- dqs_perbyte_dly.last_dqdly_pass[0]=12, finish count=2
- byte:0, (DQS,DQ)=(9,8)
- byte:1, (DQS,DQ)=(8,8)
- 20,data:89
- [EMI] DRAMC calibration passed
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