library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity targ_term is
port(	-- Inputs
		clk			: in std_logic;
		rstn		: in std_logic;
		l_adro		: in std_logic_vector(31 downto 0);
		l_dato		: in std_logic_vector(31 downto 0);
		l_beno		: in std_logic_vector(3 downto 0);
		l_cmdo		: in std_logic_vector(3 downto 0);
		lt_framen	: in std_logic;
		lt_ackn		: in std_logic;
		lt_dxfrn	: in std_logic;
		lt_tsr		: in std_logic_vector(11 downto 0);
		cmd_reg		: in std_logic_vector(6 downto 0);
		stat_reg	: in std_logic_vector(6 downto 0);
		-- Outputs
		l_adi		: out std_logic_vector(31 downto 0);
		lt_rdyn		: out std_logic;
		lt_abortn	: out std_logic;
		lt_discn	: out std_logic;
		lt_irqn		: out std_logic
);
end targ_term;

architecture rtl of targ_term is

	signal	bar0_mem_hit	: std_logic;
	signal	pci_xfr			: std_logic;

	signal 	lt_framen_q		: std_logic;

	signal	cycle_start		: std_logic;
	signal	cycle_end		: std_logic;

	signal	targ_wr_rdn		: std_logic;	-- write = 1 and read = 0



begin
	l_adi <= mem_rd_data;
	lt_rdyn <= lt_rdyn_tmp;

	lt_abortn <= '1';	-- Target Abort
	lt_irqn <= '1';	-- Irq

	-- Some renames
	bar0_mem_hit <= lt_tsr(0);
	pci_xfr <= lt_tsr(10);

    -- Detect the start and end of a PCI transaction
	-- The falling edge of lt_framen can be used to detect start of a
	-- PCI transaction, similarly detecting the rising edge of
	-- lt_framen indicates the end of the PCI transaction.
    process(clk, rstn)
    begin
		if (rstn='0') then
			lt_framen_q <= '1';
		elsif(clk'event and clk='1') then
			lt_framen_q <= lt_framen;
		end if;
    end process;

	cycle_start <= (lt_framen_q and (not(lt_framen)));
	cycle_end <= (lt_framen and (not(lt_framen_q)));

	-- Direction of Data Transfer
	-- Read/Write Signals
    process(clk)
    begin
		if (clk'event and clk='1') then
			targ_wr_rdn <= l_cmdo(0);
		end if;
    end process;

    process(clk, rstn)
    begin
		if (rstn='0') then
			xfr_cntr <= x"00";
		elsif (clk'event and clk='1') then
			if (cycle_start='1') then
				xfr_cntr <= x"00";
			elsif (lt_dxfrn='0') then
				xfr_cntr <= xfr_cntr + 1;
			end if;
		end if;
    end process;

	lt_discn<= (not(assert_disc  and (not(lt_dxfrn) or transfer_1_dword)));

	-- Interface to a sync. memory
	mem_wr_enable <= (not(lt_dxfrn) and targ_wr_rdn and bar0_mem_hit);

	-- Generate Address
	mem_wr_inc <= (targ_wr_rdn and (not(lt_dxfrn)) and bar0_mem_hit);
	mem_rd_inc <= ((not(targ_wr_rdn)) and (not(lt_ackn)) and bar0_mem_hit);

	mem_inc <= mem_wr_inc or mem_rd_inc;

	process(clk)
    begin
		if (clk'event and clk='1') then
			if (cycle_start='1') then
				mem_addr <= l_adro(9 downto 2);
			elsif (mem_inc='1') then
				mem_addr <= mem_addr + 1;
			end if;
		end if;
    end process;

	process(clk)
    begin
		if (clk'event and clk='1') then
			if (mem_wr_enable='1') then
				mem_data(conv_integer(mem_addr)) <= l_dato;
			end if;
		end if;
    end process;

	mem_rdata <= mem_data(conv_integer(mem_addr));

    process(clk)
    begin
		if (clk'event and clk='1') then
			if (mem_rd_inc='1') then
				mem_rd_data <= mem_rdata;
			end if;
		end if;
    end process;

end rtl;