library ieee;
use ieee.std_logic_1164.all;

entity adder_4bit is

	port
	(
		-- Input ports
		a	: in  std_logic_vector(3 downto 0);
		b 	: in  std_logic_vector(3 downto 0);
	   cin : in  std_logic;


		-- Output ports
		s	: out std_logic_vector(3 downto 0);
		cout	: out std_logic
	);
end adder_4bit;


architecture structural of adder_4bit is
signal carries: std_logic_vector(4 downto 0);


component fulladder is

	port
	(
		-- Input ports
		a	: in  std_logic;
		b 	: in  std_logic;
	   cin : in  std_logic;


		-- Output ports
		s	: out std_logic;
		cout	: out std_logic
	);
end component;
begin
	carries(0)<=cin;
--	FA0: fulladder port map( a(0),b(0),carries(0),s(0),carries(1));
--	FA1: fulladder port map( a(1),b(1),carries(1),s(1),carries(1));
--	FA2: fulladder port map( a(2),b(2),carries(2),s(2),carries(2));
--	FA3: fulladder port map( a(3),b(3),carries(3),s(3),carries(3));
	FAi: for i in 3 downto 0 generate
		FA: fulladder port map(a(i),b(i),carries(i),s(i),carries(i+1));
	end generate;

	cout<=carries(4);
end structural;


test bench:



LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY adder_4bit_vhd_tst IS
END adder_4bit_vhd_tst;
ARCHITECTURE adder_4bit_arch OF adder_4bit_vhd_tst IS
-- constants
-- signals
SIGNAL a : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cin : STD_LOGIC;
SIGNAL cout : STD_LOGIC;
SIGNAL s : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT adder_4bit
	PORT (
	a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	cin : IN STD_LOGIC;
	cout : OUT STD_LOGIC;
	s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	i1 : adder_4bit
	PORT MAP (
-- list connections between master ports and signals
	a => a,
	b => b,
	cin => cin,
	cout => cout,
	s => s
	);

always : PROCESS

-- (        )
-- variable declarations
BEGIN
  a<="0101";
b<="1111";
cin<='0'
wait for 1 ns;
a<=x"A";
wait for 1 ns;
b<=x"1";
WAIT;
END PROCESS always;
END adder_4bit_arch;