module ram128x16(
  input [6:0] adrs,
  inout [15:0] data,
  input _ce, _we, _oe

);
  reg [3:0] _cee;

  ram64x8 u1(adrs[5:0], data[15:8], _cee[0], _we, _oe);
  ram64x8 u2(adrs[5:0], data[7:0], _cee[1], _we, _oe);
  ram64x8 u3(adrs[5:0], data[15:8], _cee[2], _we, _oe);
  ram64x8 u4(adrs[5:0], data[7:0], _cee[3], _we, _oe);
  //1 - to - 2 decode
  always @ (*)
begin
    if(_ce == 0)
      case(adrs[6])
    0: _cee = 4'b0011;
    1: _cee = 4'b1100;
    default: _cee = 4'hf;
    endcase
    else
        _cee = 4'hf;
end
  endmodule

module ram64x8(
    input [5:0] adrs,
    inout [7:0] data,
    input _ce, _we, _oe
);
  reg [3:0] _cee;
ram16x8 u1(adrs[3:0], data, _cee[0], _we, _oe);
ram16x8 u2(adrs[3:0], data, _cee[1], _we, _oe);
ram16x8 u3(adrs[3:0], data, _cee[2], _we, _oe);
ram16x8 u4(adrs[3:0], data, _cee[3], _we, _oe);
//2 - to - 4 decode
always @ (*)
begin
    if(_ce == 0)
    case(adrs[5:4])
    0: _cee = 4'b1110;
    1: _cee = 4'b1101;
    2: _cee = 4'b1011;
    3: _cee = 4'b0111;
    default: _cee = 4'hf;
    endcase
    else
        _cee = 4'hf;
end
endmodule

module ram16x8(
    input [3:0] adrs,
    inout [7:0] data,
    input _ce, _we, _oe
);

	ram16x4 u1(adrs, data[7:4], data[7:4], _ce, _we, _oe);
	ram16x4 u2(adrs, data[3:0], data[3:0], _ce, _we, _oe);

endmodule

module ram16x4(
    input [3:0] adrs,
    input [3:0] dataIn,
    output [3:0] dataOut,
    input _ce, _we, _oe
);
  reg [3:0] mem[0:15]; // 16 X 4 ram
assign dataOut = ~_ce & _we & ~_oe ? mem[adrs]:4'hz;
always@(*)
begin
if(_ce==0)
    if(_we == 0 && _oe ==1)
        mem[adrs] = dataIn;
end
endmodule