-------------------------------------------------------------------------------
--
-- Title       : JKtrigg
-- Design      : lab5
-- Author      : ivan
-- Company     : lala
--
-------------------------------------------------------------------------------
--
-- File        : JKtrigg.vhd
-- Generated   : Sun May 27 19:12:23 2018
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {JKtrigg} architecture {JKtrigg}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity JKtrigg is
	 port(
		 Sa : in STD_LOGIC;
		 J : in STD_LOGIC;
		 K : in STD_LOGIC;
		 C : in STD_LOGIC;
		 Ra : in STD_LOGIC;
		 Q : out STD_LOGIC;
		 nQ : out STD_LOGIC
	     );
end JKtrigg;

--}} End of automatically maintained section

architecture JKtrigg of JKtrigg is
signal S1, S2, S3, S4, S5, S6, S7, S8:STD_LOGIC;
component and3 is
	 port(
		 x1 : in STD_LOGIC;
		 x2 : in STD_LOGIC;
		 x3 : in STD_LOGIC;
		 y : out STD_LOGIC
	     );
end component and3;
begin

	-- enter your statements here --
	and3_1: and3 port map(S8, J, C, S1);
	and3_2: and3 port map(C, S7, K, S2);
	and3_3: and3 port map(Sa, S1, S4, S3);
	and3_4: and3 port map(S3, S2, Ra, S4);
	and3_5: and3 port map(S1, S3, S2, S5);
	and3_6: and3 port map(S2, S4, S1, S6);
	and3_7: and3 port map(Sa, S5, S8, S7);
	and3_8: and3 port map(S7, S6, Ra, S8);
	Q <= S7;
	nQ <= S8;
end JKtrigg;