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fsm.v

a guest Jun 20th, 2019 130 Never
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  1. module FSM (
  2.   CLK,
  3.   INPUT_0,
  4.   INPUT_1,
  5.   INPUT_2,
  6.   INPUT_3,
  7.   INPUT_4,
  8.   OUTPUT_0,
  9.   OUTPUT_1
  10.  ) ;
  11.   input CLK ;
  12.   input INPUT_0 ;
  13.   input INPUT_1 ;
  14.   input INPUT_2 ;
  15.   input INPUT_3 ;
  16.   input INPUT_4 ;
  17.   output OUTPUT_0 ;
  18.   output OUTPUT_1 ;
  19.   wire CLK_BUF ;
  20.   wire CLK_BUF_BUF ;
  21.   wire FSM_sequential_STATE_REG_0_i_2_n_0 ;
  22.   wire FSM_sequential_STATE_REG_0_i_3_n_0 ;
  23.   wire FSM_sequential_STATE_REG_1_i_2_n_0 ;
  24.   wire FSM_sequential_STATE_REG_1_i_3_n_0 ;
  25.   wire INPUT_BUF_0 ;
  26.   wire INPUT_BUF_1 ;
  27.   wire INPUT_BUF_2 ;
  28.   wire INPUT_BUF_3 ;
  29.   wire INPUT_BUF_4 ;
  30.   wire NEXT_STATE_S_0 ;
  31.   wire NEXT_STATE_S_1 ;
  32.   wire OUTPUT_BUF_0 ;
  33.   wire OUTPUT_BUF_1 ;
  34.   wire STATE_REG_0 ;
  35.   wire STATE_REG_1 ;
  36.   wire const0 ;
  37.   wire const1 ;
  38. BUF CLK_BUF_BUF_inst_inst (
  39.   .\I (CLK_BUF ),
  40.   .\O (CLK_BUF_BUF )
  41.  ) ;
  42. BUF CLK_BUF_inst_inst (
  43.   .\I (CLK ),
  44.   .\O (CLK_BUF )
  45.  ) ;
  46. LUT6 #(.INIT(64'hc8ccccccfccccccc))
  47. FSM_sequential_STATE_REG_0_i_2_inst (
  48.   .\I0 (INPUT_BUF_3 ),
  49.   .\I1 (STATE_REG_0 ),
  50.   .\I2 (INPUT_BUF_1 ),
  51.   .\I3 (INPUT_BUF_4 ),
  52.   .\I4 (INPUT_BUF_0 ),
  53.   .\I5 (INPUT_BUF_2 ),
  54.   .\O (FSM_sequential_STATE_REG_0_i_2_n_0 )
  55.  ) ;
  56. LUT6 #(.INIT(64'haaaaabaaaaaaaa8a))
  57. FSM_sequential_STATE_REG_0_i_3_inst (
  58.   .\I0 (STATE_REG_0 ),
  59.   .\I1 (INPUT_BUF_1 ),
  60.   .\I2 (INPUT_BUF_4 ),
  61.   .\I3 (INPUT_BUF_3 ),
  62.   .\I4 (INPUT_BUF_0 ),
  63.   .\I5 (INPUT_BUF_2 ),
  64.   .\O (FSM_sequential_STATE_REG_0_i_3_n_0 )
  65.  ) ;
  66. LUT6 #(.INIT(61'h0a00000004000000))
  67. FSM_sequential_STATE_REG_1_i_2_inst (
  68.   .\I0 (STATE_REG_0 ),
  69.   .\I1 (INPUT_BUF_1 ),
  70.   .\I2 (INPUT_BUF_3 ),
  71.   .\I3 (INPUT_BUF_4 ),
  72.   .\I4 (INPUT_BUF_0 ),
  73.   .\I5 (INPUT_BUF_2 ),
  74.   .\O (FSM_sequential_STATE_REG_1_i_2_n_0 )
  75.  ) ;
  76. LUT6 #(.INIT(64'hfdffffffffbfffdf))
  77. FSM_sequential_STATE_REG_1_i_3_inst (
  78.   .\I0 (STATE_REG_0 ),
  79.   .\I1 (INPUT_BUF_1 ),
  80.   .\I2 (INPUT_BUF_4 ),
  81.   .\I3 (INPUT_BUF_3 ),
  82.   .\I4 (INPUT_BUF_0 ),
  83.   .\I5 (INPUT_BUF_2 ),
  84.   .\O (FSM_sequential_STATE_REG_1_i_3_n_0 )
  85.  ) ;
  86. FFR #(.INIT(1'h0))
  87. FSM_sequential_STATE_REG_reg_0_inst (
  88.   .\C (CLK_BUF_BUF ),
  89.   .\CE (const1 ),
  90.   .\D (NEXT_STATE_S_0 ),
  91.   .\R (const0 ),
  92.   .\Q (STATE_REG_0 )
  93.  ) ;
  94. MUX FSM_sequential_STATE_REG_reg_0_i_1_inst (
  95.   .\I0 (FSM_sequential_STATE_REG_0_i_2_n_0 ),
  96.   .\I1 (FSM_sequential_STATE_REG_0_i_3_n_0 ),
  97.   .\S (STATE_REG_1 ),
  98.   .\O (NEXT_STATE_S_0 )
  99.  ) ;
  100. FFR #(.INIT(1'h0))
  101. FSM_sequential_STATE_REG_reg_1_inst (
  102.   .\C (CLK_BUF_BUF ),
  103.   .\CE (const1 ),
  104.   .\D (NEXT_STATE_S_1 ),
  105.   .\R (const0 ),
  106.   .\Q (STATE_REG_1 )
  107.  ) ;
  108. GND GND_inst (
  109.   .\O (const0 )
  110.  ) ;
  111. MUX FSM_sequential_STATE_REG_reg_1_i_1_inst (
  112.   .\I0 (FSM_sequential_STATE_REG_1_i_2_n_0 ),
  113.   .\I1 (FSM_sequential_STATE_REG_1_i_3_n_0 ),
  114.   .\S (STATE_REG_1 ),
  115.   .\O (NEXT_STATE_S_1 )
  116.  ) ;
  117. BUF INPUT_BUF_0_inst_inst (
  118.   .\I (INPUT_0 ),
  119.   .\O (INPUT_BUF_0 )
  120.  ) ;
  121. BUF INPUT_BUF_1_inst_inst (
  122.   .\I (INPUT_1 ),
  123.   .\O (INPUT_BUF_1 )
  124.  ) ;
  125. BUF INPUT_BUF_2_inst_inst (
  126.   .\I (INPUT_2 ),
  127.   .\O (INPUT_BUF_2 )
  128.  ) ;
  129. BUF INPUT_BUF_3_inst_inst (
  130.   .\I (INPUT_3 ),
  131.   .\O (INPUT_BUF_3 )
  132.  ) ;
  133. BUF INPUT_BUF_4_inst_inst (
  134.   .\I (INPUT_4 ),
  135.   .\O (INPUT_BUF_4 )
  136.  ) ;
  137. BUF OUTPUT_BUF_0_inst_inst (
  138.   .\I (OUTPUT_BUF_0 ),
  139.   .\O (OUTPUT_0 )
  140.  ) ;
  141. LUT1 #(.INIT(1'h1))
  142. OUTPUT_BUF_0_inst_i_1_inst (
  143.   .\I0 (STATE_REG_0 ),
  144.   .\O (OUTPUT_BUF_0 )
  145.  ) ;
  146. BUF OUTPUT_BUF_1_inst_inst (
  147.   .\I (OUTPUT_BUF_1 ),
  148.   .\O (OUTPUT_1 )
  149.  ) ;
  150. LUT2 #(.INIT(3'h6))
  151. OUTPUT_BUF_1_inst_i_1_inst (
  152.   .\I0 (STATE_REG_1 ),
  153.   .\I1 (STATE_REG_0 ),
  154.   .\O (OUTPUT_BUF_1 )
  155.  ) ;
  156. VCC VCC_inst (
  157.   .\O (const1 )
  158.  ) ;
  159. endmodule
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