VSRCS= \
       testbench.v \
       xupv5_top.v \
       mig_v3_61/user_design/sim/ddr2_model.v \
       mig_v3_61/user_design/rtl/ddr2_chipscope.v \
       mig_v3_61/user_design/rtl/ddr2_ctrl.v \
       mig_v3_61/user_design/rtl/ddr2_idelay_ctrl.v \
       mig_v3_61/user_design/rtl/ddr2_infrastructure.v \
       mig_v3_61/user_design/rtl/ddr2_mem_if_top.v \
       mig_v3_61/user_design/rtl/ddr2_phy_calib.v \
       mig_v3_61/user_design/rtl/ddr2_phy_ctl_io.v \
       mig_v3_61/user_design/rtl/ddr2_phy_dm_iob.v \
       mig_v3_61/user_design/rtl/ddr2_phy_dq_iob.v \
       mig_v3_61/user_design/rtl/ddr2_phy_dqs_iob.v \
       mig_v3_61/user_design/rtl/ddr2_phy_init.v \
       mig_v3_61/user_design/rtl/ddr2_phy_io.v \
       mig_v3_61/user_design/rtl/ddr2_phy_top.v \
       mig_v3_61/user_design/rtl/ddr2_phy_write.v \
       mig_v3_61/user_design/rtl/ddr2_top.v \
       mig_v3_61/user_design/rtl/ddr2_usr_addr_fifo.v \
       mig_v3_61/user_design/rtl/ddr2_usr_rd.v \
       mig_v3_61/user_design/rtl/ddr2_usr_top.v \
       mig_v3_61/user_design/rtl/ddr2_usr_wr.v \
       mig_v3_61/user_design/rtl/mig_v3_61.v

TOPMODULE=testbench

WORKPATH=work
VOBJS=$(patsubst %.v,$(WORKPATH)/%, $(VSRCS))

VLOGFLAGS=+acc -vopt +incdir+mig_v3_61/user_design/sim/

sim: $(VOBJS)
    vsim -c -lib $(WORKPATH) $(TOPMODULE)

$(WORKPATH)/%: %.v $(WORKPATH)
    echo $(VOBJS)
    vlog $(VLOGFLAGS) -work $(WORKPATH) $<

$(WORKPATH):
    vlib $(WORKPATH)

clean:
    rm -rf $(WORKPATH)